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boards: frdm_mcxn236: add frdm_mcxn236 board

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add frdm_mcxn236 board support

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
This commit is contained in:
Neil Chen 2024-08-07 14:21:33 +08:00 • committed by Fabio Baltieri
commit a42e10fb73
13 changed files with 812 additions and 0 deletions
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boards/nxp/frdm_mcxn236/CMakeLists.txt Normal file
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#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_library()
zephyr_library_sources(board.c)

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# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config BOARD_INIT_PRIORITY
int "Board initialization priority"
default 1
help
Board initialization priority.

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boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236 Normal file
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# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config BOARD_FRDM_MCXN236
select SOC_MCXN236
select SOC_PART_NUMBER_MCXN236VDF

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/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <fsl_spc.h>
#include <soc.h>
/* Board xtal frequency in Hz */
#define BOARD_XTAL0_CLK_HZ 24000000U
/* Core clock frequency: 150MHz */
#define CLOCK_INIT_CORE_CLOCK 150000000U
/* System clock frequency. */
extern uint32_t SystemCoreClock;
static void enable_lpcac(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK |
SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK);
}
/* Update Active mode voltage for OverDrive mode. */
void power_mode_od(void)
{
/* Set the DCDC VDD regulator to 1.2 V voltage level */
spc_active_mode_dcdc_option_t opt = {
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
};
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
spc_active_mode_core_ldo_option_t ldo_opt = {
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
};
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
spc_sram_voltage_config_t cfg = {
.operateVoltage = kSPC_sramOperateAt1P2V,
.requestVoltageUpdate = true,
};
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
}
static int frdm_mcxn236_init(void)
{
enable_lpcac();
power_mode_od();
/* Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
/* FRO OSC setup - begin, enable the FRO for safety switching */
/* Switch to FRO 12M first to ensure we can change the clock setting */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
/* Enable FRO HF(48MHz) output */
CLOCK_SetupFROHFClocking(48000000U);
/* Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
/* Configure PLL0 to the desired values */
CLOCK_SetPLL0Freq(&pll0Setup);
/* PLL0 Monitor is disabled */
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
/* Switch MAIN_CLK to PLL0 */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
/* Set AHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom5Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay)
CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
CLOCK_EnableClock(kCLOCK_Gpio0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
CLOCK_EnableClock(kCLOCK_Gpio1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
CLOCK_EnableClock(kCLOCK_Gpio2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
CLOCK_EnableClock(kCLOCK_Gpio3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
CLOCK_EnableClock(kCLOCK_Gpio4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
CLOCK_EnableClock(kCLOCK_Gpio5);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(wwdt0), okay)
CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER4);
#endif
/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
return 0;
}
SYS_INIT(frdm_mcxn236_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);

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#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
board_runner_args(jlink "--device=MCXN236" "--reset-after-load")
board_runner_args(linkserver "--device=MCXN236:FRDM-MCXN236")
board_runner_args(linkserver "--core=cm33_core0")
board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXNxxx_S.cfx")
board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000")
# Linkserver v1.4.85 and earlier do not include the secure regions in the
# MCXN236 memory map, so we add them here
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
\"size\":\"0x00040000\",\"type\":\"RAM\"\}")
# Define region for peripherals
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
\"size\":\"0x00140000\",\"type\":\"RAM\"\}")
# Pyocd support added with the NXP.MCXN236_DFP.17.0.0.pack CMSIS Pack
board_runner_args(pyocd "--target=mcxn236")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

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board:
name: frdm_mcxn236
vendor: nxp
socs:
- name: mcxn236

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.. _frdm_mcxn236:
NXP FRDM-MCXN236
################
Overview
********
FRDM-MCXN236 are compact and scalable development boards for rapid prototyping of
MCX N23X MCUs. They offer industry standard headers for easy access to the
MCUs I/Os, integrated open-standard serial interfaces, external flash memory and
an on-board MCU-Link debugger. MCX N Series are high-performance, low-power
microcontrollers with intelligent peripherals and accelerators providing multi-tasking
capabilities and performance efficiency.
.. image:: frdm_mcxn236.webp
:align: center
:alt: FRDM-MCXN236
Hardware
********
- MCX-N236 Arm Cortex-M33 microcontroller running at 150 MHz
- 1MB dual-bank on chip Flash
- 352 KB RAM
- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors
- 8x LP Flexcomms each supporting SPI, I2C, UART
- 2x FlexCAN with FD, 2x I3Cs, 2x SAI
- On-board MCU-Link debugger with CMSIS-DAP
- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS
For more information about the MCX-N236 SoC and FRDM-MCXN236 board, see:
- `MCX-N236 SoC Website`_
- `MCX-N236 Datasheet`_
- `MCX-N236 Reference Manual`_
- `FRDM-MCXN236 Website`_
- `FRDM-MCXN236 User Guide`_
- `FRDM-MCXN236 Board User Manual`_
- `FRDM-MCXN236 Schematics`_
Supported Features
==================
The FRDM-MCXN236 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
Targets available
==================
The default configuration file
:zephyr_file:`boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The MCX-N236 SoC has 6 gpio controllers and has pinmux registers which
can be used to configure the functionality of a pin.
+------------+-----------------+----------------------------+
| Name | Function | Usage |
+============+=================+============================+
| P0_PIO1_8 | UART | UART RX |
+------------+-----------------+----------------------------+
| P1_PIO1_9 | UART | UART TX |
+------------+-----------------+----------------------------+
System Clock
============
The MCX-N236 SoC is configured to use PLL0 running at 150MHz as a source for
the system clock.
Serial Port
===========
The FRDM-MCXN236 SoC has 8 FLEXCOMM interfaces for serial communication.
Flexcomm 4 is configured as UART for the console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
Using LinkServer
----------------
Linkserver is the default runner for this board, and supports the factory
default MCU-Link firmware. Follow the instructions in
:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
firmware. This only needs to be done if the default onboard debug circuit
firmware was changed. To put the board in ``DFU mode`` to program the firmware,
short jumper JP5.
Using J-Link
------------
There are two options. The onboard debug circuit can be updated with Segger
J-Link firmware by following the instructions in
:ref:`mcu-link-jlink-onboard-debug-probe`.
To be able to program the firmware, you need to put the board in ``DFU mode``
by shortening the jumper JP5.
The second option is to attach a :ref:`jlink-external-debug-probe` to the
10-pin SWD connector (J12) of the board. Additionally, the jumper JP7 must
be shortened.
For both options use the ``-r jlink`` option with west to use the jlink runner.
.. code-block:: console
west flash -r jlink
Configuring a Console
=====================
Connect a USB cable from your PC to J10, and use the serial terminal of your choice
(minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_mcxn236
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxn236/mcxn236
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_mcxn236/mcxn236
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxn236/mcxn236
.. _MCX-N236 SoC Website:
https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n23x-highly-integrated-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N23X
.. _MCX-N236 Datasheet:
https://www.nxp.com/docs/en/data-sheet/MCXN23x.pdf
.. _MCX-N236 Reference Manual:
https://www.nxp.com/docs/en/reference-manual/MCXN23xRM.pdf
.. _FRDM-MCXN236 Website:
https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-n23x-mcus:FRDM-MCXN236
.. _FRDM-MCXN236 User Guide:
https://www.nxp.com/document/guide/getting-started-with-frdm-mcxn236:GS-FRDM-MCXN236
.. _FRDM-MCXN236 Board User Manual:
https://www.nxp.com/docs/en/user-manual/UM12041.pdf
.. _FRDM-MCXN236 Schematics:
https://www.nxp.com/webapp/Download?colCode=SPF-90828

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/*
* Copyright 2024 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/mcx/MCXN236VDF-pinctrl.h>
&pinctrl {
pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart {
group0 {
pinmux = <FC2_P2_PIO4_2>,
<FC2_P3_PIO4_3>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c {
group0 {
pinmux = <FC2_P0_PIO4_0>,
<FC2_P1_PIO4_1>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};
pinmux_flexcomm3_lpspi: pinmux_flexcomm3_lpspi {
group0 {
pinmux = <FC3_P0_PIO1_0>,
<FC3_P1_PIO1_1>,
<FC3_P2_PIO1_2>,
<FC3_P3_PIO1_3>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
group0 {
pinmux = <FC4_P0_PIO1_8>,
<FC4_P1_PIO1_9>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm5_lpi2c: pinmux_flexcomm5_lpi2c {
group0 {
pinmux = <FC5_P0_PIO1_16>,
<FC5_P1_PIO1_17>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};
pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 {
group0 {
pinmux = <PWM1_A0_PIO3_12>,
<PWM1_B0_PIO2_7>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 {
group0 {
pinmux = <PWM1_A1_PIO3_14>,
<PWM1_B1_PIO3_15>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 {
group0 {
pinmux = <PWM1_A2_PIO3_16>,
<PWM1_B2_PIO3_17>;
slew-rate = "fast";
drive-strength = "low";
};
};
};

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/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nxp/nxp_mcxn23x.dtsi>
#include "frdm_mcxn236.dtsi"
/ {
model = "NXP FRDM_N236 board";
compatible = "nxp,mcxn236", "nxp,mcx";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash;
zephyr,flash-controller = &fmu;
zephyr,code-partition = &slot0_partition;
zephyr,console = &flexcomm4_lpuart4;
zephyr,shell-uart = &flexcomm4_lpuart4;
};
aliases{
watchdog0 = &wwdt0;
pwm-0 = &flexpwm1_pwm0;
};
};
&sram0 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(192)>;
};
&gpio4 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&edma0 {
status = "okay";
};
&flexcomm2 {
status = "okay";
};
/*
* LPFLEXCOMM supports UART and I2C on the same instance, enable this for
* LFLEXCOMM2
*/
&flexcomm2_lpuart2 {
status = "okay";
};
&flexcomm2_lpi2c2 {
status = "okay";
};
&flexcomm3 {
status = "okay";
};
&flexcomm3_lpspi3 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&flexcomm4_lpuart4 {
status = "okay";
};
&flexcomm5 {
status = "okay";
};
&flexcomm5_lpi2c5 {
status = "okay";
};
&wwdt0 {
status = "okay";
};
&flexpwm1_pwm0 {
status = "okay";
};
&ctimer0 {
status = "okay";
};

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/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "frdm_mcxn236-pinctrl.dtsi"
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases{
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
blue_led: led_2 {
gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
red_led: led_3 {
gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_WAKEUP>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&flexcomm2_lpuart2 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm2_lpuart>;
pinctrl-names = "default";
};
&flexcomm2_lpi2c2 {
pinctrl-0 = <&pinmux_flexcomm2_lpi2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
&flexcomm3_lpspi3 {
pinctrl-0 = <&pinmux_flexcomm3_lpspi>;
pinctrl-names = "default";
};
&flexcomm4_lpuart4 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
pinctrl-names = "default";
};
&flexcomm5_lpi2c5 {
pinctrl-0 = <&pinmux_flexcomm5_lpi2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
/*
* MCXN236 board uses OS timer as the kernel timer
* In case we need to switch to SYSTICK timer, then
* replace &os_timer with &systick
*/
&os_timer {
status = "disabled";
};
&systick {
status = "okay";
};
&flash {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
/* Note slot 0 has one additional sector,
* this is intended for use with the swap move algorithm
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(480)>;
};
slot1_partition: partition@80000 {
label = "image-1";
reg = <0x0088000 DT_SIZE_K(472)>;
};
};
};
&flexpwm1_pwm0 {
pinctrl-0 = <&pinmux_flexpwm1_pwm0>;
pinctrl-names = "default";
};

25
boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml Normal file
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@ -0,0 +1,25 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
identifier: frdm_mcxn236
name: NXP FRDM MCXN236
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- dma
- gpio
- spi
- i2c
- watchdog
- pwm
- counter
vendor: nxp

18
boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig Normal file
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@ -0,0 +1,18 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y