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soc: arm: cypress: Fix psoc6 irq priority

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PSoC-6 have different priority bit masks for cortex-m0+ and cortex-m4.

M0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel)
M4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel)

The current macro that gets priority level value from devicetree apply
same value from cortex-m4 on cortex-m0+.  This add missing indirection
to get from intmux node the correct cortex-m0+ priority level value.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2021-08-11 08:09:27 -03:00 • committed by Christopher Friedt
commit a42890fb39
1 changed files with 6 additions and 2 deletions
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6
soc/arm/cypress/common/cypress_psoc6_dt.h
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@ -66,6 +66,9 @@
(CY_PSOC6_IRQ_CONFIG(n, isr)))
#define CY_PSOC6_NVIC_MUX_IRQN(n) DT_IRQN(DT_INST_PHANDLE_BY_IDX(n,\
interrupt_parent, 0))
#define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_IRQ(DT_INST_PHANDLE_BY_IDX(n,\
interrupt_parent, 0), priority)
/*
* DT_INST_PROP_BY_IDX should be used get interrupt and configure, instead
* DT_INST_IRQN. The DT_INST_IRQN return IRQ number with level translation,
@ -86,13 +89,14 @@
*/
#define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) CY_PSOC6_IRQ_CONFIG(n, isr)
#define CY_PSOC6_NVIC_MUX_IRQN(n) DT_INST_IRQN(n)
#define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_INST_IRQ(n, priority)
#define CY_PSOC6_NVIC_MUX_MAP(n)
#endif
#define CY_PSOC6_IRQ_CONFIG(n, isr) \
do { \
IRQ_CONNECT(CY_PSOC6_NVIC_MUX_IRQN(n), \
DT_INST_IRQ(n, priority), \
CY_PSOC6_NVIC_MUX_IRQ_PRIO(n),\
isr, DEVICE_DT_INST_GET(n), 0);\
CY_PSOC6_NVIC_MUX_MAP(n); \
irq_enable(CY_PSOC6_NVIC_MUX_IRQN(n)); \