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drivers: eth: mcux: Fix PHY access in eth_mcux_phy_setup

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It is necessary to poll the ENET_EIR_MII bit before reading
the data register as explained in the i.MX RT1060 reference
manual in chapter 41.7.17.4.
Use PHY_* functions from NXP HAL to correctly access the PHY
registers.

Signed-off-by: Armand Ciejak <armandciejak@users.noreply.github.com>
This commit is contained in:
Armand Ciejak 2020-03-06 10:59:00 +01:00 • committed by Johan Hedberg
commit a3d413c51a
1 changed files with 18 additions and 9 deletions
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27
drivers/ethernet/eth_mcux.c
View file

@ -399,18 +399,27 @@ static void eth_mcux_phy_setup(void)
{
#ifdef CONFIG_SOC_SERIES_IMX_RT
const u32_t phy_addr = 0U;
u32_t status;
status_t res;
u32_t status_reg;
/* Disable MII interrupts to prevent triggering PHY events. */
ENET_DisableInterrupts(ENET, ENET_EIR_MII_MASK);
/* Prevent PHY entering NAND Tree mode override*/
ENET_StartSMIRead(ENET, phy_addr, PHY_OMS_STATUS_REG,
kENET_MiiReadValidFrame);
status = ENET_ReadSMIData(ENET);
if (status & PHY_OMS_NANDTREE_MASK) {
status &= ~PHY_OMS_NANDTREE_MASK;
ENET_StartSMIWrite(ENET, phy_addr, PHY_OMS_OVERRIDE_REG,
kENET_MiiWriteValidFrame, status);
res = PHY_Read(ENET, phy_addr, PHY_OMS_STATUS_REG, &status_reg);
if (res != kStatus_Success) {
LOG_WRN("Reading PHY register failed with status 0x%x", res);
} else {
if (status_reg & PHY_OMS_NANDTREE_MASK) {
status_reg &= ~PHY_OMS_NANDTREE_MASK;
res = PHY_Write(ENET, phy_addr, PHY_OMS_OVERRIDE_REG, status_reg);
if (res != kStatus_Success) {
LOG_WRN("Writing PHY register failed with status 0x%x", res);
}
}
}
ENET_EnableInterrupts(ENET, ENET_EIR_MII_MASK);
#endif
}