boards: add support for HiFive Unmatched

This patch adds new support for SiFive HiFive Unmatched which has
SiFive FU740 SoC, DDR and some peripherals.

This is first version so not support all features on the board.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>

boards/riscv/hifive_unmatched/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 Katsuhiro Suzuki
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_HIFIVE_UNMATCHED
+	bool "HiFive Unmatched target"
+	depends on SOC_RISCV_SIFIVE_FU740

boards/riscv/hifive_unmatched/Kconfig.defconfig

@@ -0,0 +1,23 @@
+# Copyright (c) 2021 Katsuhiro Suzuki
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_HIFIVE_UNMATCHED
+
+config BOARD
+	default "hifive_unmatched"
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1000000
+
+config SPI_SIFIVE
+	default y
+	depends on SPI
+
+config UART_SIFIVE
+	default y
+	depends on SERIAL
+
+endif

boards/riscv/hifive_unmatched/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+set(OPENOCD_USE_LOAD_IMAGE NO)
+
+board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_hifive_unmatched.cfg")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/riscv/hifive_unmatched/doc/index.rst

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+.. _hifive_unmatched:
+
+SiFive HiFive Unmatched
+#######################
+
+Overview
+********
+
+The HiFive Unmatched is a development board with a SiFive FU740-C000
+multi-core 64bit RISC-V SoC.
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``hifive_unmatched`` board configuration can be built as
+usual (see :ref:`build_an_application`) using the corresponding board name:
+
+.. zephyr-app-commands::
+   :board: hifive_unmatched
+   :goals: build
+
+Flashing
+========
+
+Current version has not yet supported flashing binary to onboard Flash ROM.
+
+This board has USB-JTAG interface and this can be used with OpenOCD.
+Load applications on DDR and run as follows:
+
+.. code-block:: console
+
+   openocd -c 'bindto 0.0.0.0' \
+           -f boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg
+   riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
+   (gdb) target remote :3333
+   (gdb) c
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.

boards/riscv/hifive_unmatched/hifive_unmatched.dts

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+/*
+ * Copyright (c) 2021 Katsuhiro Suzuki
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <riscv64-fu740.dtsi>
+
+/ {
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &l2lim;
+	};
+
+	ram0: ram0@80000000 {
+		compatible = "memory";
+		reg = <0x80000000 0xf0000000>;
+		reg-names = "mem";
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <125125000>;
+};
+
+&spi0 {
+	status = "okay";
+	clock-frequency = <125125000>;
+
+	reg = <0x10040000 0x1000 0x20000000 0x2000000>;
+	flash0: flash@0 {
+		compatible = "issi,is25wp256d", "jedec,spi-nor";
+		size = <33554432>;
+		label = "FLASH0";
+		jedec-id = [96 60 18];
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+	clock-frequency = <125125000>;
+};
+
+&spi2 {
+	status = "okay";
+	clock-frequency = <125125000>;
+};

boards/riscv/hifive_unmatched/hifive_unmatched.yaml

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+identifier: hifive_unmatched
+name: SiFive HiFive Unmatched
+type: mcu
+arch: riscv64
+toolchain:
+  - zephyr
+ram: 3840
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+supported:
+  - spi

boards/riscv/hifive_unmatched/hifive_unmatched_defconfig

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+CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y
+CONFIG_SOC_RISCV_SIFIVE_FU740=y
+CONFIG_BOARD_HIFIVE_UNMATCHED=y
+CONFIG_RISCV_MACHINE_TIMER=y
+CONFIG_PLIC=y
+CONFIG_CONSOLE=y
+CONFIG_PRINTK=y
+CONFIG_SPI=y
+CONFIG_SPI_SIFIVE=y
+CONFIG_SERIAL=y
+CONFIG_UART_SIFIVE=y
+CONFIG_UART_SIFIVE_PORT_0=y
+CONFIG_UART_CONSOLE=y
+CONFIG_BOOT_BANNER=y
+CONFIG_XIP=n

boards/riscv/hifive_unmatched/support/openocd_hifive_unleashed.cfg

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+adapter speed 10000
+
+adapter driver ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
+target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
+target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
+target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
+target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
+target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
+
+flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000