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drivers: pinctrl: rename nxp,kinetis-pinctrl to nxp,port-pinctrl

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The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.

Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver

Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2024-11-19 12:46:56 -06:00 • committed by Mahesh Mahadevan
commit a36c7ddb36
26 changed files with 123 additions and 126 deletions
Download patch file Download diff file Expand all files Collapse all files

2
MAINTAINERS.yml
View file

@ -3680,7 +3680,7 @@ NXP Drivers:
- drivers/*/*.mcux - drivers/*/*.mcux
- drivers/*/*.nxp - drivers/*/*.nxp
- drivers/*/*nxp* - drivers/*/*nxp*
- drivers/*/*kinetis* - drivers/*/*/*kinetis*
- drivers/misc/*/nxp* - drivers/misc/*/nxp*
- include/zephyr/dt-bindings/*/*nxp* - include/zephyr/dt-bindings/*/*nxp*
- include/zephyr/dt-bindings/*/*mcux* - include/zephyr/dt-bindings/*/*mcux*

4
drivers/clock_control/clock_control_mcux_syscon.c
View file

@ -44,7 +44,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
} }
#endif #endif
#if defined(CONFIG_PINCTRL_NXP_KINETIS) #if defined(CONFIG_PINCTRL_NXP_PORT)
switch ((uint32_t)sub_system) { switch ((uint32_t)sub_system) {
#if defined(CONFIG_SOC_SERIES_MCXA) #if defined(CONFIG_SOC_SERIES_MCXA)
case MCUX_PORT0_CLK: case MCUX_PORT0_CLK:
@ -82,7 +82,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
default: default:
break; break;
} }
#endif /* defined(CONFIG_PINCTRL_NXP_KINETIS) */ #endif /* defined(CONFIG_PINCTRL_NXP_PORT) */
#ifdef CONFIG_ETH_NXP_ENET_QOS #ifdef CONFIG_ETH_NXP_ENET_QOS
if ((uint32_t)sub_system == MCUX_ENET_QOS_CLK) { if ((uint32_t)sub_system == MCUX_ENET_QOS_CLK) {

2
drivers/pinctrl/CMakeLists.txt
View file

@ -15,7 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_PORT pinctrl_nxp_port.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)

2
drivers/pinctrl/Kconfig
View file

@ -44,7 +44,7 @@ source "drivers/pinctrl/Kconfig.rpi_pico"
source "drivers/pinctrl/Kconfig.sam" source "drivers/pinctrl/Kconfig.sam"
source "drivers/pinctrl/Kconfig.sam0" source "drivers/pinctrl/Kconfig.sam0"
source "drivers/pinctrl/Kconfig.stm32" source "drivers/pinctrl/Kconfig.stm32"
source "drivers/pinctrl/Kconfig.kinetis" source "drivers/pinctrl/Kconfig.nxp_port"
source "drivers/pinctrl/Kconfig.xec" source "drivers/pinctrl/Kconfig.xec"
source "drivers/pinctrl/Kconfig.imx" source "drivers/pinctrl/Kconfig.imx"
source "drivers/pinctrl/Kconfig.sifive" source "drivers/pinctrl/Kconfig.sifive"

9
drivers/pinctrl/Kconfig.kinetis
View file

@ -1,9 +0,0 @@
# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0
config PINCTRL_NXP_KINETIS
bool "Pin controller driver for NXP Kinetis MCUs"
default y
depends on DT_HAS_NXP_KINETIS_PINMUX_ENABLED
help
Enable pin controller driver for NXP Kinetis MCUs

9
drivers/pinctrl/Kconfig.nxp_port Normal file
View file

@ -0,0 +1,9 @@
# Copyright 2022, 2024 NXP
# SPDX-License-Identifier: Apache-2.0
config PINCTRL_NXP_PORT
bool "Pin controller driver for NXP PORT peripheral"
default y
depends on DT_HAS_NXP_PORT_PINMUX_ENABLED
help
Enable pin controller driver for NXP PORT peripheral

8
drivers/pinctrl/pinctrl_kinetis.c → drivers/pinctrl/pinctrl_nxp_port.c
View file

@ -5,14 +5,14 @@
*/ */
#define DT_DRV_COMPAT nxp_kinetis_pinmux #define DT_DRV_COMPAT nxp_port_pinmux
#include <zephyr/drivers/clock_control.h> #include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h> #include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
#include <fsl_clock.h> #include <fsl_clock.h>
LOG_MODULE_REGISTER(pinctrl_kinetis, CONFIG_PINCTRL_LOG_LEVEL); LOG_MODULE_REGISTER(pinctrl_nxp_port, CONFIG_PINCTRL_LOG_LEVEL);
/* Port register addresses. */ /* Port register addresses. */
static PORT_Type *ports[] = { static PORT_Type *ports[] = {
@ -52,10 +52,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
return 0; return 0;
} }
/* Kinetis pinmux driver binds to the same DTS nodes,
* and handles clock init. Only bind to these nodes if pinmux driver
* is disabled.
*/
static int pinctrl_mcux_init(const struct device *dev) static int pinctrl_mcux_init(const struct device *dev)
{ {
const struct pinctrl_mcux_config *config = dev->config; const struct pinctrl_mcux_config *config = dev->config;

12
dts/arm/nxp/nxp_k2x.dtsi
View file

@ -55,7 +55,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -194,31 +194,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xd0>; reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xd0>; reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xd0>; reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0xd0>; reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0xd0>; reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

12
dts/arm/nxp/nxp_k6x.dtsi
View file

@ -74,7 +74,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -255,31 +255,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xd0>; reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xd0>; reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xd0>; reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0xd0>; reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0xd0>; reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

12
dts/arm/nxp/nxp_k8x.dtsi
View file

@ -34,7 +34,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -260,31 +260,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0x1000>; reg = <0x40049000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0x1000>; reg = <0x4004a000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0x1000>; reg = <0x4004b000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0x1000>; reg = <0x4004c000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0x1000>; reg = <0x4004d000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

12
dts/arm/nxp/nxp_ke1xf.dtsi
View file

@ -92,7 +92,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -422,31 +422,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0x1000>; reg = <0x40049000 0x1000>;
clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0x1000>; reg = <0x4004a000 0x1000>;
clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0x1000>; reg = <0x4004b000 0x1000>;
clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0x1000>; reg = <0x4004c000 0x1000>;
clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0x1000>; reg = <0x4004d000 0x1000>;
clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };

12
dts/arm/nxp/nxp_ke1xz.dtsi
View file

@ -67,7 +67,7 @@
}; };
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
}; };
soc { soc {
@ -187,31 +187,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0x1000>; reg = <0x40049000 0x1000>;
clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0x1000>; reg = <0x4004a000 0x1000>;
clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0x1000>; reg = <0x4004b000 0x1000>;
clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0x1000>; reg = <0x4004c000 0x1000>;
clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0x1000>; reg = <0x4004d000 0x1000>;
clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>; clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };

12
dts/arm/nxp/nxp_kl25z.dtsi
View file

@ -31,7 +31,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -119,31 +119,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xd0>; reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xd0>; reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xd0>; reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0xd0>; reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0xd0>; reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

12
dts/arm/nxp/nxp_kv5x.dtsi
View file

@ -29,7 +29,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -177,31 +177,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0x1000>; reg = <0x40049000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0x1000>; reg = <0x4004a000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0x1000>; reg = <0x4004b000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0x1000>; reg = <0x4004c000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0x1000>; reg = <0x4004d000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

12
dts/arm/nxp/nxp_kw2xd.dtsi
View file

@ -34,7 +34,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
/* /*
* KW2XD is a system in package part, so the SPI1 controller is * KW2XD is a system in package part, so the SPI1 controller is
@ -176,31 +176,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xd0>; reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xd0>; reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xd0>; reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0xd0>; reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0xd0>; reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

8
dts/arm/nxp/nxp_kw40z.dtsi
View file

@ -32,7 +32,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -124,19 +124,19 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xa4>; reg = <0x40049000 0xa4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xa4>; reg = <0x4004a000 0xa4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xa4>; reg = <0x4004b000 0xa4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };

8
dts/arm/nxp/nxp_kw41z.dtsi
View file

@ -37,7 +37,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -131,19 +131,19 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xa4>; reg = <0x40049000 0xa4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xa4>; reg = <0x4004a000 0xa4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xa4>; reg = <0x4004b000 0xa4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };

12
dts/arm/nxp/nxp_mcxa156.dtsi
View file

@ -24,7 +24,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -50,31 +50,31 @@
}; };
porta: pinmux@400bc000 { porta: pinmux@400bc000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x400bc000 0x1000>; reg = <0x400bc000 0x1000>;
clocks = <&syscon MCUX_PORT0_CLK>; clocks = <&syscon MCUX_PORT0_CLK>;
}; };
portb: pinmux@400bd000 { portb: pinmux@400bd000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x400bd000 0x1000>; reg = <0x400bd000 0x1000>;
clocks = <&syscon MCUX_PORT1_CLK>; clocks = <&syscon MCUX_PORT1_CLK>;
}; };
portc: pinmux@400be000 { portc: pinmux@400be000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x400be000 0x1000>; reg = <0x400be000 0x1000>;
clocks = <&syscon MCUX_PORT2_CLK>; clocks = <&syscon MCUX_PORT2_CLK>;
}; };
portd: pinmux@400bf000 { portd: pinmux@400bf000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x400bf000 0x1000>; reg = <0x400bf000 0x1000>;
clocks = <&syscon MCUX_PORT3_CLK>; clocks = <&syscon MCUX_PORT3_CLK>;
}; };
porte: pinmux@400c0000 { porte: pinmux@400c0000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x400c0000 0x1000>; reg = <0x400c0000 0x1000>;
clocks = <&syscon MCUX_PORT4_CLK>; clocks = <&syscon MCUX_PORT4_CLK>;
}; };

12
dts/arm/nxp/nxp_mcxc_common.dtsi
View file

@ -35,7 +35,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -107,31 +107,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0xd0>; reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0xd0>; reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0xd0>; reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0xd0>; reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0xd0>; reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
}; };

14
dts/arm/nxp/nxp_mcxn23x_common.dtsi
View file

@ -30,7 +30,7 @@
}; };
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
}; };
@ -74,37 +74,37 @@
}; };
porta: pinmux@116000 { porta: pinmux@116000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x116000 0x1000>; reg = <0x116000 0x1000>;
clocks = <&syscon MCUX_PORT0_CLK>; clocks = <&syscon MCUX_PORT0_CLK>;
}; };
portb: pinmux@117000 { portb: pinmux@117000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x117000 0x1000>; reg = <0x117000 0x1000>;
clocks = <&syscon MCUX_PORT1_CLK>; clocks = <&syscon MCUX_PORT1_CLK>;
}; };
portc: pinmux@118000 { portc: pinmux@118000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x118000 0x1000>; reg = <0x118000 0x1000>;
clocks = <&syscon MCUX_PORT2_CLK>; clocks = <&syscon MCUX_PORT2_CLK>;
}; };
portd: pinmux@119000 { portd: pinmux@119000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x119000 0x1000>; reg = <0x119000 0x1000>;
clocks = <&syscon MCUX_PORT3_CLK>; clocks = <&syscon MCUX_PORT3_CLK>;
}; };
porte: pinmux@11a000 { porte: pinmux@11a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x11a000 0x1000>; reg = <0x11a000 0x1000>;
clocks = <&syscon MCUX_PORT4_CLK>; clocks = <&syscon MCUX_PORT4_CLK>;
}; };
portf: pinmux@42000 { portf: pinmux@42000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x42000 0x1000>; reg = <0x42000 0x1000>;
clocks = <&syscon MCUX_PORT5_CLK>; clocks = <&syscon MCUX_PORT5_CLK>;
}; };

14
dts/arm/nxp/nxp_mcxn94x_common.dtsi
View file

@ -35,7 +35,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
}; };
@ -80,37 +80,37 @@
}; };
porta: pinmux@116000 { porta: pinmux@116000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x116000 0x1000>; reg = <0x116000 0x1000>;
clocks = <&syscon MCUX_PORT0_CLK>; clocks = <&syscon MCUX_PORT0_CLK>;
}; };
portb: pinmux@117000 { portb: pinmux@117000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x117000 0x1000>; reg = <0x117000 0x1000>;
clocks = <&syscon MCUX_PORT1_CLK>; clocks = <&syscon MCUX_PORT1_CLK>;
}; };
portc: pinmux@118000 { portc: pinmux@118000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x118000 0x1000>; reg = <0x118000 0x1000>;
clocks = <&syscon MCUX_PORT2_CLK>; clocks = <&syscon MCUX_PORT2_CLK>;
}; };
portd: pinmux@119000 { portd: pinmux@119000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x119000 0x1000>; reg = <0x119000 0x1000>;
clocks = <&syscon MCUX_PORT3_CLK>; clocks = <&syscon MCUX_PORT3_CLK>;
}; };
porte: pinmux@11a000 { porte: pinmux@11a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x11a000 0x1000>; reg = <0x11a000 0x1000>;
clocks = <&syscon MCUX_PORT4_CLK>; clocks = <&syscon MCUX_PORT4_CLK>;
}; };
portf: pinmux@42000 { portf: pinmux@42000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x42000 0x1000>; reg = <0x42000 0x1000>;
clocks = <&syscon MCUX_PORT5_CLK>; clocks = <&syscon MCUX_PORT5_CLK>;
}; };

10
dts/arm/nxp/nxp_mcxw71.dtsi
View file

@ -116,7 +116,7 @@
}; };
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
}; };
}; };
@ -147,25 +147,25 @@
}; };
porta: pinctrl@42000 { porta: pinctrl@42000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x42000 0xe0>; reg = <0x42000 0xe0>;
clocks = <&scg SCG_K4_SLOW_CLK 0x108>; clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
}; };
portb: pinctrl@43000 { portb: pinctrl@43000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x43000 0xe0>; reg = <0x43000 0xe0>;
clocks = <&scg SCG_K4_SLOW_CLK 0x10c>; clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
}; };
portc: pinctrl@44000 { portc: pinctrl@44000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x44000 0xe0>; reg = <0x44000 0xe0>;
clocks = <&scg SCG_K4_SLOW_CLK 0x110>; clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
}; };
portd: pinctrl@45000 { portd: pinctrl@45000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x45000 0xe0>; reg = <0x45000 0xe0>;
clocks = <&scg SCG_K4_SLOW_CLK 0>; clocks = <&scg SCG_K4_SLOW_CLK 0>;
}; };

12
dts/arm/nxp/nxp_s32k1xx.dtsi
View file

@ -25,7 +25,7 @@
/* Dummy pinctrl node, filled with pin mux options at board level */ /* Dummy pinctrl node, filled with pin mux options at board level */
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "nxp,kinetis-pinctrl"; compatible = "nxp,port-pinctrl";
status = "okay"; status = "okay";
}; };
@ -99,31 +99,31 @@
}; };
porta: pinmux@40049000 { porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x40049000 0x1000>; reg = <0x40049000 0x1000>;
clocks = <&clock NXP_S32_PORTA_CLK>; clocks = <&clock NXP_S32_PORTA_CLK>;
}; };
portb: pinmux@4004a000 { portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004a000 0x1000>; reg = <0x4004a000 0x1000>;
clocks = <&clock NXP_S32_PORTB_CLK>; clocks = <&clock NXP_S32_PORTB_CLK>;
}; };
portc: pinmux@4004b000 { portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004b000 0x1000>; reg = <0x4004b000 0x1000>;
clocks = <&clock NXP_S32_PORTC_CLK>; clocks = <&clock NXP_S32_PORTC_CLK>;
}; };
portd: pinmux@4004c000 { portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004c000 0x1000>; reg = <0x4004c000 0x1000>;
clocks = <&clock NXP_S32_PORTD_CLK>; clocks = <&clock NXP_S32_PORTD_CLK>;
}; };
porte: pinmux@4004d000 { porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,port-pinmux";
reg = <0x4004d000 0x1000>; reg = <0x4004d000 0x1000>;
clocks = <&clock NXP_S32_PORTE_CLK>; clocks = <&clock NXP_S32_PORTE_CLK>;
}; };

21
dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml → dts/bindings/pinctrl/nxp,port-pinctrl.yaml
View file

@ -2,13 +2,14 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
description: | description: |
Kinetis pinctrl node. This node will define pin configurations in pin groups, NXP PORT pinctrl node. This node will define pin configurations in pin
and has the 'pinctrl' node identifier in the SOC's devicetree. Each group groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
within the pin configuration defines the pin configuration for a peripheral, group within the pin configuration defines the pin configuration for a
and each numbered subgroup in the pin group defines all the pins for that peripheral, and each numbered subgroup in the pin group defines all the pins
peripheral with the same configuration properties. The 'pins' property in for that peripheral with the same configuration properties. The 'pins'
a group selects the pins to be configured, and the remaining properties set property in a group selects the pins to be configured, and the remaining
configuration values for those pins. Here is an example group for UART0 pins: properties set configuration values for those pins. Here is an example
group for UART0 pins:
uart0_default: uart0_default { uart0_default: uart0_default {
group0 { group0 {
@ -28,15 +29,15 @@ description: |
PCR_DSE=<drive-strength selection>, PCR_DSE=<drive-strength selection>,
PCR_PFE=0 PCR_PFE=0
compatible: "nxp,kinetis-pinctrl" compatible: "nxp,port-pinctrl"
include: base.yaml include: base.yaml
child-binding: child-binding:
description: Kinetis pin controller pin group description: NXP PORT pin controller pin group
child-binding: child-binding:
description: | description: |
Kinetis pin controller pin configuration node NXP PORT pin controller pin configuration node
include: include:
- name: pincfg-node.yaml - name: pincfg-node.yaml

4
dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml → dts/bindings/pinctrl/nxp,port-pinmux.yaml
View file

@ -1,6 +1,6 @@
description: Kinetis pinmux node description: NXP PORT pinmux node
compatible: "nxp,kinetis-pinmux" compatible: "nxp,port-pinmux"
include: base.yaml include: base.yaml

2
west.yml
View file

@ -198,7 +198,7 @@ manifest:
groups: groups:
- hal - hal
- name: hal_nxp - name: hal_nxp
revision: 3c64cd63125c86870802a561ce79dc33697b005c revision: cae40020064894f67b00215dad2baf7c743e1dfb
path: modules/hal/nxp path: modules/hal/nxp
groups: groups:
- hal - hal