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arch: arm: aarch64: add SMP support

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With timer/gic/cache added, we could add the SMP support.
Bringup cores

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2020-11-09 15:58:15 +08:00 • committed by Anas Nashif
commit a2ea20dd6d
7 changed files with 189 additions and 0 deletions
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4
include/arch/arm/aarch64/cpu.h
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@ -202,4 +202,8 @@
#endif /* CONFIG_CPU_CORTEX_A72 */
#define L1_CACHE_SHIFT (6)
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#define ARM64_CPU_INIT_SIZE L1_CACHE_BYTES
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_ */

4
include/arch/arm/aarch64/lib_helpers.h
View file

@ -127,6 +127,10 @@ static ALWAYS_INLINE void disable_fiq(void)
:: "i" (DAIFSET_FIQ_BIT) : "memory");
}
#define sev() __asm__ volatile("sev" : : : "memory")
#define wfe() __asm__ volatile("wfe" : : : "memory")
#define wfi() __asm__ volatile("wfi" : : : "memory")
#define dsb() __asm__ volatile ("dsb sy" ::: "memory")
#define dmb() __asm__ volatile ("dmb sy" ::: "memory")
#define isb() __asm__ volatile ("isb" ::: "memory")