dts: Convert from DT_<COMPAT>_<INSTANCE>_<PROP> to DT_INST...

Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-06-11 14:20:32 -05:00 committed by Kumar Gala
commit a2693975d7
206 changed files with 1480 additions and 1479 deletions

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@ -25,11 +25,11 @@ static struct arc_mpu_region mpu_regions[] = {
REGION_KERNEL_RAM_ATTR | REGION_DYNAMIC), REGION_KERNEL_RAM_ATTR | REGION_DYNAMIC),
#endif #endif
#if DT_MMIO_SRAM_0_SIZE > 0 #if DT_INST_0_MMIO_SRAM_SIZE > 0
/* Region DDR RAM */ /* Region DDR RAM */
MPU_REGION_ENTRY("DDR RAM", MPU_REGION_ENTRY("DDR RAM",
DT_MMIO_SRAM_0_BASE_ADDRESS, DT_INST_0_MMIO_SRAM_BASE_ADDRESS,
DT_MMIO_SRAM_0_SIZE, DT_INST_0_MMIO_SRAM_SIZE,
AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | AUX_MPU_ATTR_UR | AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | AUX_MPU_ATTR_UR |
AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE | REGION_DYNAMIC), AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE | REGION_DYNAMIC),
#endif #endif

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@ -67,7 +67,7 @@ DEVICE_INIT(vdd_pwr_ctrl_init, "", pwr_ctrl_init, NULL, &vdd_pwr_ctrl_cfg,
#endif #endif
static const struct pwr_ctrl_cfg ccs_vdd_pwr_ctrl_cfg = { static const struct pwr_ctrl_cfg ccs_vdd_pwr_ctrl_cfg = {
.port = DT_SEMTECH_SX1509B_0_LABEL, .port = DT_INST_0_SEMTECH_SX1509B_LABEL,
.pin = CCS_VDD_PWR_CTRL_GPIO_PIN, .pin = CCS_VDD_PWR_CTRL_GPIO_PIN,
}; };

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@ -8,11 +8,11 @@
#define __INC_BOARD_H #define __INC_BOARD_H
/* SKYWORKS SKY13351 antenna selection settings */ /* SKYWORKS SKY13351 antenna selection settings */
#define SKY_UFLn_GPIO_NAME DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_CONTROLLER #define SKY_UFLn_GPIO_NAME DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_CONTROLLER
#define SKY_UFLn_GPIO_FLAGS DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_FLAGS #define SKY_UFLn_GPIO_FLAGS DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_FLAGS
#define SKY_UFLn_GPIO_PIN DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_PIN #define SKY_UFLn_GPIO_PIN DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_PIN
#define SKY_PCBn_GPIO_NAME DT_SKYWORKS_SKY13351_0_VCTL2_GPIOS_CONTROLLER #define SKY_PCBn_GPIO_NAME DT_INST_0_SKYWORKS_SKY13351_VCTL2_GPIOS_CONTROLLER
#define SKY_PCBn_GPIO_FLAGS DT_SKYWORKS_SKY13351_0_VCTL2_GPIOS_FLAGS #define SKY_PCBn_GPIO_FLAGS DT_INST_0_SKYWORKS_SKY13351_VCTL2_GPIOS_FLAGS
#define SKY_PCBn_GPIO_PIN DT_SKYWORKS_SKY13351_0_VCTL2_GPIOS_PIN #define SKY_PCBn_GPIO_PIN DT_INST_0_SKYWORKS_SKY13351_VCTL2_GPIOS_PIN
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

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@ -8,15 +8,15 @@
#define __INC_BOARD_H #define __INC_BOARD_H
/* pin used to enable the buffer power */ /* pin used to enable the buffer power */
#define SERIAL_BUFFER_ENABLE_GPIO_NAME DT_NORDIC_NRF_GPIO_0_LABEL #define SERIAL_BUFFER_ENABLE_GPIO_NAME DT_INST_0_NORDIC_NRF_GPIO_LABEL
#define SERIAL_BUFFER_ENABLE_GPIO_PIN 25 #define SERIAL_BUFFER_ENABLE_GPIO_PIN 25
/* pin used to detect V_INT (buffer power) */ /* pin used to detect V_INT (buffer power) */
#define V_INT_DETECT_GPIO_PIN 2 #define V_INT_DETECT_GPIO_PIN 2
/* SKYWORKS SKY13351 antenna selection settings (only use vctl1) */ /* SKYWORKS SKY13351 antenna selection settings (only use vctl1) */
#define ANT_SEL_GPIO_NAME DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_CONTROLLER #define ANT_SEL_GPIO_NAME DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_CONTROLLER
#define ANT_SEL_GPIO_FLAGS DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_FLAGS #define ANT_SEL_GPIO_FLAGS DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_FLAGS
#define ANT_SEL_GPIO_PIN DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_PIN #define ANT_SEL_GPIO_PIN DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_PIN
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

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@ -8,11 +8,11 @@
#define __INC_BOARD_H #define __INC_BOARD_H
/* SKYWORKS SKY13351 antenna selection settings */ /* SKYWORKS SKY13351 antenna selection settings */
#define SKY_UFLn_GPIO_NAME DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_CONTROLLER #define SKY_UFLn_GPIO_NAME DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_CONTROLLER
#define SKY_UFLn_GPIO_FLAGS DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_FLAGS #define SKY_UFLn_GPIO_FLAGS DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_FLAGS
#define SKY_UFLn_GPIO_PIN DT_SKYWORKS_SKY13351_0_VCTL1_GPIOS_PIN #define SKY_UFLn_GPIO_PIN DT_INST_0_SKYWORKS_SKY13351_VCTL1_GPIOS_PIN
#define SKY_PCBn_GPIO_NAME DT_SKYWORKS_SKY13351_0_VCTL2_GPIOS_CONTROLLER #define SKY_PCBn_GPIO_NAME DT_INST_0_SKYWORKS_SKY13351_VCTL2_GPIOS_CONTROLLER
#define SKY_PCBn_GPIO_FLAGS DT_SKYWORKS_SKY13351_0_VCTL2_GPIOS_FLAGS #define SKY_PCBn_GPIO_FLAGS DT_INST_0_SKYWORKS_SKY13351_VCTL2_GPIOS_FLAGS
#define SKY_PCBn_GPIO_PIN DT_SKYWORKS_SKY13351_0_VCTL2_GPIOS_PIN #define SKY_PCBn_GPIO_PIN DT_INST_0_SKYWORKS_SKY13351_VCTL2_GPIOS_PIN
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

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@ -33,11 +33,11 @@ static int board_reel_board_init(struct device *dev)
* (High-Impedance state of pin B from Dual-Supply Bus Transceiver). * (High-Impedance state of pin B from Dual-Supply Bus Transceiver).
*/ */
gpio = NRF_P0; gpio = NRF_P0;
gpio->PIN_CNF[DT_NORDIC_NRF_UART_0_RX_PIN] = gpio->PIN_CNF[DT_INST_0_NORDIC_NRF_UART_RX_PIN] =
(GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) |
(GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
gpio->PIN_CNF[DT_NORDIC_NRF_UART_0_TX_PIN] = gpio->PIN_CNF[DT_INST_0_NORDIC_NRF_UART_TX_PIN] =
(GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) |
(GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);

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@ -103,10 +103,10 @@ static int twr_ke18f_pinmux_init(struct device *dev)
#endif #endif
/* FXOS8700 INT1, INT2, RST */ /* FXOS8700 INT1, INT2, RST */
#ifdef DT_NXP_FXOS8700_0_INT1_GPIOS_PIN #ifdef DT_INST_0_NXP_FXOS8700_INT1_GPIOS_PIN
pinmux_pin_set(porta, 14, PORT_PCR_MUX(kPORT_MuxAsGpio)); pinmux_pin_set(porta, 14, PORT_PCR_MUX(kPORT_MuxAsGpio));
#endif #endif
#ifdef DT_NXP_FXOS8700_0_INT2_GPIOS_PIN #ifdef DT_INST_0_NXP_FXOS8700_INT2_GPIOS_PIN
pinmux_pin_set(portc, 17, PORT_PCR_MUX(kPORT_MuxAsGpio)); pinmux_pin_set(portc, 17, PORT_PCR_MUX(kPORT_MuxAsGpio));
#endif #endif
pinmux_pin_set(portc, 15, PORT_PCR_MUX(kPORT_MuxAsGpio)); pinmux_pin_set(portc, 15, PORT_PCR_MUX(kPORT_MuxAsGpio));

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@ -4,6 +4,6 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#define DT_FLASH_DEV_NAME DT_ZEPHYR_NATIVE_POSIX_FLASH_CONTROLLER_0_LABEL #define DT_FLASH_DEV_NAME DT_INST_0_ZEPHYR_NATIVE_POSIX_FLASH_CONTROLLER_LABEL
#define DT_UART_0_DEV_NAME DT_ZEPHYR_NATIVE_POSIX_UART_1_LABEL #define DT_UART_0_DEV_NAME DT_ZEPHYR_NATIVE_POSIX_UART_1_LABEL

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@ -34,14 +34,14 @@
#define OFFLOAD_SW_IRQ SWI0_EGU0_IRQn #define OFFLOAD_SW_IRQ SWI0_EGU0_IRQn
/* HACK due to the nrf52_bsim not yet supporting DTS */ /* HACK due to the nrf52_bsim not yet supporting DTS */
#if !defined(DT_NORDIC_NRF_CLOCK_0_LABEL) #if !defined(DT_INST_0_NORDIC_NRF_CLOCK_LABEL)
#define DT_NORDIC_NRF_CLOCK_0_LABEL "CLOCK" #define DT_INST_0_NORDIC_NRF_CLOCK_LABEL "CLOCK"
#endif #endif
#if !defined(DT_NORDIC_NRF_CLOCK_0_IRQ_0) #if !defined(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0)
#define DT_NORDIC_NRF_CLOCK_0_IRQ_0 POWER_CLOCK_IRQn #define DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0 POWER_CLOCK_IRQn
#endif #endif
#if !defined(DT_NORDIC_NRF_CLOCK_0_IRQ_0_PRIORITY) #if !defined(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0_PRIORITY)
#define DT_NORDIC_NRF_CLOCK_0_IRQ_0_PRIORITY 1 #define DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0_PRIORITY 1
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus

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@ -40,7 +40,7 @@ config GPIO_PCAL9535A_0_DEV_NAME
config GPIO_PCAL9535A_0_I2C_ADDR config GPIO_PCAL9535A_0_I2C_ADDR
default 0x25 default 0x25
config GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME config GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_SNPS_DESIGNWARE_I2C_0_LABEL)" default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # GPIO_PCAL9535A_0 endif # GPIO_PCAL9535A_0
@ -54,7 +54,7 @@ config GPIO_PCAL9535A_1_DEV_NAME
config GPIO_PCAL9535A_1_I2C_ADDR config GPIO_PCAL9535A_1_I2C_ADDR
default 0x26 default 0x26
config GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME config GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_SNPS_DESIGNWARE_I2C_0_LABEL)" default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # GPIO_PCAL9535A_1 endif # GPIO_PCAL9535A_1
@ -68,7 +68,7 @@ config GPIO_PCAL9535A_2_DEV_NAME
config GPIO_PCAL9535A_2_I2C_ADDR config GPIO_PCAL9535A_2_I2C_ADDR
default 0x27 default 0x27
config GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME config GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_SNPS_DESIGNWARE_I2C_0_LABEL)" default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # GPIO_PCAL9535A_2 endif # GPIO_PCAL9535A_2
@ -93,7 +93,7 @@ config PWM_PCA9685_0_DEV_NAME
config PWM_PCA9685_0_I2C_ADDR config PWM_PCA9685_0_I2C_ADDR
default 0x47 default 0x47
config PWM_PCA9685_0_I2C_MASTER_DEV_NAME config PWM_PCA9685_0_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_SNPS_DESIGNWARE_I2C_0_LABEL)" default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # PWM_PCA9685_0 endif # PWM_PCA9685_0
endif # PWM_PCA9685 endif # PWM_PCA9685

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@ -15,12 +15,12 @@
#include <gpio.h> #include <gpio.h>
static struct cc2520_gpio_configuration cc2520_gpios[CC2520_GPIO_IDX_MAX] = { static struct cc2520_gpio_configuration cc2520_gpios[CC2520_GPIO_IDX_MAX] = {
{ .dev = NULL, .pin = DT_TI_CC2520_0_VREG_EN_GPIOS_PIN, }, { .dev = NULL, .pin = DT_INST_0_TI_CC2520_VREG_EN_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_TI_CC2520_0_RESET_GPIOS_PIN, }, { .dev = NULL, .pin = DT_INST_0_TI_CC2520_RESET_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_TI_CC2520_0_FIFO_GPIOS_PIN, }, { .dev = NULL, .pin = DT_INST_0_TI_CC2520_FIFO_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_TI_CC2520_0_CCA_GPIOS_PIN, }, { .dev = NULL, .pin = DT_INST_0_TI_CC2520_CCA_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_TI_CC2520_0_SFD_GPIOS_PIN, }, { .dev = NULL, .pin = DT_INST_0_TI_CC2520_SFD_GPIOS_PIN, },
{ .dev = NULL, .pin = DT_TI_CC2520_0_FIFOP_GPIOS_PIN, }, { .dev = NULL, .pin = DT_INST_0_TI_CC2520_FIFOP_GPIOS_PIN, },
}; };
struct cc2520_gpio_configuration *cc2520_configure_gpios(void) struct cc2520_gpio_configuration *cc2520_configure_gpios(void)
@ -31,32 +31,32 @@ struct cc2520_gpio_configuration *cc2520_configure_gpios(void)
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE); GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
struct device *gpio; struct device *gpio;
gpio = device_get_binding(DT_TI_CC2520_0_VREG_EN_GPIOS_CONTROLLER); gpio = device_get_binding(DT_INST_0_TI_CC2520_VREG_EN_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].pin, gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].pin,
flags_noint_out); flags_noint_out);
cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].dev = gpio; cc2520_gpios[CC2520_GPIO_IDX_VREG_EN].dev = gpio;
gpio = device_get_binding(DT_TI_CC2520_0_RESET_GPIOS_CONTROLLER); gpio = device_get_binding(DT_INST_0_TI_CC2520_RESET_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_RESET].pin, gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_RESET].pin,
flags_noint_out); flags_noint_out);
cc2520_gpios[CC2520_GPIO_IDX_RESET].dev = gpio; cc2520_gpios[CC2520_GPIO_IDX_RESET].dev = gpio;
gpio = device_get_binding(DT_TI_CC2520_0_SFD_GPIOS_CONTROLLER); gpio = device_get_binding(DT_INST_0_TI_CC2520_SFD_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_SFD].pin, gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_SFD].pin,
flags_int_in); flags_int_in);
cc2520_gpios[CC2520_GPIO_IDX_SFD].dev = gpio; cc2520_gpios[CC2520_GPIO_IDX_SFD].dev = gpio;
gpio = device_get_binding(DT_TI_CC2520_0_FIFOP_GPIOS_CONTROLLER); gpio = device_get_binding(DT_INST_0_TI_CC2520_FIFOP_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFOP].pin, gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFOP].pin,
flags_int_in); flags_int_in);
cc2520_gpios[CC2520_GPIO_IDX_FIFOP].dev = gpio; cc2520_gpios[CC2520_GPIO_IDX_FIFOP].dev = gpio;
gpio = device_get_binding(DT_TI_CC2520_0_FIFO_GPIOS_CONTROLLER); gpio = device_get_binding(DT_INST_0_TI_CC2520_FIFO_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFO].pin, gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_FIFO].pin,
flags_noint_in); flags_noint_in);
cc2520_gpios[CC2520_GPIO_IDX_FIFO].dev = gpio; cc2520_gpios[CC2520_GPIO_IDX_FIFO].dev = gpio;
gpio = device_get_binding(DT_TI_CC2520_0_CCA_GPIOS_CONTROLLER); gpio = device_get_binding(DT_INST_0_TI_CC2520_CCA_GPIOS_CONTROLLER);
gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_CCA].pin, gpio_pin_configure(gpio, cc2520_gpios[CC2520_GPIO_IDX_CCA].pin,
flags_noint_in); flags_noint_in);
cc2520_gpios[CC2520_GPIO_IDX_CCA].dev = gpio; cc2520_gpios[CC2520_GPIO_IDX_CCA].dev = gpio;

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@ -150,10 +150,10 @@ static int mpxxdtyy_initialize(struct device *dev)
{ {
struct mpxxdtyy_data *const data = DEV_DATA(dev); struct mpxxdtyy_data *const data = DEV_DATA(dev);
data->comm_master = device_get_binding(DT_ST_MPXXDTYY_0_BUS_NAME); data->comm_master = device_get_binding(DT_INST_0_ST_MPXXDTYY_BUS_NAME);
if (data->comm_master == NULL) { if (data->comm_master == NULL) {
LOG_ERR("master %s not found", DT_ST_MPXXDTYY_0_BUS_NAME); LOG_ERR("master %s not found", DT_INST_0_ST_MPXXDTYY_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
@ -163,6 +163,6 @@ static int mpxxdtyy_initialize(struct device *dev)
static struct mpxxdtyy_data mpxxdtyy_data; static struct mpxxdtyy_data mpxxdtyy_data;
DEVICE_AND_API_INIT(mpxxdtyy, DT_ST_MPXXDTYY_0_LABEL, mpxxdtyy_initialize, DEVICE_AND_API_INIT(mpxxdtyy, DT_INST_0_ST_MPXXDTYY_LABEL, mpxxdtyy_initialize,
&mpxxdtyy_data, NULL, POST_KERNEL, &mpxxdtyy_data, NULL, POST_KERNEL,
CONFIG_AUDIO_DMIC_INIT_PRIORITY, &mpxxdtyy_driver_api); CONFIG_AUDIO_DMIC_INIT_PRIORITY, &mpxxdtyy_driver_api);

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@ -45,11 +45,11 @@
#define CMD_OGF 1 #define CMD_OGF 1
#define CMD_OCF 2 #define CMD_OCF 2
#define GPIO_IRQ_PIN DT_ZEPHYR_BT_HCI_SPI_0_IRQ_GPIO_PIN #define GPIO_IRQ_PIN DT_INST_0_ZEPHYR_BT_HCI_SPI_IRQ_GPIO_PIN
#define GPIO_RESET_PIN DT_ZEPHYR_BT_HCI_SPI_0_RESET_GPIO_PIN #define GPIO_RESET_PIN DT_INST_0_ZEPHYR_BT_HCI_SPI_RESET_GPIO_PIN
#ifdef DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_PIN #ifdef DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_PIN
#define GPIO_CS_PIN DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_PIN #define GPIO_CS_PIN DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_PIN
#endif /* DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_PIN */ #endif /* DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_PIN */
/* Max SPI buffer length for transceive operations. /* Max SPI buffer length for transceive operations.
* *
@ -124,7 +124,7 @@ static int bt_spi_send_aci_config_data_controller_mode(void);
static struct device *spi_dev; static struct device *spi_dev;
static struct spi_config spi_conf = { static struct spi_config spi_conf = {
.frequency = DT_ZEPHYR_BT_HCI_SPI_0_SPI_MAX_FREQUENCY, .frequency = DT_INST_0_ZEPHYR_BT_HCI_SPI_SPI_MAX_FREQUENCY,
.operation = (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8) | .operation = (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8) |
SPI_LINES_SINGLE), SPI_LINES_SINGLE),
.slave = 0, .slave = 0,
@ -194,10 +194,10 @@ static void bt_spi_handle_vendor_evt(u8_t *rxmsg)
*/ */
static int configure_cs(void) static int configure_cs(void)
{ {
cs_dev = device_get_binding(DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_CONTROLLER); cs_dev = device_get_binding(DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_CONTROLLER);
if (!cs_dev) { if (!cs_dev) {
BT_ERR("Failed to initialize GPIO driver: %s", BT_ERR("Failed to initialize GPIO driver: %s",
DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_CONTROLLER);
return -EIO; return -EIO;
} }
@ -254,10 +254,10 @@ static int configure_cs(void)
spi_conf_cs.gpio_pin = GPIO_CS_PIN, spi_conf_cs.gpio_pin = GPIO_CS_PIN,
spi_conf_cs.gpio_dev = device_get_binding( spi_conf_cs.gpio_dev = device_get_binding(
DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_CONTROLLER);
if (!spi_conf_cs.gpio_dev) { if (!spi_conf_cs.gpio_dev) {
BT_ERR("Failed to initialize GPIO driver: %s", BT_ERR("Failed to initialize GPIO driver: %s",
DT_ZEPHYR_BT_HCI_SPI_0_CS_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_CS_GPIO_CONTROLLER);
return -EIO; return -EIO;
} }
@ -520,7 +520,7 @@ static int bt_spi_open(void)
} }
static const struct bt_hci_driver drv = { static const struct bt_hci_driver drv = {
.name = DT_ZEPHYR_BT_HCI_SPI_0_LABEL, .name = DT_INST_0_ZEPHYR_BT_HCI_SPI_LABEL,
.bus = BT_HCI_DRIVER_BUS_SPI, .bus = BT_HCI_DRIVER_BUS_SPI,
#if defined(CONFIG_BT_BLUENRG_ACI) #if defined(CONFIG_BT_BLUENRG_ACI)
.quirks = BT_QUIRK_NO_RESET, .quirks = BT_QUIRK_NO_RESET,
@ -533,10 +533,10 @@ static int bt_spi_init(struct device *unused)
{ {
ARG_UNUSED(unused); ARG_UNUSED(unused);
spi_dev = device_get_binding(DT_ZEPHYR_BT_HCI_SPI_0_BUS_NAME); spi_dev = device_get_binding(DT_INST_0_ZEPHYR_BT_HCI_SPI_BUS_NAME);
if (!spi_dev) { if (!spi_dev) {
BT_ERR("Failed to initialize SPI driver: %s", BT_ERR("Failed to initialize SPI driver: %s",
DT_ZEPHYR_BT_HCI_SPI_0_BUS_NAME); DT_INST_0_ZEPHYR_BT_HCI_SPI_BUS_NAME);
return -EIO; return -EIO;
} }
@ -545,18 +545,18 @@ static int bt_spi_init(struct device *unused)
} }
irq_dev = device_get_binding( irq_dev = device_get_binding(
DT_ZEPHYR_BT_HCI_SPI_0_IRQ_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_IRQ_GPIO_CONTROLLER);
if (!irq_dev) { if (!irq_dev) {
BT_ERR("Failed to initialize GPIO driver: %s", BT_ERR("Failed to initialize GPIO driver: %s",
DT_ZEPHYR_BT_HCI_SPI_0_IRQ_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_IRQ_GPIO_CONTROLLER);
return -EIO; return -EIO;
} }
rst_dev = device_get_binding( rst_dev = device_get_binding(
DT_ZEPHYR_BT_HCI_SPI_0_RESET_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_RESET_GPIO_CONTROLLER);
if (!rst_dev) { if (!rst_dev) {
BT_ERR("Failed to initialize GPIO driver: %s", BT_ERR("Failed to initialize GPIO driver: %s",
DT_ZEPHYR_BT_HCI_SPI_0_RESET_GPIO_CONTROLLER); DT_INST_0_ZEPHYR_BT_HCI_SPI_RESET_GPIO_CONTROLLER);
return -EIO; return -EIO;
} }

View file

@ -56,7 +56,7 @@ static int m16src_start(struct device *dev, clock_control_subsys_t sub_system)
if (blocking) { if (blocking) {
u32_t intenset; u32_t intenset;
irq_disable(DT_NORDIC_NRF_CLOCK_0_IRQ_0); irq_disable(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
@ -77,9 +77,9 @@ static int m16src_start(struct device *dev, clock_control_subsys_t sub_system)
nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK); nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK);
} }
NVIC_ClearPendingIRQ(DT_NORDIC_NRF_CLOCK_0_IRQ_0); NVIC_ClearPendingIRQ(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
irq_enable(DT_NORDIC_NRF_CLOCK_0_IRQ_0); irq_enable(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
} else { } else {
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
@ -184,7 +184,7 @@ static int k32src_start(struct device *dev, clock_control_subsys_t sub_system)
NRF_CLOCK->LFCLKSRC = lf_clk_src; NRF_CLOCK->LFCLKSRC = lf_clk_src;
#if defined(CONFIG_CLOCK_CONTROL_NRF_K32SRC_BLOCKING) #if defined(CONFIG_CLOCK_CONTROL_NRF_K32SRC_BLOCKING)
irq_disable(DT_NORDIC_NRF_CLOCK_0_IRQ_0); irq_disable(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
intenset = NRF_CLOCK->INTENSET; intenset = NRF_CLOCK->INTENSET;
nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK); nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK);
@ -204,9 +204,9 @@ static int k32src_start(struct device *dev, clock_control_subsys_t sub_system)
nrf_clock_int_disable(NRF_CLOCK_INT_LF_STARTED_MASK); nrf_clock_int_disable(NRF_CLOCK_INT_LF_STARTED_MASK);
} }
NVIC_ClearPendingIRQ(DT_NORDIC_NRF_CLOCK_0_IRQ_0); NVIC_ClearPendingIRQ(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
irq_enable(DT_NORDIC_NRF_CLOCK_0_IRQ_0); irq_enable(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
#else /* !CONFIG_CLOCK_CONTROL_NRF_K32SRC_BLOCKING */ #else /* !CONFIG_CLOCK_CONTROL_NRF_K32SRC_BLOCKING */
/* NOTE: LFCLK will initially start running from the LFRC if LFXO is /* NOTE: LFCLK will initially start running from the LFRC if LFXO is
@ -250,7 +250,7 @@ static int k32src_start(struct device *dev, clock_control_subsys_t sub_system)
err = m16src_start(dev, false); err = m16src_start(dev, false);
if (!err) { if (!err) {
NVIC_SetPendingIRQ(DT_NORDIC_NRF_CLOCK_0_IRQ_0); NVIC_SetPendingIRQ(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
} else { } else {
__ASSERT_NO_MSG(err == -EINPROGRESS); __ASSERT_NO_MSG(err == -EINPROGRESS);
} }
@ -410,7 +410,7 @@ void nrf_power_clock_isr(void *arg)
err = m16src_start(dev, false); err = m16src_start(dev, false);
if (!err) { if (!err) {
NVIC_SetPendingIRQ(DT_NORDIC_NRF_CLOCK_0_IRQ_0); NVIC_SetPendingIRQ(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
} else { } else {
__ASSERT_NO_MSG(err == -EINPROGRESS); __ASSERT_NO_MSG(err == -EINPROGRESS);
} }
@ -443,11 +443,11 @@ static int clock_control_init(struct device *dev)
* power peripheral driver and/or new SoC series. * power peripheral driver and/or new SoC series.
* NOTE: Currently the operations here are idempotent. * NOTE: Currently the operations here are idempotent.
*/ */
IRQ_CONNECT(DT_NORDIC_NRF_CLOCK_0_IRQ_0, IRQ_CONNECT(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0,
DT_NORDIC_NRF_CLOCK_0_IRQ_0_PRIORITY, DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0_PRIORITY,
nrf_power_clock_isr, 0, 0); nrf_power_clock_isr, 0, 0);
irq_enable(DT_NORDIC_NRF_CLOCK_0_IRQ_0); irq_enable(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
return 0; return 0;
} }
@ -459,7 +459,7 @@ static const struct clock_control_driver_api _m16src_clock_control_api = {
}; };
DEVICE_AND_API_INIT(clock_nrf5_m16src, DEVICE_AND_API_INIT(clock_nrf5_m16src,
DT_NORDIC_NRF_CLOCK_0_LABEL "_16M", DT_INST_0_NORDIC_NRF_CLOCK_LABEL "_16M",
clock_control_init, NULL, NULL, PRE_KERNEL_1, clock_control_init, NULL, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&_m16src_clock_control_api); &_m16src_clock_control_api);
@ -471,7 +471,7 @@ static const struct clock_control_driver_api _k32src_clock_control_api = {
}; };
DEVICE_AND_API_INIT(clock_nrf5_k32src, DEVICE_AND_API_INIT(clock_nrf5_k32src,
DT_NORDIC_NRF_CLOCK_0_LABEL "_32K", DT_INST_0_NORDIC_NRF_CLOCK_LABEL "_32K",
clock_control_init, NULL, NULL, PRE_KERNEL_1, clock_control_init, NULL, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&_k32src_clock_control_api); &_k32src_clock_control_api);
@ -489,7 +489,7 @@ void nrf5_power_usb_power_int_enable(bool enable)
if (enable) { if (enable) {
nrf_power_int_enable(mask); nrf_power_int_enable(mask);
irq_enable(DT_NORDIC_NRF_CLOCK_0_IRQ_0); irq_enable(DT_INST_0_NORDIC_NRF_CLOCK_IRQ_0);
} else { } else {
nrf_power_int_disable(mask); nrf_power_int_disable(mask);
} }

View file

@ -62,9 +62,9 @@ config COUNTER_RTC2
select NRFX_RTC2 select NRFX_RTC2
# Internal flag which detects if PPI wrap feature is enabled for any instance # Internal flag which detects if PPI wrap feature is enabled for any instance
if $(dt_int_val,DT_NORDIC_NRF_RTC_0_PPI_WRAP) > 0 || \ if $(dt_int_val,DT_INST_0_NORDIC_NRF_RTC_PPI_WRAP) > 0 || \
$(dt_int_val,DT_NORDIC_NRF_RTC_1_PPI_WRAP) > 0 || \ $(dt_int_val,DT_INST_1_NORDIC_NRF_RTC_PPI_WRAP) > 0 || \
$(dt_int_val,DT_NORDIC_NRF_RTC_2_PPI_WRAP) > 0 $(dt_int_val,DT_INST_2_NORDIC_NRF_RTC_PPI_WRAP) > 0
config COUNTER_RTC_WITH_PPI_WRAP config COUNTER_RTC_WITH_PPI_WRAP
bool bool

View file

@ -340,32 +340,32 @@ ISR_DIRECT_DECLARE(counter_gecko_isr_0)
return 1; return 1;
} }
BUILD_ASSERT((DT_SILABS_GECKO_RTCC_0_PRESCALER > 0U) && BUILD_ASSERT((DT_INST_0_SILABS_GECKO_RTCC_PRESCALER > 0U) &&
(DT_SILABS_GECKO_RTCC_0_PRESCALER <= 32768U)); (DT_INST_0_SILABS_GECKO_RTCC_PRESCALER <= 32768U));
static void counter_gecko_0_irq_config(void) static void counter_gecko_0_irq_config(void)
{ {
IRQ_DIRECT_CONNECT(DT_SILABS_GECKO_RTCC_0_IRQ_0, IRQ_DIRECT_CONNECT(DT_INST_0_SILABS_GECKO_RTCC_IRQ_0,
DT_SILABS_GECKO_RTCC_0_IRQ_0_PRIORITY, DT_INST_0_SILABS_GECKO_RTCC_IRQ_0_PRIORITY,
counter_gecko_isr_0, 0); counter_gecko_isr_0, 0);
irq_enable(DT_SILABS_GECKO_RTCC_0_IRQ_0); irq_enable(DT_INST_0_SILABS_GECKO_RTCC_IRQ_0);
} }
static const struct counter_gecko_config counter_gecko_0_config = { static const struct counter_gecko_config counter_gecko_0_config = {
.info = { .info = {
.max_top_value = RTCC_MAX_VALUE, .max_top_value = RTCC_MAX_VALUE,
.freq = DT_SILABS_GECKO_RTCC_0_CLOCK_FREQUENCY / .freq = DT_INST_0_SILABS_GECKO_RTCC_CLOCK_FREQUENCY /
DT_SILABS_GECKO_RTCC_0_PRESCALER, DT_INST_0_SILABS_GECKO_RTCC_PRESCALER,
.flags = COUNTER_CONFIG_INFO_COUNT_UP, .flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = RTCC_ALARM_NUM, .channels = RTCC_ALARM_NUM,
}, },
.irq_config = counter_gecko_0_irq_config, .irq_config = counter_gecko_0_irq_config,
.prescaler = DT_SILABS_GECKO_RTCC_0_PRESCALER, .prescaler = DT_INST_0_SILABS_GECKO_RTCC_PRESCALER,
}; };
static struct counter_gecko_data counter_gecko_0_data; static struct counter_gecko_data counter_gecko_0_data;
DEVICE_AND_API_INIT(counter_gecko_0, DT_SILABS_GECKO_RTCC_0_LABEL, DEVICE_AND_API_INIT(counter_gecko_0, DT_INST_0_SILABS_GECKO_RTCC_LABEL,
counter_gecko_init, &counter_gecko_0_data, &counter_gecko_0_config, counter_gecko_init, &counter_gecko_0_data, &counter_gecko_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_gecko_driver_api); &counter_gecko_driver_api);

View file

@ -256,8 +256,8 @@ static struct mcux_rtc_config mcux_rtc_config_0 = {
.irq_config_func = mcux_rtc_irq_config_0, .irq_config_func = mcux_rtc_irq_config_0,
.info = { .info = {
.max_top_value = UINT32_MAX, .max_top_value = UINT32_MAX,
.freq = DT_NXP_KINETIS_RTC_0_CLOCK_FREQUENCY / .freq = DT_INST_0_NXP_KINETIS_RTC_CLOCK_FREQUENCY /
DT_NXP_KINETIS_RTC_0_PRESCALER, DT_INST_0_NXP_KINETIS_RTC_PRESCALER,
.flags = COUNTER_CONFIG_INFO_COUNT_UP, .flags = COUNTER_CONFIG_INFO_COUNT_UP,
.channels = 1, .channels = 1,
}, },

View file

@ -267,7 +267,7 @@ static int init_rtc(struct device *dev,
const nrfx_rtc_t *rtc = &nrfx_config->rtc; const nrfx_rtc_t *rtc = &nrfx_config->rtc;
int err; int err;
clock = device_get_binding(DT_NORDIC_NRF_CLOCK_0_LABEL "_32K"); clock = device_get_binding(DT_INST_0_NORDIC_NRF_CLOCK_LABEL "_32K");
if (!clock) { if (!clock) {
return -ENODEV; return -ENODEV;
} }

View file

@ -165,14 +165,14 @@ static const struct dtmr_cmsdk_apb_cfg dtmr_cmsdk_apb_cfg_0 = {
.flags = 0, .flags = 0,
.channels = 0U, .channels = 0U,
}, },
.dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_ARM_CMSDK_DTIMER_0_BASE_ADDRESS), .dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_INST_0_ARM_CMSDK_DTIMER_BASE_ADDRESS),
.dtimer_config_func = dtimer_cmsdk_apb_config_0, .dtimer_config_func = dtimer_cmsdk_apb_config_0,
.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_ARM_CMSDK_DTIMER_0_BASE_ADDRESS,}, .device = DT_INST_0_ARM_CMSDK_DTIMER_BASE_ADDRESS,},
.dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_ARM_CMSDK_DTIMER_0_BASE_ADDRESS,}, .device = DT_INST_0_ARM_CMSDK_DTIMER_BASE_ADDRESS,},
.dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_ARM_CMSDK_DTIMER_0_BASE_ADDRESS,}, .device = DT_INST_0_ARM_CMSDK_DTIMER_BASE_ADDRESS,},
}; };
static struct dtmr_cmsdk_apb_dev_data dtmr_cmsdk_apb_dev_data_0 = { static struct dtmr_cmsdk_apb_dev_data dtmr_cmsdk_apb_dev_data_0 = {
@ -180,7 +180,7 @@ static struct dtmr_cmsdk_apb_dev_data dtmr_cmsdk_apb_dev_data_0 = {
}; };
DEVICE_AND_API_INIT(dtmr_cmsdk_apb_0, DEVICE_AND_API_INIT(dtmr_cmsdk_apb_0,
DT_ARM_CMSDK_DTIMER_0_LABEL, DT_INST_0_ARM_CMSDK_DTIMER_LABEL,
dtmr_cmsdk_apb_init, dtmr_cmsdk_apb_init,
&dtmr_cmsdk_apb_dev_data_0, &dtmr_cmsdk_apb_dev_data_0,
&dtmr_cmsdk_apb_cfg_0, POST_KERNEL, &dtmr_cmsdk_apb_cfg_0, POST_KERNEL,
@ -189,10 +189,10 @@ DEVICE_AND_API_INIT(dtmr_cmsdk_apb_0,
static void dtimer_cmsdk_apb_config_0(struct device *dev) static void dtimer_cmsdk_apb_config_0(struct device *dev)
{ {
IRQ_CONNECT(DT_ARM_CMSDK_DTIMER_0_IRQ_0, IRQ_CONNECT(DT_INST_0_ARM_CMSDK_DTIMER_IRQ_0,
DT_ARM_CMSDK_DTIMER_0_IRQ_0_PRIORITY, DT_INST_0_ARM_CMSDK_DTIMER_IRQ_0_PRIORITY,
dtmr_cmsdk_apb_isr, dtmr_cmsdk_apb_isr,
DEVICE_GET(dtmr_cmsdk_apb_0), 0); DEVICE_GET(dtmr_cmsdk_apb_0), 0);
irq_enable(DT_ARM_CMSDK_DTIMER_0_IRQ_0); irq_enable(DT_INST_0_ARM_CMSDK_DTIMER_IRQ_0);
} }
#endif /* DT_ARM_CMSDK_DTIMER_0 */ #endif /* DT_ARM_CMSDK_DTIMER_0 */

View file

@ -167,14 +167,14 @@ static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_0 = {
.flags = 0, .flags = 0,
.channels = 0U, .channels = 0U,
}, },
.timer = ((volatile struct timer_cmsdk_apb *)DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS), .timer = ((volatile struct timer_cmsdk_apb *)DT_INST_0_ARM_CMSDK_TIMER_BASE_ADDRESS),
.timer_config_func = timer_cmsdk_apb_config_0, .timer_config_func = timer_cmsdk_apb_config_0,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS,}, .device = DT_INST_0_ARM_CMSDK_TIMER_BASE_ADDRESS,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS,}, .device = DT_INST_0_ARM_CMSDK_TIMER_BASE_ADDRESS,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_ARM_CMSDK_TIMER_0_BASE_ADDRESS,}, .device = DT_INST_0_ARM_CMSDK_TIMER_BASE_ADDRESS,},
}; };
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = { static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = {
@ -182,7 +182,7 @@ static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = {
}; };
DEVICE_AND_API_INIT(tmr_cmsdk_apb_0, DEVICE_AND_API_INIT(tmr_cmsdk_apb_0,
DT_ARM_CMSDK_TIMER_0_LABEL, DT_INST_0_ARM_CMSDK_TIMER_LABEL,
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_0, tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_0,
&tmr_cmsdk_apb_cfg_0, POST_KERNEL, &tmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -190,10 +190,10 @@ DEVICE_AND_API_INIT(tmr_cmsdk_apb_0,
static void timer_cmsdk_apb_config_0(struct device *dev) static void timer_cmsdk_apb_config_0(struct device *dev)
{ {
IRQ_CONNECT(DT_ARM_CMSDK_TIMER_0_IRQ_0, DT_ARM_CMSDK_TIMER_0_IRQ_0_PRIORITY, IRQ_CONNECT(DT_INST_0_ARM_CMSDK_TIMER_IRQ_0, DT_INST_0_ARM_CMSDK_TIMER_IRQ_0_PRIORITY,
tmr_cmsdk_apb_isr, tmr_cmsdk_apb_isr,
DEVICE_GET(tmr_cmsdk_apb_0), 0); DEVICE_GET(tmr_cmsdk_apb_0), 0);
irq_enable(DT_ARM_CMSDK_TIMER_0_IRQ_0); irq_enable(DT_INST_0_ARM_CMSDK_TIMER_IRQ_0);
} }
#endif /* DT_ARM_CMSDK_TIMER_0 */ #endif /* DT_ARM_CMSDK_TIMER_0 */
@ -208,14 +208,14 @@ static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_1 = {
.flags = 0, .flags = 0,
.channels = 0U, .channels = 0U,
}, },
.timer = ((volatile struct timer_cmsdk_apb *)DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS), .timer = ((volatile struct timer_cmsdk_apb *)DT_INST_1_ARM_CMSDK_TIMER_BASE_ADDRESS),
.timer_config_func = timer_cmsdk_apb_config_1, .timer_config_func = timer_cmsdk_apb_config_1,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS,}, .device = DT_INST_1_ARM_CMSDK_TIMER_BASE_ADDRESS,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS,}, .device = DT_INST_1_ARM_CMSDK_TIMER_BASE_ADDRESS,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_ARM_CMSDK_TIMER_1_BASE_ADDRESS,}, .device = DT_INST_1_ARM_CMSDK_TIMER_BASE_ADDRESS,},
}; };
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = { static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = {
@ -223,7 +223,7 @@ static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = {
}; };
DEVICE_AND_API_INIT(tmr_cmsdk_apb_1, DEVICE_AND_API_INIT(tmr_cmsdk_apb_1,
DT_ARM_CMSDK_TIMER_1_LABEL, DT_INST_1_ARM_CMSDK_TIMER_LABEL,
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_1, tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_1,
&tmr_cmsdk_apb_cfg_1, POST_KERNEL, &tmr_cmsdk_apb_cfg_1, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -231,9 +231,9 @@ DEVICE_AND_API_INIT(tmr_cmsdk_apb_1,
static void timer_cmsdk_apb_config_1(struct device *dev) static void timer_cmsdk_apb_config_1(struct device *dev)
{ {
IRQ_CONNECT(DT_ARM_CMSDK_TIMER_1_IRQ_0, DT_ARM_CMSDK_TIMER_1_IRQ_0_PRIORITY, IRQ_CONNECT(DT_INST_1_ARM_CMSDK_TIMER_IRQ_0, DT_INST_1_ARM_CMSDK_TIMER_IRQ_0_PRIORITY,
tmr_cmsdk_apb_isr, tmr_cmsdk_apb_isr,
DEVICE_GET(tmr_cmsdk_apb_1), 0); DEVICE_GET(tmr_cmsdk_apb_1), 0);
irq_enable(DT_ARM_CMSDK_TIMER_1_IRQ_0); irq_enable(DT_INST_1_ARM_CMSDK_TIMER_IRQ_0);
} }
#endif /* DT_ARM_CMSDK_TIMER_1 */ #endif /* DT_ARM_CMSDK_TIMER_1 */

View file

@ -18,13 +18,13 @@ LOG_MODULE_REGISTER(display_ili9340);
#include <string.h> #include <string.h>
struct ili9340_data { struct ili9340_data {
#ifdef DT_ILITEK_ILI9340_0_RESET_GPIOS_CONTROLLER #ifdef DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_CONTROLLER
struct device *reset_gpio; struct device *reset_gpio;
#endif #endif
struct device *command_data_gpio; struct device *command_data_gpio;
struct device *spi_dev; struct device *spi_dev;
struct spi_config spi_config; struct spi_config spi_config;
#ifdef DT_ILITEK_ILI9340_0_CS_GPIO_CONTROLLER #ifdef DT_INST_0_ILITEK_ILI9340_CS_GPIO_CONTROLLER
struct spi_cs_control cs_ctrl; struct spi_cs_control cs_ctrl;
#endif #endif
}; };
@ -51,55 +51,55 @@ static int ili9340_init(struct device *dev)
LOG_DBG("Initializing display driver"); LOG_DBG("Initializing display driver");
data->spi_dev = device_get_binding(DT_ILITEK_ILI9340_0_BUS_NAME); data->spi_dev = device_get_binding(DT_INST_0_ILITEK_ILI9340_BUS_NAME);
if (data->spi_dev == NULL) { if (data->spi_dev == NULL) {
LOG_ERR("Could not get SPI device for ILI9340"); LOG_ERR("Could not get SPI device for ILI9340");
return -EPERM; return -EPERM;
} }
data->spi_config.frequency = DT_ILITEK_ILI9340_0_SPI_MAX_FREQUENCY; data->spi_config.frequency = DT_INST_0_ILITEK_ILI9340_SPI_MAX_FREQUENCY;
data->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); data->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8);
data->spi_config.slave = DT_ILITEK_ILI9340_0_BASE_ADDRESS; data->spi_config.slave = DT_INST_0_ILITEK_ILI9340_BASE_ADDRESS;
#ifdef DT_ILITEK_ILI9340_0_CS_GPIO_CONTROLLER #ifdef DT_INST_0_ILITEK_ILI9340_CS_GPIO_CONTROLLER
data->cs_ctrl.gpio_dev = data->cs_ctrl.gpio_dev =
device_get_binding(DT_ILITEK_ILI9340_0_CS_GPIO_CONTROLLER); device_get_binding(DT_INST_0_ILITEK_ILI9340_CS_GPIO_CONTROLLER);
data->cs_ctrl.gpio_pin = DT_ILITEK_ILI9340_0_CS_GPIO_PIN; data->cs_ctrl.gpio_pin = DT_INST_0_ILITEK_ILI9340_CS_GPIO_PIN;
data->cs_ctrl.delay = 0U; data->cs_ctrl.delay = 0U;
data->spi_config.cs = &(data->cs_ctrl); data->spi_config.cs = &(data->cs_ctrl);
#else #else
data->spi_config.cs = NULL; data->spi_config.cs = NULL;
#endif #endif
#ifdef DT_ILITEK_ILI9340_0_RESET_GPIOS_CONTROLLER #ifdef DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_CONTROLLER
data->reset_gpio = data->reset_gpio =
device_get_binding(DT_ILITEK_ILI9340_0_RESET_GPIOS_CONTROLLER); device_get_binding(DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_CONTROLLER);
if (data->reset_gpio == NULL) { if (data->reset_gpio == NULL) {
LOG_ERR("Could not get GPIO port for ILI9340 reset"); LOG_ERR("Could not get GPIO port for ILI9340 reset");
return -EPERM; return -EPERM;
} }
gpio_pin_configure(data->reset_gpio, DT_ILITEK_ILI9340_0_RESET_GPIOS_PIN, gpio_pin_configure(data->reset_gpio, DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
#endif #endif
data->command_data_gpio = data->command_data_gpio =
device_get_binding(DT_ILITEK_ILI9340_0_CMD_DATA_GPIOS_CONTROLLER); device_get_binding(DT_INST_0_ILITEK_ILI9340_CMD_DATA_GPIOS_CONTROLLER);
if (data->command_data_gpio == NULL) { if (data->command_data_gpio == NULL) {
LOG_ERR("Could not get GPIO port for ILI9340 command/data"); LOG_ERR("Could not get GPIO port for ILI9340 command/data");
return -EPERM; return -EPERM;
} }
gpio_pin_configure(data->command_data_gpio, DT_ILITEK_ILI9340_0_CMD_DATA_GPIOS_PIN, gpio_pin_configure(data->command_data_gpio, DT_INST_0_ILITEK_ILI9340_CMD_DATA_GPIOS_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
#ifdef DT_ILITEK_ILI9340_0_RESET_GPIOS_CONTROLLER #ifdef DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_CONTROLLER
LOG_DBG("Resetting display driver"); LOG_DBG("Resetting display driver");
gpio_pin_write(data->reset_gpio, DT_ILITEK_ILI9340_0_RESET_GPIOS_PIN, 1); gpio_pin_write(data->reset_gpio, DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_PIN, 1);
k_sleep(1); k_sleep(1);
gpio_pin_write(data->reset_gpio, DT_ILITEK_ILI9340_0_RESET_GPIOS_PIN, 0); gpio_pin_write(data->reset_gpio, DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_PIN, 0);
k_sleep(1); k_sleep(1);
gpio_pin_write(data->reset_gpio, DT_ILITEK_ILI9340_0_RESET_GPIOS_PIN, 1); gpio_pin_write(data->reset_gpio, DT_INST_0_ILITEK_ILI9340_RESET_GPIOS_PIN, 1);
k_sleep(5); k_sleep(5);
#endif #endif
@ -266,7 +266,7 @@ void ili9340_transmit(struct ili9340_data *data, u8_t cmd, void *tx_data,
struct spi_buf tx_buf = { .buf = &cmd, .len = 1 }; struct spi_buf tx_buf = { .buf = &cmd, .len = 1 };
struct spi_buf_set tx_bufs = { .buffers = &tx_buf, .count = 1 }; struct spi_buf_set tx_bufs = { .buffers = &tx_buf, .count = 1 };
gpio_pin_write(data->command_data_gpio, DT_ILITEK_ILI9340_0_CMD_DATA_GPIOS_PIN, gpio_pin_write(data->command_data_gpio, DT_INST_0_ILITEK_ILI9340_CMD_DATA_GPIOS_PIN,
ILI9340_CMD_DATA_PIN_COMMAND); ILI9340_CMD_DATA_PIN_COMMAND);
spi_write(data->spi_dev, &data->spi_config, &tx_bufs); spi_write(data->spi_dev, &data->spi_config, &tx_bufs);
@ -274,7 +274,7 @@ void ili9340_transmit(struct ili9340_data *data, u8_t cmd, void *tx_data,
tx_buf.buf = tx_data; tx_buf.buf = tx_data;
tx_buf.len = tx_len; tx_buf.len = tx_len;
gpio_pin_write(data->command_data_gpio, gpio_pin_write(data->command_data_gpio,
DT_ILITEK_ILI9340_0_CMD_DATA_GPIOS_PIN, DT_INST_0_ILITEK_ILI9340_CMD_DATA_GPIOS_PIN,
ILI9340_CMD_DATA_PIN_DATA); ILI9340_CMD_DATA_PIN_DATA);
spi_write(data->spi_dev, &data->spi_config, &tx_bufs); spi_write(data->spi_dev, &data->spi_config, &tx_bufs);
} }
@ -295,6 +295,6 @@ static const struct display_driver_api ili9340_api = {
static struct ili9340_data ili9340_data; static struct ili9340_data ili9340_data;
DEVICE_AND_API_INIT(ili9340, DT_ILITEK_ILI9340_0_LABEL, &ili9340_init, DEVICE_AND_API_INIT(ili9340, DT_INST_0_ILITEK_ILI9340_LABEL, &ili9340_init,
&ili9340_data, NULL, APPLICATION, &ili9340_data, NULL, APPLICATION,
CONFIG_APPLICATION_INIT_PRIORITY, &ili9340_api); CONFIG_APPLICATION_INIT_PRIORITY, &ili9340_api);

View file

@ -226,7 +226,7 @@ static const struct display_driver_api mcux_elcdif_api = {
static void mcux_elcdif_config_func_1(struct device *dev); static void mcux_elcdif_config_func_1(struct device *dev);
static struct mcux_elcdif_config mcux_elcdif_config_1 = { static struct mcux_elcdif_config mcux_elcdif_config_1 = {
.base = (LCDIF_Type *) DT_FSL_IMX6SX_LCDIF_0_BASE_ADDRESS, .base = (LCDIF_Type *) DT_INST_0_FSL_IMX6SX_LCDIF_BASE_ADDRESS,
.irq_config_func = mcux_elcdif_config_func_1, .irq_config_func = mcux_elcdif_config_func_1,
#ifdef CONFIG_MCUX_ELCDIF_PANEL_RK043FN02H #ifdef CONFIG_MCUX_ELCDIF_PANEL_RK043FN02H
.rgb_mode = { .rgb_mode = {
@ -252,7 +252,7 @@ static struct mcux_elcdif_config mcux_elcdif_config_1 = {
static struct mcux_elcdif_data mcux_elcdif_data_1; static struct mcux_elcdif_data mcux_elcdif_data_1;
DEVICE_AND_API_INIT(mcux_elcdif_1, DT_FSL_IMX6SX_LCDIF_0_LABEL, DEVICE_AND_API_INIT(mcux_elcdif_1, DT_INST_0_FSL_IMX6SX_LCDIF_LABEL,
&mcux_elcdif_init, &mcux_elcdif_init,
&mcux_elcdif_data_1, &mcux_elcdif_config_1, &mcux_elcdif_data_1, &mcux_elcdif_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -260,9 +260,9 @@ DEVICE_AND_API_INIT(mcux_elcdif_1, DT_FSL_IMX6SX_LCDIF_0_LABEL,
static void mcux_elcdif_config_func_1(struct device *dev) static void mcux_elcdif_config_func_1(struct device *dev)
{ {
IRQ_CONNECT(DT_FSL_IMX6SX_LCDIF_0_IRQ_0, IRQ_CONNECT(DT_INST_0_FSL_IMX6SX_LCDIF_IRQ_0,
DT_FSL_IMX6SX_LCDIF_0_IRQ_0_PRIORITY, DT_INST_0_FSL_IMX6SX_LCDIF_IRQ_0_PRIORITY,
mcux_elcdif_isr, DEVICE_GET(mcux_elcdif_1), 0); mcux_elcdif_isr, DEVICE_GET(mcux_elcdif_1), 0);
irq_enable(DT_FSL_IMX6SX_LCDIF_0_IRQ_0); irq_enable(DT_INST_0_FSL_IMX6SX_LCDIF_IRQ_0);
} }

View file

@ -17,19 +17,19 @@ LOG_MODULE_REGISTER(ssd1306);
#include "ssd1306_regs.h" #include "ssd1306_regs.h"
#include <display/cfb.h> #include <display/cfb.h>
#if DT_SOLOMON_SSD1306FB_0_SEGMENT_REMAP == 1 #if DT_INST_0_SOLOMON_SSD1306FB_SEGMENT_REMAP == 1
#define SSD1306_PANEL_SEGMENT_REMAP true #define SSD1306_PANEL_SEGMENT_REMAP true
#else #else
#define SSD1306_PANEL_SEGMENT_REMAP false #define SSD1306_PANEL_SEGMENT_REMAP false
#endif #endif
#if DT_SOLOMON_SSD1306FB_0_COM_INVDIR == 1 #if DT_INST_0_SOLOMON_SSD1306FB_COM_INVDIR == 1
#define SSD1306_PANEL_COM_INVDIR true #define SSD1306_PANEL_COM_INVDIR true
#else #else
#define SSD1306_PANEL_COM_INVDIR false #define SSD1306_PANEL_COM_INVDIR false
#endif #endif
#define SSD1306_PANEL_NUMOF_PAGES (DT_SOLOMON_SSD1306FB_0_HEIGHT / 8) #define SSD1306_PANEL_NUMOF_PAGES (DT_INST_0_SOLOMON_SSD1306FB_HEIGHT / 8)
#define SSD1306_CLOCK_DIV_RATIO 0x0 #define SSD1306_CLOCK_DIV_RATIO 0x0
#define SSD1306_CLOCK_FREQUENCY 0x8 #define SSD1306_CLOCK_FREQUENCY 0x8
#define SSD1306_PANEL_MUX_RATIO 63 #define SSD1306_PANEL_MUX_RATIO 63
@ -56,21 +56,21 @@ struct ssd1306_data {
static inline int ssd1306_reg_read(struct ssd1306_data *driver, static inline int ssd1306_reg_read(struct ssd1306_data *driver,
u8_t reg, u8_t * const val) u8_t reg, u8_t * const val)
{ {
return i2c_reg_read_byte(driver->i2c, DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS, return i2c_reg_read_byte(driver->i2c, DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS,
reg, val); reg, val);
} }
static inline int ssd1306_reg_write(struct ssd1306_data *driver, static inline int ssd1306_reg_write(struct ssd1306_data *driver,
u8_t reg, u8_t val) u8_t reg, u8_t val)
{ {
return i2c_reg_write_byte(driver->i2c, DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS, return i2c_reg_write_byte(driver->i2c, DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS,
reg, val); reg, val);
} }
static inline int ssd1306_reg_update(struct ssd1306_data *driver, u8_t reg, static inline int ssd1306_reg_update(struct ssd1306_data *driver, u8_t reg,
u8_t mask, u8_t val) u8_t mask, u8_t val)
{ {
return i2c_reg_update_byte(driver->i2c, DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS, return i2c_reg_update_byte(driver->i2c, DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS,
reg, mask, val); reg, mask, val);
} }
@ -89,7 +89,7 @@ static inline int ssd1306_set_panel_orientation(struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS); DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS);
} }
static inline int ssd1306_set_timing_setting(struct device *dev) static inline int ssd1306_set_timing_setting(struct device *dev)
@ -103,7 +103,7 @@ static inline int ssd1306_set_timing_setting(struct device *dev)
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_CHARGE_PERIOD, SSD1306_SET_CHARGE_PERIOD,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
DT_SOLOMON_SSD1306FB_0_PRECHARGEP, DT_INST_0_SOLOMON_SSD1306FB_PRECHARGEP,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_VCOM_DESELECT_LEVEL, SSD1306_SET_VCOM_DESELECT_LEVEL,
SSD1306_CONTROL_LAST_BYTE_CMD, SSD1306_CONTROL_LAST_BYTE_CMD,
@ -111,7 +111,7 @@ static inline int ssd1306_set_timing_setting(struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS); DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS);
} }
static inline int ssd1306_set_hardware_config(struct device *dev) static inline int ssd1306_set_hardware_config(struct device *dev)
@ -123,7 +123,7 @@ static inline int ssd1306_set_hardware_config(struct device *dev)
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_DISPLAY_OFFSET, SSD1306_SET_DISPLAY_OFFSET,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
DT_SOLOMON_SSD1306FB_0_DISPLAY_OFFSET, DT_INST_0_SOLOMON_SSD1306FB_DISPLAY_OFFSET,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_PADS_HW_CONFIG, SSD1306_SET_PADS_HW_CONFIG,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
@ -135,7 +135,7 @@ static inline int ssd1306_set_hardware_config(struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS); DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS);
} }
static inline int ssd1306_set_charge_pump(const struct device *dev) static inline int ssd1306_set_charge_pump(const struct device *dev)
@ -159,7 +159,7 @@ static inline int ssd1306_set_charge_pump(const struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS); DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS);
} }
int ssd1306_resume(const struct device *dev) int ssd1306_resume(const struct device *dev)
@ -191,11 +191,11 @@ int ssd1306_write_page(const struct device *dev, u8_t page, void const *data,
#endif #endif
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_LOWER_COL_ADDRESS | SSD1306_SET_LOWER_COL_ADDRESS |
(DT_SOLOMON_SSD1306FB_0_SEGMENT_OFFSET & (DT_INST_0_SOLOMON_SSD1306FB_SEGMENT_OFFSET &
SSD1306_SET_LOWER_COL_ADDRESS_MASK), SSD1306_SET_LOWER_COL_ADDRESS_MASK),
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_HIGHER_COL_ADDRESS | SSD1306_SET_HIGHER_COL_ADDRESS |
((DT_SOLOMON_SSD1306FB_0_SEGMENT_OFFSET >> 4) & ((DT_INST_0_SOLOMON_SSD1306FB_SEGMENT_OFFSET >> 4) &
SSD1306_SET_LOWER_COL_ADDRESS_MASK), SSD1306_SET_LOWER_COL_ADDRESS_MASK),
SSD1306_CONTROL_LAST_BYTE_CMD, SSD1306_CONTROL_LAST_BYTE_CMD,
SSD1306_SET_PAGE_START_ADDRESS | page SSD1306_SET_PAGE_START_ADDRESS | page
@ -210,11 +210,11 @@ int ssd1306_write_page(const struct device *dev, u8_t page, void const *data,
} }
if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS)) { DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS)) {
return -1; return -1;
} }
return i2c_burst_write(driver->i2c, DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS, return i2c_burst_write(driver->i2c, DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS,
SSD1306_CONTROL_LAST_BYTE_DATA, SSD1306_CONTROL_LAST_BYTE_DATA,
data, length); data, length);
} }
@ -266,27 +266,27 @@ int ssd1306_write(const struct device *dev, const u16_t x, const u16_t y,
}; };
if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS)) { DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS)) {
LOG_ERR("Failed to write command"); LOG_ERR("Failed to write command");
return -1; return -1;
} }
return i2c_burst_write(driver->i2c, DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS, return i2c_burst_write(driver->i2c, DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS,
SSD1306_CONTROL_LAST_BYTE_DATA, SSD1306_CONTROL_LAST_BYTE_DATA,
(u8_t *)buf, desc->buf_size); (u8_t *)buf, desc->buf_size);
#elif defined(CONFIG_SSD1306_SH1106_COMPATIBLE) #elif defined(CONFIG_SSD1306_SH1106_COMPATIBLE)
if (desc->buf_size != if (desc->buf_size !=
(SSD1306_PANEL_NUMOF_PAGES * DT_SOLOMON_SSD1306FB_0_WIDTH)) { (SSD1306_PANEL_NUMOF_PAGES * DT_INST_0_SOLOMON_SSD1306FB_WIDTH)) {
return -1; return -1;
} }
for (size_t pidx = 0; pidx < SSD1306_PANEL_NUMOF_PAGES; pidx++) { for (size_t pidx = 0; pidx < SSD1306_PANEL_NUMOF_PAGES; pidx++) {
if (ssd1306_write_page(dev, pidx, buf, if (ssd1306_write_page(dev, pidx, buf,
DT_SOLOMON_SSD1306FB_0_WIDTH)) { DT_INST_0_SOLOMON_SSD1306FB_WIDTH)) {
return -1; return -1;
} }
buf = (u8_t *)buf + DT_SOLOMON_SSD1306FB_0_WIDTH; buf = (u8_t *)buf + DT_INST_0_SOLOMON_SSD1306FB_WIDTH;
} }
#endif #endif
@ -326,15 +326,15 @@ int ssd1306_set_contrast(const struct device *dev, const u8_t contrast)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS); DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS);
} }
static void ssd1306_get_capabilities(const struct device *dev, static void ssd1306_get_capabilities(const struct device *dev,
struct display_capabilities *caps) struct display_capabilities *caps)
{ {
memset(caps, 0, sizeof(struct display_capabilities)); memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = DT_SOLOMON_SSD1306FB_0_WIDTH; caps->x_resolution = DT_INST_0_SOLOMON_SSD1306FB_WIDTH;
caps->y_resolution = DT_SOLOMON_SSD1306FB_0_HEIGHT; caps->y_resolution = DT_INST_0_SOLOMON_SSD1306FB_HEIGHT;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO10; caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
caps->current_pixel_format = PIXEL_FORMAT_MONO10; caps->current_pixel_format = PIXEL_FORMAT_MONO10;
caps->screen_info = SCREEN_INFO_MONO_VTILED; caps->screen_info = SCREEN_INFO_MONO_VTILED;
@ -369,12 +369,12 @@ static int ssd1306_init_device(struct device *dev)
SSD1306_SET_NORMAL_DISPLAY, SSD1306_SET_NORMAL_DISPLAY,
}; };
#ifdef DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_CONTROLLER #ifdef DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_CONTROLLER
gpio_pin_write(driver->reset, DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_PIN, 1); gpio_pin_write(driver->reset, DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_PIN, 1);
k_sleep(SSD1306_RESET_DELAY); k_sleep(SSD1306_RESET_DELAY);
gpio_pin_write(driver->reset, DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_PIN, 0); gpio_pin_write(driver->reset, DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_PIN, 0);
k_sleep(SSD1306_RESET_DELAY); k_sleep(SSD1306_RESET_DELAY);
gpio_pin_write(driver->reset, DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_PIN, 1); gpio_pin_write(driver->reset, DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_PIN, 1);
#endif #endif
/* Turn display off */ /* Turn display off */
@ -400,7 +400,7 @@ static int ssd1306_init_device(struct device *dev)
} }
if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
DT_SOLOMON_SSD1306FB_0_BASE_ADDRESS)) { DT_INST_0_SOLOMON_SSD1306FB_BASE_ADDRESS)) {
return -EIO; return -EIO;
} }
@ -419,22 +419,22 @@ static int ssd1306_init(struct device *dev)
LOG_DBG(""); LOG_DBG("");
driver->i2c = device_get_binding(DT_SOLOMON_SSD1306FB_0_BUS_NAME); driver->i2c = device_get_binding(DT_INST_0_SOLOMON_SSD1306FB_BUS_NAME);
if (driver->i2c == NULL) { if (driver->i2c == NULL) {
LOG_ERR("Failed to get pointer to %s device!", LOG_ERR("Failed to get pointer to %s device!",
DT_SOLOMON_SSD1306FB_0_BUS_NAME); DT_INST_0_SOLOMON_SSD1306FB_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
#ifdef DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_CONTROLLER #ifdef DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_CONTROLLER
driver->reset = device_get_binding(DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_CONTROLLER); driver->reset = device_get_binding(DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_CONTROLLER);
if (driver->reset == NULL) { if (driver->reset == NULL) {
LOG_ERR("Failed to get pointer to %s device!", LOG_ERR("Failed to get pointer to %s device!",
DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_CONTROLLER); DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_CONTROLLER);
return -EINVAL; return -EINVAL;
} }
gpio_pin_configure(driver->reset, DT_SOLOMON_SSD1306FB_0_RESET_GPIOS_PIN, gpio_pin_configure(driver->reset, DT_INST_0_SOLOMON_SSD1306FB_RESET_GPIOS_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
#endif #endif
@ -461,7 +461,7 @@ static struct display_driver_api ssd1306_driver_api = {
.set_orientation = ssd1306_set_orientation, .set_orientation = ssd1306_set_orientation,
}; };
DEVICE_AND_API_INIT(ssd1306, DT_SOLOMON_SSD1306FB_0_LABEL, ssd1306_init, DEVICE_AND_API_INIT(ssd1306, DT_INST_0_SOLOMON_SSD1306FB_LABEL, ssd1306_init,
&ssd1306_driver, NULL, &ssd1306_driver, NULL,
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY,
&ssd1306_driver_api); &ssd1306_driver_api);

View file

@ -19,8 +19,8 @@ LOG_MODULE_REGISTER(ssd1673);
#include "ssd1673_regs.h" #include "ssd1673_regs.h"
#include <display/cfb.h> #include <display/cfb.h>
#define EPD_PANEL_WIDTH DT_SOLOMON_SSD1673FB_0_WIDTH #define EPD_PANEL_WIDTH DT_INST_0_SOLOMON_SSD1673FB_WIDTH
#define EPD_PANEL_HEIGHT DT_SOLOMON_SSD1673FB_0_HEIGHT #define EPD_PANEL_HEIGHT DT_INST_0_SOLOMON_SSD1673FB_HEIGHT
#define EPD_PANEL_NUMOF_COLUMS EPD_PANEL_WIDTH #define EPD_PANEL_NUMOF_COLUMS EPD_PANEL_WIDTH
#define EPD_PANEL_NUMOF_ROWS_PER_PAGE 8 #define EPD_PANEL_NUMOF_ROWS_PER_PAGE 8
#define EPD_PANEL_NUMOF_PAGES (EPD_PANEL_HEIGHT / \ #define EPD_PANEL_NUMOF_PAGES (EPD_PANEL_HEIGHT / \
@ -39,7 +39,7 @@ struct ssd1673_data {
struct device *busy; struct device *busy;
struct device *spi_dev; struct device *spi_dev;
struct spi_config spi_config; struct spi_config spi_config;
#if defined(DT_SOLOMON_SSD1673FB_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_SOLOMON_SSD1673FB_CS_GPIO_CONTROLLER)
struct spi_cs_control cs_ctrl; struct spi_cs_control cs_ctrl;
#endif #endif
u8_t scan_mode; u8_t scan_mode;
@ -98,7 +98,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver,
struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)}; struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)};
struct spi_buf_set buf_set = {.buffers = &buf, .count = 1}; struct spi_buf_set buf_set = {.buffers = &buf, .count = 1};
gpio_pin_write(driver->dc, DT_SOLOMON_SSD1673FB_0_DC_GPIOS_PIN, 0); gpio_pin_write(driver->dc, DT_INST_0_SOLOMON_SSD1673FB_DC_GPIOS_PIN, 0);
err = spi_write(driver->spi_dev, &driver->spi_config, &buf_set); err = spi_write(driver->spi_dev, &driver->spi_config, &buf_set);
if (err < 0) { if (err < 0) {
return err; return err;
@ -107,7 +107,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver,
if (data != NULL) { if (data != NULL) {
buf.buf = data; buf.buf = data;
buf.len = len; buf.len = len;
gpio_pin_write(driver->dc, DT_SOLOMON_SSD1673FB_0_DC_GPIOS_PIN, 1); gpio_pin_write(driver->dc, DT_INST_0_SOLOMON_SSD1673FB_DC_GPIOS_PIN, 1);
err = spi_write(driver->spi_dev, &driver->spi_config, &buf_set); err = spi_write(driver->spi_dev, &driver->spi_config, &buf_set);
if (err < 0) { if (err < 0) {
return err; return err;
@ -121,36 +121,36 @@ static inline void ssd1673_busy_wait(struct ssd1673_data *driver)
{ {
u32_t val = 0U; u32_t val = 0U;
gpio_pin_read(driver->busy, DT_SOLOMON_SSD1673FB_0_BUSY_GPIOS_PIN, &val); gpio_pin_read(driver->busy, DT_INST_0_SOLOMON_SSD1673FB_BUSY_GPIOS_PIN, &val);
while (val) { while (val) {
k_sleep(SSD1673_BUSY_DELAY); k_sleep(SSD1673_BUSY_DELAY);
gpio_pin_read(driver->busy, DT_SOLOMON_SSD1673FB_0_BUSY_GPIOS_PIN, &val); gpio_pin_read(driver->busy, DT_INST_0_SOLOMON_SSD1673FB_BUSY_GPIOS_PIN, &val);
} }
} }
static inline size_t push_x_param(u8_t *data, u16_t x) static inline size_t push_x_param(u8_t *data, u16_t x)
{ {
#if DT_SOLOMON_SSD1673FB_0_PP_WIDTH_BITS == 8 #if DT_INST_0_SOLOMON_SSD1673FB_PP_WIDTH_BITS == 8
data[0] = (u8_t)x; data[0] = (u8_t)x;
return 1; return 1;
#elif DT_SOLOMON_SSD1673FB_0_PP_WIDTH_BITS == 16 #elif DT_INST_0_SOLOMON_SSD1673FB_PP_WIDTH_BITS == 16
sys_put_le16(sys_cpu_to_le16(x), data); sys_put_le16(sys_cpu_to_le16(x), data);
return 2; return 2;
#else #else
#error Unsupported DT_SOLOMON_SSD1673FB_0_PP_WIDTH_BITS value #error Unsupported DT_INST_0_SOLOMON_SSD1673FB_PP_WIDTH_BITS value
#endif #endif
} }
static inline size_t push_y_param(u8_t *data, u16_t y) static inline size_t push_y_param(u8_t *data, u16_t y)
{ {
#if DT_SOLOMON_SSD1673FB_0_PP_HEIGHT_BITS == 8 #if DT_INST_0_SOLOMON_SSD1673FB_PP_HEIGHT_BITS == 8
data[0] = (u8_t)y; data[0] = (u8_t)y;
return 1; return 1;
#elif DT_SOLOMON_SSD1673FB_0_PP_HEIGHT_BITS == 16 #elif DT_INST_0_SOLOMON_SSD1673FB_PP_HEIGHT_BITS == 16
sys_put_le16(sys_cpu_to_le16(y), data); sys_put_le16(sys_cpu_to_le16(y), data);
return 2; return 2;
#else #else
#error Unsupported DT_SOLOMON_SSD1673FB_0_PP_HEIGHT_BITS value #error Unsupported DT_INST_0_SOLOMON_SSD1673FB_PP_HEIGHT_BITS value
#endif #endif
} }
@ -199,7 +199,7 @@ static inline int ssd1673_set_ram_ptr(struct ssd1673_data *driver,
static void ssd1673_set_orientation_internall(struct ssd1673_data *driver) static void ssd1673_set_orientation_internall(struct ssd1673_data *driver)
{ {
#if DT_SOLOMON_SSD1673FB_0_ORIENTATION_FLIPPED == 1 #if DT_INST_0_SOLOMON_SSD1673FB_ORIENTATION_FLIPPED == 1
driver->scan_mode = SSD1673_DATA_ENTRY_XIYDY; driver->scan_mode = SSD1673_DATA_ENTRY_XIYDY;
#else #else
driver->scan_mode = SSD1673_DATA_ENTRY_XDYIY; driver->scan_mode = SSD1673_DATA_ENTRY_XDYIY;
@ -446,7 +446,7 @@ static int ssd1673_clear_and_write_buffer(struct device *dev)
return err; return err;
} }
gpio_pin_write(driver->dc, DT_SOLOMON_SSD1673FB_0_DC_GPIOS_PIN, 0); gpio_pin_write(driver->dc, DT_INST_0_SOLOMON_SSD1673FB_DC_GPIOS_PIN, 0);
tmp = SSD1673_CMD_WRITE_RAM; tmp = SSD1673_CMD_WRITE_RAM;
sbuf.buf = &tmp; sbuf.buf = &tmp;
@ -456,7 +456,7 @@ static int ssd1673_clear_and_write_buffer(struct device *dev)
return err; return err;
} }
gpio_pin_write(driver->dc, DT_SOLOMON_SSD1673FB_0_DC_GPIOS_PIN, 1); gpio_pin_write(driver->dc, DT_INST_0_SOLOMON_SSD1673FB_DC_GPIOS_PIN, 1);
memset(clear_page, 0xff, sizeof(clear_page)); memset(clear_page, 0xff, sizeof(clear_page));
sbuf.buf = clear_page; sbuf.buf = clear_page;
@ -480,9 +480,9 @@ static int ssd1673_controller_init(struct device *dev)
LOG_DBG(""); LOG_DBG("");
gpio_pin_write(driver->reset, DT_SOLOMON_SSD1673FB_0_RESET_GPIOS_PIN, 0); gpio_pin_write(driver->reset, DT_INST_0_SOLOMON_SSD1673FB_RESET_GPIOS_PIN, 0);
k_sleep(SSD1673_RESET_DELAY); k_sleep(SSD1673_RESET_DELAY);
gpio_pin_write(driver->reset, DT_SOLOMON_SSD1673FB_0_RESET_GPIOS_PIN, 1); gpio_pin_write(driver->reset, DT_INST_0_SOLOMON_SSD1673FB_RESET_GPIOS_PIN, 1);
k_sleep(SSD1673_RESET_DELAY); k_sleep(SSD1673_RESET_DELAY);
ssd1673_busy_wait(driver); ssd1673_busy_wait(driver);
@ -499,19 +499,19 @@ static int ssd1673_controller_init(struct device *dev)
return err; return err;
} }
#if defined(DT_SOLOMON_SSD1673FB_0_SOFTSTART_1) #if defined(DT_INST_0_SOLOMON_SSD1673FB_SOFTSTART_1)
tmp[0] = DT_SOLOMON_SSD1673FB_0_SOFTSTART_1; tmp[0] = DT_INST_0_SOLOMON_SSD1673FB_SOFTSTART_1;
tmp[1] = DT_SOLOMON_SSD1673FB_0_SOFTSTART_2; tmp[1] = DT_INST_0_SOLOMON_SSD1673FB_SOFTSTART_2;
tmp[2] = DT_SOLOMON_SSD1673FB_0_SOFTSTART_3; tmp[2] = DT_INST_0_SOLOMON_SSD1673FB_SOFTSTART_3;
err = ssd1673_write_cmd(driver, SSD1673_CMD_SOFTSTART, tmp, 3); err = ssd1673_write_cmd(driver, SSD1673_CMD_SOFTSTART, tmp, 3);
if (err < 0) { if (err < 0) {
return err; return err;
} }
#endif #endif
tmp[0] = DT_SOLOMON_SSD1673FB_0_GDV_A; tmp[0] = DT_INST_0_SOLOMON_SSD1673FB_GDV_A;
#if defined(DT_SOLOMON_SSD1673FB_0_GDV_B) #if defined(DT_INST_0_SOLOMON_SSD1673FB_GDV_B)
tmp[1] = DT_SOLOMON_SSD1673FB_0_GDV_B; tmp[1] = DT_INST_0_SOLOMON_SSD1673FB_GDV_B;
err = ssd1673_write_cmd(driver, SSD1673_CMD_GDV_CTRL, tmp, 2); err = ssd1673_write_cmd(driver, SSD1673_CMD_GDV_CTRL, tmp, 2);
#else #else
err = ssd1673_write_cmd(driver, SSD1673_CMD_GDV_CTRL, tmp, 1); err = ssd1673_write_cmd(driver, SSD1673_CMD_GDV_CTRL, tmp, 1);
@ -520,13 +520,13 @@ static int ssd1673_controller_init(struct device *dev)
return err; return err;
} }
tmp[0] = DT_SOLOMON_SSD1673FB_0_SDV; tmp[0] = DT_INST_0_SOLOMON_SSD1673FB_SDV;
err = ssd1673_write_cmd(driver, SSD1673_CMD_SDV_CTRL, tmp, 1); err = ssd1673_write_cmd(driver, SSD1673_CMD_SDV_CTRL, tmp, 1);
if (err < 0) { if (err < 0) {
return err; return err;
} }
tmp[0] = DT_SOLOMON_SSD1673FB_0_VCOM; tmp[0] = DT_INST_0_SOLOMON_SSD1673FB_VCOM;
err = ssd1673_write_cmd(driver, SSD1673_CMD_VCOM_VOLTAGE, tmp, 1); err = ssd1673_write_cmd(driver, SSD1673_CMD_VCOM_VOLTAGE, tmp, 1);
if (err < 0) { if (err < 0) {
return err; return err;
@ -544,7 +544,7 @@ static int ssd1673_controller_init(struct device *dev)
return err; return err;
} }
tmp[0] = DT_SOLOMON_SSD1673FB_0_BORDER_WAVEFORM; tmp[0] = DT_INST_0_SOLOMON_SSD1673FB_BORDER_WAVEFORM;
err = ssd1673_write_cmd(driver, SSD1673_CMD_BWF_CTRL, tmp, 1); err = ssd1673_write_cmd(driver, SSD1673_CMD_BWF_CTRL, tmp, 1);
if (err < 0) { if (err < 0) {
return err; return err;
@ -582,53 +582,53 @@ static int ssd1673_init(struct device *dev)
LOG_DBG(""); LOG_DBG("");
driver->spi_dev = device_get_binding(DT_SOLOMON_SSD1673FB_0_BUS_NAME); driver->spi_dev = device_get_binding(DT_INST_0_SOLOMON_SSD1673FB_BUS_NAME);
if (driver->spi_dev == NULL) { if (driver->spi_dev == NULL) {
LOG_ERR("Could not get SPI device for SSD1673"); LOG_ERR("Could not get SPI device for SSD1673");
return -EIO; return -EIO;
} }
driver->spi_config.frequency = DT_SOLOMON_SSD1673FB_0_SPI_MAX_FREQUENCY; driver->spi_config.frequency = DT_INST_0_SOLOMON_SSD1673FB_SPI_MAX_FREQUENCY;
driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8);
driver->spi_config.slave = DT_SOLOMON_SSD1673FB_0_BASE_ADDRESS; driver->spi_config.slave = DT_INST_0_SOLOMON_SSD1673FB_BASE_ADDRESS;
driver->spi_config.cs = NULL; driver->spi_config.cs = NULL;
driver->reset = device_get_binding(DT_SOLOMON_SSD1673FB_0_RESET_GPIOS_CONTROLLER); driver->reset = device_get_binding(DT_INST_0_SOLOMON_SSD1673FB_RESET_GPIOS_CONTROLLER);
if (driver->reset == NULL) { if (driver->reset == NULL) {
LOG_ERR("Could not get GPIO port for SSD1673 reset"); LOG_ERR("Could not get GPIO port for SSD1673 reset");
return -EIO; return -EIO;
} }
gpio_pin_configure(driver->reset, DT_SOLOMON_SSD1673FB_0_RESET_GPIOS_PIN, gpio_pin_configure(driver->reset, DT_INST_0_SOLOMON_SSD1673FB_RESET_GPIOS_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
driver->dc = device_get_binding(DT_SOLOMON_SSD1673FB_0_DC_GPIOS_CONTROLLER); driver->dc = device_get_binding(DT_INST_0_SOLOMON_SSD1673FB_DC_GPIOS_CONTROLLER);
if (driver->dc == NULL) { if (driver->dc == NULL) {
LOG_ERR("Could not get GPIO port for SSD1673 DC signal"); LOG_ERR("Could not get GPIO port for SSD1673 DC signal");
return -EIO; return -EIO;
} }
gpio_pin_configure(driver->dc, DT_SOLOMON_SSD1673FB_0_DC_GPIOS_PIN, gpio_pin_configure(driver->dc, DT_INST_0_SOLOMON_SSD1673FB_DC_GPIOS_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
driver->busy = device_get_binding(DT_SOLOMON_SSD1673FB_0_BUSY_GPIOS_CONTROLLER); driver->busy = device_get_binding(DT_INST_0_SOLOMON_SSD1673FB_BUSY_GPIOS_CONTROLLER);
if (driver->busy == NULL) { if (driver->busy == NULL) {
LOG_ERR("Could not get GPIO port for SSD1673 busy signal"); LOG_ERR("Could not get GPIO port for SSD1673 busy signal");
return -EIO; return -EIO;
} }
gpio_pin_configure(driver->busy, DT_SOLOMON_SSD1673FB_0_BUSY_GPIOS_PIN, gpio_pin_configure(driver->busy, DT_INST_0_SOLOMON_SSD1673FB_BUSY_GPIOS_PIN,
GPIO_DIR_IN); GPIO_DIR_IN);
#if defined(DT_SOLOMON_SSD1673FB_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_SOLOMON_SSD1673FB_CS_GPIO_CONTROLLER)
driver->cs_ctrl.gpio_dev = device_get_binding( driver->cs_ctrl.gpio_dev = device_get_binding(
DT_SOLOMON_SSD1673FB_0_CS_GPIO_CONTROLLER); DT_INST_0_SOLOMON_SSD1673FB_CS_GPIO_CONTROLLER);
if (!driver->cs_ctrl.gpio_dev) { if (!driver->cs_ctrl.gpio_dev) {
LOG_ERR("Unable to get SPI GPIO CS device"); LOG_ERR("Unable to get SPI GPIO CS device");
return -EIO; return -EIO;
} }
driver->cs_ctrl.gpio_pin = DT_SOLOMON_SSD1673FB_0_CS_GPIO_PIN; driver->cs_ctrl.gpio_pin = DT_INST_0_SOLOMON_SSD1673FB_CS_GPIO_PIN;
driver->cs_ctrl.delay = 0U; driver->cs_ctrl.delay = 0U;
driver->spi_config.cs = &driver->cs_ctrl; driver->spi_config.cs = &driver->cs_ctrl;
#endif #endif
@ -652,7 +652,7 @@ static struct display_driver_api ssd1673_driver_api = {
}; };
DEVICE_AND_API_INIT(ssd1673, DT_SOLOMON_SSD1673FB_0_LABEL, ssd1673_init, DEVICE_AND_API_INIT(ssd1673, DT_INST_0_SOLOMON_SSD1673FB_LABEL, ssd1673_init,
&ssd1673_driver, NULL, &ssd1673_driver, NULL,
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY,
&ssd1673_driver_api); &ssd1673_driver_api);

View file

@ -11,7 +11,7 @@
#include <logging/log.h> #include <logging/log.h>
LOG_MODULE_REGISTER(dma_sam0, CONFIG_DMA_LOG_LEVEL); LOG_MODULE_REGISTER(dma_sam0, CONFIG_DMA_LOG_LEVEL);
#define DMA_REGS ((Dmac *)DT_ATMEL_SAM0_DMAC_0_BASE_ADDRESS) #define DMA_REGS ((Dmac *)DT_INST_0_ATMEL_SAM0_DMAC_BASE_ADDRESS)
typedef void (*dma_callback)(void *callback_arg, u32_t channel, typedef void (*dma_callback)(void *callback_arg, u32_t channel,
int error_code); int error_code);
@ -397,10 +397,10 @@ DEVICE_DECLARE(dma_sam0_0);
#define DMA_SAM0_IRQ_CONNECT(n) \ #define DMA_SAM0_IRQ_CONNECT(n) \
do { \ do { \
IRQ_CONNECT(DT_ATMEL_SAM0_DMAC_0_IRQ_ ## n, \ IRQ_CONNECT(DT_INST_0_ATMEL_SAM0_DMAC_IRQ_ ## n, \
DT_ATMEL_SAM0_DMAC_0_IRQ_ ## n ## _PRIORITY, \ DT_INST_0_ATMEL_SAM0_DMAC_IRQ_ ## n ## _PRIORITY, \
dma_sam0_isr, DEVICE_GET(dma_sam0_0), 0); \ dma_sam0_isr, DEVICE_GET(dma_sam0_0), 0); \
irq_enable(DT_ATMEL_SAM0_DMAC_0_IRQ_ ## n); \ irq_enable(DT_INST_0_ATMEL_SAM0_DMAC_IRQ_ ## n); \
} while (0) } while (0)
static int dma_sam0_init(struct device *dev) static int dma_sam0_init(struct device *dev)
@ -427,7 +427,7 @@ static int dma_sam0_init(struct device *dev)
/* Enable the unit and enable all priorities */ /* Enable the unit and enable all priorities */
DMA_REGS->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0x0F); DMA_REGS->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0x0F);
#ifdef DT_ATMEL_SAM0_DMAC_0_IRQ_0 #ifdef DT_INST_0_ATMEL_SAM0_DMAC_IRQ_0
DMA_SAM0_IRQ_CONNECT(0); DMA_SAM0_IRQ_CONNECT(0);
#endif #endif
#ifdef DT_ATMEL_SAM0_DMAC_0_IRQ_1 #ifdef DT_ATMEL_SAM0_DMAC_0_IRQ_1

View file

@ -146,11 +146,11 @@ static int entropy_cc13xx_cc26xx_init(struct device *dev)
TRNGEnable(); TRNGEnable();
TRNGIntEnable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); TRNGIntEnable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN);
IRQ_CONNECT(DT_TI_CC13XX_CC26XX_TRNG_0_IRQ_0, IRQ_CONNECT(DT_INST_0_TI_CC13XX_CC26XX_TRNG_IRQ_0,
DT_TI_CC13XX_CC26XX_TRNG_0_IRQ_0_PRIORITY, DT_INST_0_TI_CC13XX_CC26XX_TRNG_IRQ_0_PRIORITY,
entropy_cc13xx_cc26xx_isr, entropy_cc13xx_cc26xx_isr,
DEVICE_GET(entropy_cc13xx_cc26xx), 0); DEVICE_GET(entropy_cc13xx_cc26xx), 0);
irq_enable(DT_TI_CC13XX_CC26XX_TRNG_0_IRQ_0); irq_enable(DT_INST_0_TI_CC13XX_CC26XX_TRNG_IRQ_0);
return 0; return 0;
} }
@ -164,7 +164,7 @@ static struct entropy_cc13xx_cc26xx_data entropy_cc13xx_cc26xx_data = {
.sync = Z_SEM_INITIALIZER(entropy_cc13xx_cc26xx_data.sync, 0, 1), .sync = Z_SEM_INITIALIZER(entropy_cc13xx_cc26xx_data.sync, 0, 1),
}; };
DEVICE_AND_API_INIT(entropy_cc13xx_cc26xx, DT_TI_CC13XX_CC26XX_TRNG_0_LABEL, DEVICE_AND_API_INIT(entropy_cc13xx_cc26xx, DT_INST_0_TI_CC13XX_CC26XX_TRNG_LABEL,
entropy_cc13xx_cc26xx_init, &entropy_cc13xx_cc26xx_data, entropy_cc13xx_cc26xx_init, &entropy_cc13xx_cc26xx_data,
NULL, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&entropy_cc13xx_cc26xx_driver_api); &entropy_cc13xx_cc26xx_driver_api);

View file

@ -659,8 +659,8 @@ static struct device DEVICE_NAME_GET(eth_smsc911x_0);
int eth_init(struct device *dev) int eth_init(struct device *dev)
{ {
IRQ_CONNECT(DT_SMSC_LAN9220_0_IRQ_0, IRQ_CONNECT(DT_INST_0_SMSC_LAN9220_IRQ_0,
DT_SMSC_LAN9220_0_IRQ_0_PRIORITY, DT_INST_0_SMSC_LAN9220_IRQ_0_PRIORITY,
eth_smsc911x_isr, DEVICE_GET(eth_smsc911x_0), 0); eth_smsc911x_isr, DEVICE_GET(eth_smsc911x_0), 0);
int ret = smsc_init(); int ret = smsc_init();
@ -670,7 +670,7 @@ int eth_init(struct device *dev)
return -ENODEV; return -ENODEV;
} }
irq_enable(DT_SMSC_LAN9220_0_IRQ_0); irq_enable(DT_INST_0_SMSC_LAN9220_IRQ_0);
return ret; return ret;
} }

View file

@ -176,7 +176,7 @@ __IO uint32_t E2P_DATA;
#define SMSC9220_PHY_CS 31 #define SMSC9220_PHY_CS 31
#ifndef SMSC9220_BASE #ifndef SMSC9220_BASE
#define SMSC9220_BASE DT_SMSC_LAN9220_0_BASE_ADDRESS #define SMSC9220_BASE DT_INST_0_SMSC_LAN9220_BASE_ADDRESS
#endif #endif
#define SMSC9220 ((volatile SMSC9220_TypeDef *)SMSC9220_BASE) #define SMSC9220 ((volatile SMSC9220_TypeDef *)SMSC9220_BASE)

View file

@ -162,8 +162,8 @@ static int erase_flash_block(off_t offset, size_t size)
#if CONFIG_FLASH_PAGE_LAYOUT #if CONFIG_FLASH_PAGE_LAYOUT
static const struct flash_pages_layout flash_gecko_0_pages_layout = { static const struct flash_pages_layout flash_gecko_0_pages_layout = {
.pages_count = (CONFIG_FLASH_SIZE * 1024) / .pages_count = (CONFIG_FLASH_SIZE * 1024) /
DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
.pages_size = DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, .pages_size = DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
}; };
void flash_gecko_page_layout(struct device *dev, void flash_gecko_page_layout(struct device *dev,
@ -199,7 +199,7 @@ static const struct flash_driver_api flash_gecko_driver_api = {
#ifdef CONFIG_FLASH_PAGE_LAYOUT #ifdef CONFIG_FLASH_PAGE_LAYOUT
.page_layout = flash_gecko_page_layout, .page_layout = flash_gecko_page_layout,
#endif #endif
.write_block_size = DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE, .write_block_size = DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE,
}; };
static struct flash_gecko_data flash_gecko_0_data; static struct flash_gecko_data flash_gecko_0_data;

View file

@ -166,10 +166,10 @@ static int flash_sam_write(struct device *dev, off_t offset,
* Check that the offset and length are multiples of the write * Check that the offset and length are multiples of the write
* block size. * block size.
*/ */
if ((offset % DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE) != 0) { if ((offset % DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE) != 0) {
return -EINVAL; return -EINVAL;
} }
if ((len % DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE) != 0) { if ((len % DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE) != 0) {
return -EINVAL; return -EINVAL;
} }
@ -253,17 +253,17 @@ static int flash_sam_erase(struct device *dev, off_t offset, size_t len)
* Check that the offset and length are multiples of the write * Check that the offset and length are multiples of the write
* erase block size. * erase block size.
*/ */
if ((offset % DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE) != 0) { if ((offset % DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE) != 0) {
return -EINVAL; return -EINVAL;
} }
if ((len % DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE) != 0) { if ((len % DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE) != 0) {
return -EINVAL; return -EINVAL;
} }
flash_sam_sem_take(dev); flash_sam_sem_take(dev);
/* Loop through the pages to erase */ /* Loop through the pages to erase */
for (i = offset; i < offset + len; i += DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE) { for (i = offset; i < offset + len; i += DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE) {
rc = flash_sam_erase_block(dev, i); rc = flash_sam_erase_block(dev, i);
if (rc < 0) { if (rc < 0) {
goto done; goto done;
@ -311,8 +311,8 @@ done:
* Here a page refers to the granularity at which the flash can be erased. * Here a page refers to the granularity at which the flash can be erased.
*/ */
static const struct flash_pages_layout flash_sam_pages_layout = { static const struct flash_pages_layout flash_sam_pages_layout = {
.pages_count = (CONFIG_FLASH_SIZE * 1024) / DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, .pages_count = (CONFIG_FLASH_SIZE * 1024) / DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
.pages_size = DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, .pages_size = DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
}; };
void flash_sam_page_layout(struct device *dev, void flash_sam_page_layout(struct device *dev,
@ -341,7 +341,7 @@ static const struct flash_driver_api flash_sam_api = {
#ifdef CONFIG_FLASH_PAGE_LAYOUT #ifdef CONFIG_FLASH_PAGE_LAYOUT
.page_layout = flash_sam_page_layout, .page_layout = flash_sam_page_layout,
#endif #endif
.write_block_size = DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE, .write_block_size = DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE,
}; };
static const struct flash_sam_dev_cfg flash_sam_cfg = { static const struct flash_sam_dev_cfg flash_sam_cfg = {

View file

@ -376,6 +376,6 @@ static const struct flash_driver_api flash_sam0_api = {
static struct flash_sam0_data flash_sam0_data_0; static struct flash_sam0_data flash_sam0_data_0;
DEVICE_AND_API_INIT(flash_sam0, DT_ATMEL_SAM0_NVMCTRL_0_LABEL, DEVICE_AND_API_INIT(flash_sam0, DT_INST_0_ATMEL_SAM0_NVMCTRL_LABEL,
flash_sam0_init, &flash_sam0_data_0, NULL, POST_KERNEL, flash_sam0_init, &flash_sam0_data_0, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_sam0_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_sam0_api);

View file

@ -274,8 +274,8 @@ static const struct flash_driver_api flash_stm32_api = {
#ifdef CONFIG_FLASH_PAGE_LAYOUT #ifdef CONFIG_FLASH_PAGE_LAYOUT
.page_layout = flash_stm32_page_layout, .page_layout = flash_stm32_page_layout,
#endif #endif
#ifdef DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE #ifdef DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE
.write_block_size = DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE, .write_block_size = DT_INST_0_SOC_NV_FLASH_WRITE_BLOCK_SIZE,
#else #else
#error Flash write block size not available #error Flash write block size not available
/* Flash Write block size is extracted from device tree */ /* Flash Write block size is extracted from device tree */

View file

@ -113,8 +113,8 @@ static int flash_mcux_write_protection(struct device *dev, bool enable)
#if defined(CONFIG_FLASH_PAGE_LAYOUT) #if defined(CONFIG_FLASH_PAGE_LAYOUT)
static const struct flash_pages_layout dev_layout = { static const struct flash_pages_layout dev_layout = {
.pages_count = KB(CONFIG_FLASH_SIZE) / DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, .pages_count = KB(CONFIG_FLASH_SIZE) / DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
.pages_size = DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, .pages_size = DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
}; };
static void flash_mcux_pages_layout(struct device *dev, static void flash_mcux_pages_layout(struct device *dev,

View file

@ -116,8 +116,8 @@ static int flash_mcux_write_protection(struct device *dev, bool enable)
#if defined(CONFIG_FLASH_PAGE_LAYOUT) #if defined(CONFIG_FLASH_PAGE_LAYOUT)
static const struct flash_pages_layout dev_layout = { static const struct flash_pages_layout dev_layout = {
.pages_count = KB(CONFIG_FLASH_SIZE) / .pages_count = KB(CONFIG_FLASH_SIZE) /
DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
.pages_size = DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE, .pages_size = DT_INST_0_SOC_NV_FLASH_ERASE_BLOCK_SIZE,
}; };
static void flash_mcux_pages_layout( static void flash_mcux_pages_layout(

View file

@ -401,23 +401,23 @@ static int spi_flash_wb_configure(struct device *dev)
{ {
struct spi_flash_data *data = dev->driver_data; struct spi_flash_data *data = dev->driver_data;
data->spi = device_get_binding(DT_WINBOND_W25Q16_0_BUS_NAME); data->spi = device_get_binding(DT_INST_0_WINBOND_W25Q16_BUS_NAME);
if (!data->spi) { if (!data->spi) {
return -EINVAL; return -EINVAL;
} }
data->spi_cfg.frequency = DT_WINBOND_W25Q16_0_SPI_MAX_FREQUENCY; data->spi_cfg.frequency = DT_INST_0_WINBOND_W25Q16_SPI_MAX_FREQUENCY;
data->spi_cfg.operation = SPI_WORD_SET(8); data->spi_cfg.operation = SPI_WORD_SET(8);
data->spi_cfg.slave = DT_WINBOND_W25Q16_0_BASE_ADDRESS; data->spi_cfg.slave = DT_INST_0_WINBOND_W25Q16_BASE_ADDRESS;
#if defined(CONFIG_SPI_FLASH_W25QXXDV_GPIO_SPI_CS) #if defined(CONFIG_SPI_FLASH_W25QXXDV_GPIO_SPI_CS)
data->cs_ctrl.gpio_dev = device_get_binding( data->cs_ctrl.gpio_dev = device_get_binding(
DT_WINBOND_W25Q16_0_CS_GPIO_CONTROLLER); DT_INST_0_WINBOND_W25Q16_CS_GPIO_CONTROLLER);
if (!data->cs_ctrl.gpio_dev) { if (!data->cs_ctrl.gpio_dev) {
return -ENODEV; return -ENODEV;
} }
data->cs_ctrl.gpio_pin = DT_WINBOND_W25Q16_0_CS_GPIO_PIN; data->cs_ctrl.gpio_pin = DT_INST_0_WINBOND_W25Q16_CS_GPIO_PIN;
data->cs_ctrl.delay = CONFIG_SPI_FLASH_W25QXXDV_GPIO_CS_WAIT_DELAY; data->cs_ctrl.delay = CONFIG_SPI_FLASH_W25QXXDV_GPIO_CS_WAIT_DELAY;
data->spi_cfg.cs = &data->cs_ctrl; data->spi_cfg.cs = &data->cs_ctrl;

View file

@ -27,7 +27,7 @@
#define MASK_64K 0xFFFF #define MASK_64K 0xFFFF
#define SPI_NOR_MAX_ADDR_WIDTH 4 #define SPI_NOR_MAX_ADDR_WIDTH 4
#define SECTORS_COUNT ((DT_JEDEC_SPI_NOR_0_SIZE / 8) \ #define SECTORS_COUNT ((DT_INST_0_JEDEC_SPI_NOR_SIZE / 8) \
/ CONFIG_SPI_NOR_SECTOR_SIZE) / CONFIG_SPI_NOR_SECTOR_SIZE)
#define JEDEC_ID(x) \ #define JEDEC_ID(x) \
@ -47,9 +47,9 @@
struct spi_nor_data { struct spi_nor_data {
struct device *spi; struct device *spi;
struct spi_config spi_cfg; struct spi_config spi_cfg;
#ifdef DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER #ifdef DT_INST_0_JEDEC_SPI_NOR_CS_GPIO_CONTROLLER
struct spi_cs_control cs_ctrl; struct spi_cs_control cs_ctrl;
#endif /* DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER */ #endif /* DT_INST_0_JEDEC_SPI_NOR_CS_GPIO_CONTROLLER */
struct k_sem sem; struct k_sem sem;
}; };
@ -339,27 +339,27 @@ static int spi_nor_configure(struct device *dev)
struct spi_nor_data *data = dev->driver_data; struct spi_nor_data *data = dev->driver_data;
const struct spi_nor_config *params = dev->config->config_info; const struct spi_nor_config *params = dev->config->config_info;
data->spi = device_get_binding(DT_JEDEC_SPI_NOR_0_BUS_NAME); data->spi = device_get_binding(DT_INST_0_JEDEC_SPI_NOR_BUS_NAME);
if (!data->spi) { if (!data->spi) {
return -EINVAL; return -EINVAL;
} }
data->spi_cfg.frequency = DT_JEDEC_SPI_NOR_0_SPI_MAX_FREQUENCY; data->spi_cfg.frequency = DT_INST_0_JEDEC_SPI_NOR_SPI_MAX_FREQUENCY;
data->spi_cfg.operation = SPI_WORD_SET(8); data->spi_cfg.operation = SPI_WORD_SET(8);
data->spi_cfg.slave = DT_JEDEC_SPI_NOR_0_BASE_ADDRESS; data->spi_cfg.slave = DT_INST_0_JEDEC_SPI_NOR_BASE_ADDRESS;
#ifdef DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER #ifdef DT_INST_0_JEDEC_SPI_NOR_CS_GPIO_CONTROLLER
data->cs_ctrl.gpio_dev = data->cs_ctrl.gpio_dev =
device_get_binding(DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER); device_get_binding(DT_INST_0_JEDEC_SPI_NOR_CS_GPIO_CONTROLLER);
if (!data->cs_ctrl.gpio_dev) { if (!data->cs_ctrl.gpio_dev) {
return -ENODEV; return -ENODEV;
} }
data->cs_ctrl.gpio_pin = DT_JEDEC_SPI_NOR_0_CS_GPIO_PIN; data->cs_ctrl.gpio_pin = DT_INST_0_JEDEC_SPI_NOR_CS_GPIO_PIN;
data->cs_ctrl.delay = CONFIG_SPI_NOR_CS_WAIT_DELAY; data->cs_ctrl.delay = CONFIG_SPI_NOR_CS_WAIT_DELAY;
data->spi_cfg.cs = &data->cs_ctrl; data->spi_cfg.cs = &data->cs_ctrl;
#endif /* DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER */ #endif /* DT_INST_0_JEDEC_SPI_NOR_CS_GPIO_CONTROLLER */
/* now the spi bus is configured, we can verify the flash id */ /* now the spi bus is configured, we can verify the flash id */
if (spi_nor_read_id(dev, params) != 0) { if (spi_nor_read_id(dev, params) != 0) {
@ -385,7 +385,7 @@ static int spi_nor_init(struct device *dev)
#if defined(CONFIG_FLASH_PAGE_LAYOUT) #if defined(CONFIG_FLASH_PAGE_LAYOUT)
static const struct flash_pages_layout dev_layout = { static const struct flash_pages_layout dev_layout = {
.pages_count = DT_JEDEC_SPI_NOR_0_SIZE / 8 / DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE, .pages_count = DT_INST_0_JEDEC_SPI_NOR_SIZE / 8 / DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE,
.pages_size = DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE, .pages_size = DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE,
}; };
@ -411,9 +411,9 @@ static const struct flash_driver_api spi_nor_api = {
static const struct spi_nor_config flash_id = { static const struct spi_nor_config flash_id = {
.id = { .id = {
DT_JEDEC_SPI_NOR_0_JEDEC_ID_0, DT_INST_0_JEDEC_SPI_NOR_JEDEC_ID_0,
DT_JEDEC_SPI_NOR_0_JEDEC_ID_1, DT_INST_0_JEDEC_SPI_NOR_JEDEC_ID_1,
DT_JEDEC_SPI_NOR_0_JEDEC_ID_2, DT_INST_0_JEDEC_SPI_NOR_JEDEC_ID_2,
}, },
.page_size = CONFIG_SPI_NOR_PAGE_SIZE, .page_size = CONFIG_SPI_NOR_PAGE_SIZE,
.sector_size = CONFIG_SPI_NOR_SECTOR_SIZE, .sector_size = CONFIG_SPI_NOR_SECTOR_SIZE,
@ -422,7 +422,7 @@ static const struct spi_nor_config flash_id = {
static struct spi_nor_data spi_nor_memory_data; static struct spi_nor_data spi_nor_memory_data;
DEVICE_AND_API_INIT(spi_flash_memory, DT_JEDEC_SPI_NOR_0_LABEL, DEVICE_AND_API_INIT(spi_flash_memory, DT_INST_0_JEDEC_SPI_NOR_LABEL,
&spi_nor_init, &spi_nor_memory_data, &spi_nor_init, &spi_nor_memory_data,
&flash_id, POST_KERNEL, CONFIG_SPI_NOR_INIT_PRIORITY, &flash_id, POST_KERNEL, CONFIG_SPI_NOR_INIT_PRIORITY,
&spi_nor_api); &spi_nor_api);

View file

@ -224,10 +224,10 @@ static int gpio_cc13xx_cc26xx_init(struct device *dev)
} }
/* Enable IRQ */ /* Enable IRQ */
IRQ_CONNECT(DT_TI_CC13XX_CC26XX_GPIO_0_IRQ_0, IRQ_CONNECT(DT_INST_0_TI_CC13XX_CC26XX_GPIO_IRQ_0,
DT_TI_CC13XX_CC26XX_GPIO_0_IRQ_0_PRIORITY, DT_INST_0_TI_CC13XX_CC26XX_GPIO_IRQ_0_PRIORITY,
gpio_cc13xx_cc26xx_isr, DEVICE_GET(gpio_cc13xx_cc26xx), 0); gpio_cc13xx_cc26xx_isr, DEVICE_GET(gpio_cc13xx_cc26xx), 0);
irq_enable(DT_TI_CC13XX_CC26XX_GPIO_0_IRQ_0); irq_enable(DT_INST_0_TI_CC13XX_CC26XX_GPIO_IRQ_0);
/* Disable callbacks */ /* Disable callbacks */
data->pin_callback_enables = 0; data->pin_callback_enables = 0;
@ -251,7 +251,7 @@ static const struct gpio_driver_api gpio_cc13xx_cc26xx_driver_api = {
.get_pending_int = gpio_cc13xx_cc26xx_get_pending_int .get_pending_int = gpio_cc13xx_cc26xx_get_pending_int
}; };
DEVICE_AND_API_INIT(gpio_cc13xx_cc26xx, DT_TI_CC13XX_CC26XX_GPIO_0_LABEL, DEVICE_AND_API_INIT(gpio_cc13xx_cc26xx, DT_INST_0_TI_CC13XX_CC26XX_GPIO_LABEL,
gpio_cc13xx_cc26xx_init, &gpio_cc13xx_cc26xx_data_0, NULL, gpio_cc13xx_cc26xx_init, &gpio_cc13xx_cc26xx_data_0, NULL,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cc13xx_cc26xx_driver_api); &gpio_cc13xx_cc26xx_driver_api);

View file

@ -148,15 +148,15 @@ static const struct gpio_driver_api gpio_ht16k33_api = {
#define GPIO_HT16K33_DEVICE(id) \ #define GPIO_HT16K33_DEVICE(id) \
static const struct gpio_ht16k33_cfg gpio_ht16k33_##id##_cfg = {\ static const struct gpio_ht16k33_cfg gpio_ht16k33_##id##_cfg = {\
.parent_dev_name = \ .parent_dev_name = \
DT_HOLTEK_HT16K33_KEYSCAN_##id##_BUS_NAME, \ DT_INST_##id##_HOLTEK_HT16K33_KEYSCAN_BUS_NAME, \
.keyscan_idx = \ .keyscan_idx = \
DT_HOLTEK_HT16K33_KEYSCAN_##id##_BASE_ADDRESS, \ DT_INST_##id##_HOLTEK_HT16K33_KEYSCAN_BASE_ADDRESS, \
}; \ }; \
\ \
static struct gpio_ht16k33_data gpio_ht16k33_##id##_data; \ static struct gpio_ht16k33_data gpio_ht16k33_##id##_data; \
\ \
DEVICE_AND_API_INIT(gpio_ht16k33_##id, \ DEVICE_AND_API_INIT(gpio_ht16k33_##id, \
DT_HOLTEK_HT16K33_KEYSCAN_##id##_LABEL, \ DT_INST_##id##_HOLTEK_HT16K33_KEYSCAN_LABEL, \
&gpio_ht16k33_init, \ &gpio_ht16k33_init, \
&gpio_ht16k33_##id##_data, \ &gpio_ht16k33_##id##_data, \
&gpio_ht16k33_##id##_cfg, POST_KERNEL, \ &gpio_ht16k33_##id##_cfg, POST_KERNEL, \

View file

@ -374,21 +374,21 @@ static int gpio_sifive_init(struct device *dev)
static void gpio_sifive_cfg_0(void); static void gpio_sifive_cfg_0(void);
static const struct gpio_sifive_config gpio_sifive_config0 = { static const struct gpio_sifive_config gpio_sifive_config0 = {
.gpio_base_addr = DT_SIFIVE_GPIO0_0_BASE_ADDRESS, .gpio_base_addr = DT_INST_0_SIFIVE_GPIO0_BASE_ADDRESS,
.gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO0_0_IRQ_0, .gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_INST_0_SIFIVE_GPIO0_IRQ_0,
.gpio_cfg_func = gpio_sifive_cfg_0, .gpio_cfg_func = gpio_sifive_cfg_0,
}; };
static struct gpio_sifive_data gpio_sifive_data0; static struct gpio_sifive_data gpio_sifive_data0;
DEVICE_AND_API_INIT(gpio_sifive_0, DT_SIFIVE_GPIO0_0_LABEL, DEVICE_AND_API_INIT(gpio_sifive_0, DT_INST_0_SIFIVE_GPIO0_LABEL,
gpio_sifive_init, gpio_sifive_init,
&gpio_sifive_data0, &gpio_sifive_config0, &gpio_sifive_data0, &gpio_sifive_config0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_sifive_driver); &gpio_sifive_driver);
#define IRQ_INIT(n) \ #define IRQ_INIT(n) \
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO0_0_IRQ_##n, \ IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_INST_0_SIFIVE_GPIO0_IRQ_##n, \
CONFIG_GPIO_SIFIVE_##n##_PRIORITY, \ CONFIG_GPIO_SIFIVE_##n##_PRIORITY, \
gpio_sifive_irq_handler, \ gpio_sifive_irq_handler, \
DEVICE_GET(gpio_sifive_0), \ DEVICE_GET(gpio_sifive_0), \
@ -396,100 +396,100 @@ IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO0_0_IRQ_##n, \
static void gpio_sifive_cfg_0(void) static void gpio_sifive_cfg_0(void)
{ {
#ifdef DT_SIFIVE_GPIO0_0_IRQ_0 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_0
IRQ_INIT(0); IRQ_INIT(0);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_1 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_1
IRQ_INIT(1); IRQ_INIT(1);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_2 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_2
IRQ_INIT(2); IRQ_INIT(2);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_3 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_3
IRQ_INIT(3); IRQ_INIT(3);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_4 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_4
IRQ_INIT(4); IRQ_INIT(4);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_5 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_5
IRQ_INIT(5); IRQ_INIT(5);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_6 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_6
IRQ_INIT(6); IRQ_INIT(6);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_7 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_7
IRQ_INIT(7); IRQ_INIT(7);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_8 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_8
IRQ_INIT(8); IRQ_INIT(8);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_9 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_9
IRQ_INIT(9); IRQ_INIT(9);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_10 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_10
IRQ_INIT(10); IRQ_INIT(10);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_11 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_11
IRQ_INIT(11); IRQ_INIT(11);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_12 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_12
IRQ_INIT(12); IRQ_INIT(12);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_13 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_13
IRQ_INIT(13); IRQ_INIT(13);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_14 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_14
IRQ_INIT(14); IRQ_INIT(14);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_15 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_15
IRQ_INIT(15); IRQ_INIT(15);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_16 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_16
IRQ_INIT(16); IRQ_INIT(16);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_17 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_17
IRQ_INIT(17); IRQ_INIT(17);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_18 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_18
IRQ_INIT(18); IRQ_INIT(18);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_19 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_19
IRQ_INIT(19); IRQ_INIT(19);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_20 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_20
IRQ_INIT(20); IRQ_INIT(20);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_21 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_21
IRQ_INIT(21); IRQ_INIT(21);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_22 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_22
IRQ_INIT(22); IRQ_INIT(22);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_23 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_23
IRQ_INIT(23); IRQ_INIT(23);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_24 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_24
IRQ_INIT(24); IRQ_INIT(24);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_25 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_25
IRQ_INIT(25); IRQ_INIT(25);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_26 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_26
IRQ_INIT(26); IRQ_INIT(26);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_27 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_27
IRQ_INIT(27); IRQ_INIT(27);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_28 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_28
IRQ_INIT(28); IRQ_INIT(28);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_29 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_29
IRQ_INIT(29); IRQ_INIT(29);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_30 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_30
IRQ_INIT(30); IRQ_INIT(30);
#endif #endif
#ifdef DT_SIFIVE_GPIO0_0_IRQ_31 #ifdef DT_INST_0_SIFIVE_GPIO0_IRQ_31
IRQ_INIT(31); IRQ_INIT(31);
#endif #endif
} }

View file

@ -15,9 +15,9 @@
#include <misc/util.h> #include <misc/util.h>
#ifdef CONFIG_HAS_DTS_I2C #ifdef CONFIG_HAS_DTS_I2C
#define CONFIG_GPIO_SX1509B_DEV_NAME DT_SEMTECH_SX1509B_0_LABEL #define CONFIG_GPIO_SX1509B_DEV_NAME DT_INST_0_SEMTECH_SX1509B_LABEL
#define CONFIG_GPIO_SX1509B_I2C_ADDR DT_SEMTECH_SX1509B_0_BASE_ADDRESS #define CONFIG_GPIO_SX1509B_I2C_ADDR DT_INST_0_SEMTECH_SX1509B_BASE_ADDRESS
#define CONFIG_GPIO_SX1509B_I2C_MASTER_DEV_NAME DT_SEMTECH_SX1509B_0_BUS_NAME #define CONFIG_GPIO_SX1509B_I2C_MASTER_DEV_NAME DT_INST_0_SEMTECH_SX1509B_BUS_NAME
#endif #endif
/** Cache of the output configuration and data of the pins */ /** Cache of the output configuration and data of the pins */

View file

@ -16,10 +16,10 @@ ssize_t z_impl_hwinfo_get_device_id(u8_t *buffer, size_t length)
{ {
struct sam0_uid dev_id; struct sam0_uid dev_id;
dev_id.id[0] = *(const u32_t *) DT_ATMEL_SAM0_ID_0_BASE_ADDRESS_0; dev_id.id[0] = *(const u32_t *) DT_INST_0_ATMEL_SAM0_ID_BASE_ADDRESS_0;
dev_id.id[1] = *(const u32_t *) DT_ATMEL_SAM0_ID_0_BASE_ADDRESS_1; dev_id.id[1] = *(const u32_t *) DT_INST_0_ATMEL_SAM0_ID_BASE_ADDRESS_1;
dev_id.id[2] = *(const u32_t *) DT_ATMEL_SAM0_ID_0_BASE_ADDRESS_2; dev_id.id[2] = *(const u32_t *) DT_INST_0_ATMEL_SAM0_ID_BASE_ADDRESS_2;
dev_id.id[3] = *(const u32_t *) DT_ATMEL_SAM0_ID_0_BASE_ADDRESS_3; dev_id.id[3] = *(const u32_t *) DT_INST_0_ATMEL_SAM0_ID_BASE_ADDRESS_3;
if (length > sizeof(dev_id.id)) { if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id); length = sizeof(dev_id.id);

View file

@ -293,16 +293,16 @@ static int i2c_cc13xx_cc26xx_init(struct device *dev)
continue; continue;
} }
IRQ_CONNECT(DT_TI_CC13XX_CC26XX_I2C_0_IRQ_0, IRQ_CONNECT(DT_INST_0_TI_CC13XX_CC26XX_I2C_IRQ_0,
DT_TI_CC13XX_CC26XX_I2C_0_IRQ_0_PRIORITY, DT_INST_0_TI_CC13XX_CC26XX_I2C_IRQ_0_PRIORITY,
i2c_cc13xx_cc26xx_isr, DEVICE_GET(i2c_cc13xx_cc26xx), 0); i2c_cc13xx_cc26xx_isr, DEVICE_GET(i2c_cc13xx_cc26xx), 0);
irq_enable(DT_TI_CC13XX_CC26XX_I2C_0_IRQ_0); irq_enable(DT_INST_0_TI_CC13XX_CC26XX_I2C_IRQ_0);
/* Configure IOC module to route SDA and SCL signals */ /* Configure IOC module to route SDA and SCL signals */
IOCPinTypeI2c(get_dev_config(dev)->base, get_dev_config(dev)->sda_pin, IOCPinTypeI2c(get_dev_config(dev)->base, get_dev_config(dev)->sda_pin,
get_dev_config(dev)->scl_pin); get_dev_config(dev)->scl_pin);
cfg = i2c_map_dt_bitrate(DT_TI_CC13XX_CC26XX_I2C_0_CLOCK_FREQUENCY); cfg = i2c_map_dt_bitrate(DT_INST_0_TI_CC13XX_CC26XX_I2C_CLOCK_FREQUENCY);
err = i2c_cc13xx_cc26xx_configure(dev, cfg | I2C_MODE_MASTER); err = i2c_cc13xx_cc26xx_configure(dev, cfg | I2C_MODE_MASTER);
if (err) { if (err) {
LOG_ERR("Failed to configure"); LOG_ERR("Failed to configure");
@ -320,9 +320,9 @@ static const struct i2c_driver_api i2c_cc13xx_cc26xx_driver_api = {
}; };
static const struct i2c_cc13xx_cc26xx_config i2c_cc13xx_cc26xx_config = { static const struct i2c_cc13xx_cc26xx_config i2c_cc13xx_cc26xx_config = {
.base = DT_TI_CC13XX_CC26XX_I2C_0_BASE_ADDRESS, .base = DT_INST_0_TI_CC13XX_CC26XX_I2C_BASE_ADDRESS,
.sda_pin = DT_TI_CC13XX_CC26XX_I2C_0_SDA_PIN, .sda_pin = DT_INST_0_TI_CC13XX_CC26XX_I2C_SDA_PIN,
.scl_pin = DT_TI_CC13XX_CC26XX_I2C_0_SCL_PIN .scl_pin = DT_INST_0_TI_CC13XX_CC26XX_I2C_SCL_PIN
}; };
static struct i2c_cc13xx_cc26xx_data i2c_cc13xx_cc26xx_data = { static struct i2c_cc13xx_cc26xx_data i2c_cc13xx_cc26xx_data = {
@ -331,7 +331,7 @@ static struct i2c_cc13xx_cc26xx_data i2c_cc13xx_cc26xx_data = {
.error = I2C_MASTER_ERR_NONE .error = I2C_MASTER_ERR_NONE
}; };
DEVICE_AND_API_INIT(i2c_cc13xx_cc26xx, DT_TI_CC13XX_CC26XX_I2C_0_LABEL, DEVICE_AND_API_INIT(i2c_cc13xx_cc26xx, DT_INST_0_TI_CC13XX_CC26XX_I2C_LABEL,
i2c_cc13xx_cc26xx_init, &i2c_cc13xx_cc26xx_data, i2c_cc13xx_cc26xx_init, &i2c_cc13xx_cc26xx_data,
&i2c_cc13xx_cc26xx_config, POST_KERNEL, &i2c_cc13xx_cc26xx_config, POST_KERNEL,
CONFIG_I2C_INIT_PRIORITY, &i2c_cc13xx_cc26xx_driver_api); CONFIG_I2C_INIT_PRIORITY, &i2c_cc13xx_cc26xx_driver_api);

View file

@ -11,14 +11,14 @@
#include <i2c.h> #include <i2c.h>
#include <stdbool.h> #include <stdbool.h>
#if DT_SNPS_DESIGNWARE_I2C_0_PCIE || \ #if DT_INST_0_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_1_PCIE || \ DT_INST_1_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_2_PCIE || \ DT_INST_2_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_3_PCIE || \ DT_INST_3_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_4_PCIE || \ DT_INST_4_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_5_PCIE || \ DT_INST_5_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_6_PCIE || \ DT_INST_6_SNPS_DESIGNWARE_I2C_PCIE || \
DT_SNPS_DESIGNWARE_I2C_7_PCIE DT_INST_7_SNPS_DESIGNWARE_I2C_PCIE
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE"); BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE");
#define I2C_DW_PCIE_ENABLED #define I2C_DW_PCIE_ENABLED
#include <drivers/pcie/pcie.h> #include <drivers/pcie/pcie.h>

View file

@ -10,34 +10,34 @@ static void i2c_config_@NUM@(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_@NUM@ = { static const struct i2c_dw_rom_config i2c_config_dw_@NUM@ = {
.config_func = i2c_config_@NUM@, .config_func = i2c_config_@NUM@,
.bitrate = DT_SNPS_DESIGNWARE_I2C_@NUM@_CLOCK_FREQUENCY, .bitrate = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_CLOCK_FREQUENCY,
#if DT_SNPS_DESIGNWARE_I2C_@NUM@_PCIE #if DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_PCIE
.pcie = true, .pcie = true,
.pcie_bdf = DT_SNPS_DESIGNWARE_I2C_@NUM@_BASE_ADDRESS, .pcie_bdf = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS,
.pcie_id = DT_SNPS_DESIGNWARE_I2C_@NUM@_SIZE, .pcie_id = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_SIZE,
#endif #endif
}; };
static struct i2c_dw_dev_config i2c_@NUM@_runtime = { static struct i2c_dw_dev_config i2c_@NUM@_runtime = {
.base_address = DT_SNPS_DESIGNWARE_I2C_@NUM@_BASE_ADDRESS .base_address = DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS
}; };
DEVICE_AND_API_INIT(i2c_@NUM@, DT_SNPS_DESIGNWARE_I2C_@NUM@_LABEL, DEVICE_AND_API_INIT(i2c_@NUM@, DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_LABEL,
&i2c_dw_initialize, &i2c_dw_initialize,
&i2c_@NUM@_runtime, &i2c_config_dw_@NUM@, &i2c_@NUM@_runtime, &i2c_config_dw_@NUM@,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&funcs); &funcs);
#ifndef DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_SENSE #ifndef DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE
#define DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_SENSE 0 #define DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE 0
#endif #endif
static void i2c_config_@NUM@(struct device *port) static void i2c_config_@NUM@(struct device *port)
{ {
ARG_UNUSED(port); ARG_UNUSED(port);
#if DT_SNPS_DESIGNWARE_I2C_@NUM@_PCIE #if DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_PCIE
#if DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0 == PCIE_IRQ_DETECT #if DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0 == PCIE_IRQ_DETECT
/* PCI(e) with auto IRQ detection */ /* PCI(e) with auto IRQ detection */
@ -46,39 +46,39 @@ static void i2c_config_@NUM@(struct device *port)
unsigned int irq; unsigned int irq;
irq = pcie_wired_irq(DT_SNPS_DESIGNWARE_I2C_@NUM@_BASE_ADDRESS); irq = pcie_wired_irq(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS);
if (irq == PCIE_CONF_INTR_IRQ_NONE) { if (irq == PCIE_CONF_INTR_IRQ_NONE) {
return; return;
} }
irq_connect_dynamic(irq, irq_connect_dynamic(irq,
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_PRIORITY, DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_PRIORITY,
i2c_dw_isr, DEVICE_GET(i2c_@NUM@), i2c_dw_isr, DEVICE_GET(i2c_@NUM@),
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_SENSE); DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE);
pcie_irq_enable(DT_SNPS_DESIGNWARE_I2C_@NUM@_BASE_ADDRESS, irq); pcie_irq_enable(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS, irq);
#else #else
/* PCI(e) with fixed or MSI IRQ */ /* PCI(e) with fixed or MSI IRQ */
IRQ_CONNECT(DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0, IRQ_CONNECT(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0,
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_PRIORITY, DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_PRIORITY,
i2c_dw_isr, DEVICE_GET(i2c_@NUM@), i2c_dw_isr, DEVICE_GET(i2c_@NUM@),
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_SENSE); DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE);
pcie_irq_enable(DT_SNPS_DESIGNWARE_I2C_@NUM@_BASE_ADDRESS, pcie_irq_enable(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_BASE_ADDRESS,
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0); DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0);
#endif #endif
#else #else
/* not PCI(e) */ /* not PCI(e) */
IRQ_CONNECT(DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0, IRQ_CONNECT(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0,
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_PRIORITY, DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_PRIORITY,
i2c_dw_isr, DEVICE_GET(i2c_@NUM@), i2c_dw_isr, DEVICE_GET(i2c_@NUM@),
DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0_SENSE); DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0_SENSE);
irq_enable(DT_SNPS_DESIGNWARE_I2C_@NUM@_IRQ_0); irq_enable(DT_INST_@NUM@_SNPS_DESIGNWARE_I2C_IRQ_0);
#endif #endif
} }

View file

@ -185,33 +185,33 @@ static const struct i2c_driver_api i2c_gecko_driver_api = {
#ifdef DT_SILABS_GECKO_I2C_0 #ifdef DT_SILABS_GECKO_I2C_0
#define PIN_I2C_0_SDA {DT_SILABS_GECKO_I2C_0_LOCATION_SDA_1, \ #define PIN_I2C_0_SDA {DT_INST_0_SILABS_GECKO_I2C_LOCATION_SDA_1, \
DT_SILABS_GECKO_I2C_0_LOCATION_SDA_2, gpioModeWiredAnd, 1} DT_INST_0_SILABS_GECKO_I2C_LOCATION_SDA_2, gpioModeWiredAnd, 1}
#define PIN_I2C_0_SCL {DT_SILABS_GECKO_I2C_0_LOCATION_SCL_1, \ #define PIN_I2C_0_SCL {DT_INST_0_SILABS_GECKO_I2C_LOCATION_SCL_1, \
DT_SILABS_GECKO_I2C_0_LOCATION_SCL_2, gpioModeWiredAnd, 1} DT_INST_0_SILABS_GECKO_I2C_LOCATION_SCL_2, gpioModeWiredAnd, 1}
static struct i2c_gecko_config i2c_gecko_config_0 = { static struct i2c_gecko_config i2c_gecko_config_0 = {
.base = (I2C_TypeDef *)DT_SILABS_GECKO_I2C_0_BASE_ADDRESS, .base = (I2C_TypeDef *)DT_INST_0_SILABS_GECKO_I2C_BASE_ADDRESS,
.clock = cmuClock_I2C0, .clock = cmuClock_I2C0,
.i2cInit = I2C_INIT_DEFAULT, .i2cInit = I2C_INIT_DEFAULT,
.pin_sda = PIN_I2C_0_SDA, .pin_sda = PIN_I2C_0_SDA,
.pin_scl = PIN_I2C_0_SCL, .pin_scl = PIN_I2C_0_SCL,
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
.loc_sda = DT_SILABS_GECKO_I2C_0_LOCATION_SDA_0, .loc_sda = DT_INST_0_SILABS_GECKO_I2C_LOCATION_SDA_0,
.loc_scl = DT_SILABS_GECKO_I2C_0_LOCATION_SCL_0, .loc_scl = DT_INST_0_SILABS_GECKO_I2C_LOCATION_SCL_0,
#else #else
#if DT_SILABS_GECKO_I2C_0_LOCATION_SDA_0 \ #if DT_INST_0_SILABS_GECKO_I2C_LOCATION_SDA_0 \
!= DT_SILABS_GECKO_I2C_0_LOCATION_SCL_0 != DT_INST_0_SILABS_GECKO_I2C_LOCATION_SCL_0
#error I2C_0 DTS location-* properties must have identical value #error I2C_0 DTS location-* properties must have identical value
#endif #endif
.loc = DT_SILABS_GECKO_I2C_0_LOCATION_SCL_0, .loc = DT_INST_0_SILABS_GECKO_I2C_LOCATION_SCL_0,
#endif #endif
.bitrate = DT_SILABS_GECKO_I2C_0_CLOCK_FREQUENCY, .bitrate = DT_INST_0_SILABS_GECKO_I2C_CLOCK_FREQUENCY,
}; };
static struct i2c_gecko_data i2c_gecko_data_0; static struct i2c_gecko_data i2c_gecko_data_0;
DEVICE_AND_API_INIT(i2c_gecko_0, DT_SILABS_GECKO_I2C_0_LABEL, DEVICE_AND_API_INIT(i2c_gecko_0, DT_INST_0_SILABS_GECKO_I2C_LABEL,
&i2c_gecko_init, &i2c_gecko_data_0, &i2c_gecko_config_0, &i2c_gecko_init, &i2c_gecko_data_0, &i2c_gecko_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_gecko_driver_api); &i2c_gecko_driver_api);
@ -219,33 +219,33 @@ DEVICE_AND_API_INIT(i2c_gecko_0, DT_SILABS_GECKO_I2C_0_LABEL,
#ifdef DT_SILABS_GECKO_I2C_1 #ifdef DT_SILABS_GECKO_I2C_1
#define PIN_I2C_1_SDA {DT_SILABS_GECKO_I2C_1_LOCATION_SDA_1, \ #define PIN_I2C_1_SDA {DT_INST_1_SILABS_GECKO_I2C_LOCATION_SDA_1, \
DT_SILABS_GECKO_I2C_1_LOCATION_SDA_2, gpioModeWiredAnd, 1} DT_INST_1_SILABS_GECKO_I2C_LOCATION_SDA_2, gpioModeWiredAnd, 1}
#define PIN_I2C_1_SCL {DT_SILABS_GECKO_I2C_1_LOCATION_SCL_1, \ #define PIN_I2C_1_SCL {DT_INST_1_SILABS_GECKO_I2C_LOCATION_SCL_1, \
DT_SILABS_GECKO_I2C_1_LOCATION_SCL_2, gpioModeWiredAnd, 1} DT_INST_1_SILABS_GECKO_I2C_LOCATION_SCL_2, gpioModeWiredAnd, 1}
static struct i2c_gecko_config i2c_gecko_config_1 = { static struct i2c_gecko_config i2c_gecko_config_1 = {
.base = (I2C_TypeDef *)DT_SILABS_GECKO_I2C_1_BASE_ADDRESS, .base = (I2C_TypeDef *)DT_INST_1_SILABS_GECKO_I2C_BASE_ADDRESS,
.clock = cmuClock_I2C1, .clock = cmuClock_I2C1,
.i2cInit = I2C_INIT_DEFAULT, .i2cInit = I2C_INIT_DEFAULT,
.pin_sda = PIN_I2C_1_SDA, .pin_sda = PIN_I2C_1_SDA,
.pin_scl = PIN_I2C_1_SCL, .pin_scl = PIN_I2C_1_SCL,
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
.loc_sda = DT_SILABS_GECKO_I2C_1_LOCATION_SDA_0, .loc_sda = DT_INST_1_SILABS_GECKO_I2C_LOCATION_SDA_0,
.loc_scl = DT_SILABS_GECKO_I2C_1_LOCATION_SCL_0, .loc_scl = DT_INST_1_SILABS_GECKO_I2C_LOCATION_SCL_0,
#else #else
#if DT_SILABS_GECKO_I2C_1_LOCATION_SDA_0 \ #if DT_INST_1_SILABS_GECKO_I2C_LOCATION_SDA_0 \
!= DT_SILABS_GECKO_I2C_1_LOCATION_SCL_0 != DT_INST_1_SILABS_GECKO_I2C_LOCATION_SCL_0
#error I2C_1 DTS location-* properties must have identical value #error I2C_1 DTS location-* properties must have identical value
#endif #endif
.loc = DT_SILABS_GECKO_I2C_1_LOCATION_SCL_0, .loc = DT_INST_1_SILABS_GECKO_I2C_LOCATION_SCL_0,
#endif #endif
.bitrate = DT_SILABS_GECKO_I2C_1_CLOCK_FREQUENCY, .bitrate = DT_INST_1_SILABS_GECKO_I2C_CLOCK_FREQUENCY,
}; };
static struct i2c_gecko_data i2c_gecko_data_1; static struct i2c_gecko_data i2c_gecko_data_1;
DEVICE_AND_API_INIT(i2c_gecko_1, DT_SILABS_GECKO_I2C_1_LABEL, DEVICE_AND_API_INIT(i2c_gecko_1, DT_INST_1_SILABS_GECKO_I2C_LABEL,
&i2c_gecko_init, &i2c_gecko_data_1, &i2c_gecko_config_1, &i2c_gecko_init, &i2c_gecko_data_1, &i2c_gecko_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_gecko_driver_api); &i2c_gecko_driver_api);

View file

@ -357,10 +357,10 @@ static const struct i2c_driver_api i2c_xec_driver_api = {
#ifdef CONFIG_I2C_XEC_0 #ifdef CONFIG_I2C_XEC_0
static struct i2c_xec_data i2c_xec_data_0; static struct i2c_xec_data i2c_xec_data_0;
static const struct i2c_xec_config i2c_xec_config_0 = { static const struct i2c_xec_config i2c_xec_config_0 = {
.base_addr = DT_MICROCHIP_XEC_I2C_0_BASE_ADDRESS, .base_addr = DT_INST_0_MICROCHIP_XEC_I2C_BASE_ADDRESS,
.port_sel = DT_MICROCHIP_XEC_I2C_0_PORT_SEL, .port_sel = DT_INST_0_MICROCHIP_XEC_I2C_PORT_SEL,
}; };
DEVICE_AND_API_INIT(i2c_xec_0, DT_MICROCHIP_XEC_I2C_0_LABEL, DEVICE_AND_API_INIT(i2c_xec_0, DT_INST_0_MICROCHIP_XEC_I2C_LABEL,
&i2c_xec_init, &i2c_xec_data_0, &i2c_xec_config_0, &i2c_xec_init, &i2c_xec_data_0, &i2c_xec_config_0,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_xec_driver_api); &i2c_xec_driver_api);
@ -369,10 +369,10 @@ DEVICE_AND_API_INIT(i2c_xec_0, DT_MICROCHIP_XEC_I2C_0_LABEL,
#ifdef CONFIG_I2C_XEC_1 #ifdef CONFIG_I2C_XEC_1
static struct i2c_xec_data i2c_xec_data_1; static struct i2c_xec_data i2c_xec_data_1;
static const struct i2c_xec_config i2c_xec_config_1 = { static const struct i2c_xec_config i2c_xec_config_1 = {
.base_addr = DT_MICROCHIP_XEC_I2C_1_BASE_ADDRESS, .base_addr = DT_INST_1_MICROCHIP_XEC_I2C_BASE_ADDRESS,
.port_sel = DT_MICROCHIP_XEC_I2C_1_PORT_SEL, .port_sel = DT_INST_1_MICROCHIP_XEC_I2C_PORT_SEL,
}; };
DEVICE_AND_API_INIT(i2c_xec_1, DT_MICROCHIP_XEC_I2C_1_LABEL, DEVICE_AND_API_INIT(i2c_xec_1, DT_INST_1_MICROCHIP_XEC_I2C_LABEL,
&i2c_xec_init, &i2c_xec_data_1, &i2c_xec_config_1, &i2c_xec_init, &i2c_xec_data_1, &i2c_xec_config_1,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_xec_driver_api); &i2c_xec_driver_api);
@ -381,10 +381,10 @@ DEVICE_AND_API_INIT(i2c_xec_1, DT_MICROCHIP_XEC_I2C_1_LABEL,
#ifdef CONFIG_I2C_XEC_2 #ifdef CONFIG_I2C_XEC_2
static struct i2c_xec_data i2c_xec_data_2; static struct i2c_xec_data i2c_xec_data_2;
static const struct i2c_xec_config i2c_xec_config_2 = { static const struct i2c_xec_config i2c_xec_config_2 = {
.base_addr = DT_MICROCHIP_XEC_I2C_2_BASE_ADDRESS, .base_addr = DT_INST_2_MICROCHIP_XEC_I2C_BASE_ADDRESS,
.port_sel = DT_MICROCHIP_XEC_I2C_2_PORT_SEL, .port_sel = DT_INST_2_MICROCHIP_XEC_I2C_PORT_SEL,
}; };
DEVICE_AND_API_INIT(i2c_xec_2, DT_MICROCHIP_XEC_I2C_2_LABEL, DEVICE_AND_API_INIT(i2c_xec_2, DT_INST_2_MICROCHIP_XEC_I2C_LABEL,
&i2c_xec_init, &i2c_xec_data_2, &i2c_xec_config_2, &i2c_xec_init, &i2c_xec_data_2, &i2c_xec_config_2,
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
&i2c_xec_driver_api); &i2c_xec_driver_api);

View file

@ -111,10 +111,10 @@ static int i2c_sbcon_init(struct device *dev)
static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \ static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \
\ \
static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \ static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \
.sbcon = (void *)DT_ARM_VERSATILE_I2C_##_num##_BASE_ADDRESS, \ .sbcon = (void *)DT_INST_##_num##_ARM_VERSATILE_I2C_BASE_ADDRESS, \
}; \ }; \
\ \
DEVICE_AND_API_INIT(i2c_sbcon_##_num, DT_ARM_VERSATILE_I2C_##_num##_LABEL, \ DEVICE_AND_API_INIT(i2c_sbcon_##_num, DT_INST_##_num##_ARM_VERSATILE_I2C_LABEL, \
i2c_sbcon_init, \ i2c_sbcon_init, \
&i2c_sbcon_dev_data_##_num, \ &i2c_sbcon_dev_data_##_num, \
&i2c_sbcon_dev_cfg_##_num, \ &i2c_sbcon_dev_cfg_##_num, \

View file

@ -345,7 +345,7 @@ static struct i2c_driver_api i2c_sifive_api = {
CONFIG_I2C_INIT_PRIORITY, \ CONFIG_I2C_INIT_PRIORITY, \
&i2c_sifive_api) &i2c_sifive_api)
#ifdef DT_SIFIVE_I2C0_0_LABEL #ifdef DT_INST_0_SIFIVE_I2C0_LABEL
I2C_SIFIVE_INIT(0); I2C_SIFIVE_INIT(0);
#endif #endif

View file

@ -207,16 +207,16 @@ static int i2c_eeprom_slave_init(struct device *dev)
static struct i2c_eeprom_slave_data i2c_eeprom_slave_0_dev_data; static struct i2c_eeprom_slave_data i2c_eeprom_slave_0_dev_data;
static u8_t i2c_eeprom_slave_0_buffer[(DT_ATMEL_AT24_0_SIZE * 1024)]; static u8_t i2c_eeprom_slave_0_buffer[(DT_INST_0_ATMEL_AT24_SIZE * 1024)];
static const struct i2c_eeprom_slave_config i2c_eeprom_slave_0_cfg = { static const struct i2c_eeprom_slave_config i2c_eeprom_slave_0_cfg = {
.controller_dev_name = DT_ATMEL_AT24_0_BUS_NAME, .controller_dev_name = DT_INST_0_ATMEL_AT24_BUS_NAME,
.address = DT_ATMEL_AT24_0_BASE_ADDRESS, .address = DT_INST_0_ATMEL_AT24_BASE_ADDRESS,
.buffer_size = (DT_ATMEL_AT24_0_SIZE * 1024), .buffer_size = (DT_INST_0_ATMEL_AT24_SIZE * 1024),
.buffer = i2c_eeprom_slave_0_buffer .buffer = i2c_eeprom_slave_0_buffer
}; };
DEVICE_AND_API_INIT(i2c_eeprom_slave_0, DT_ATMEL_AT24_0_LABEL, DEVICE_AND_API_INIT(i2c_eeprom_slave_0, DT_INST_0_ATMEL_AT24_LABEL,
&i2c_eeprom_slave_init, &i2c_eeprom_slave_init,
&i2c_eeprom_slave_0_dev_data, &i2c_eeprom_slave_0_cfg, &i2c_eeprom_slave_0_dev_data, &i2c_eeprom_slave_0_cfg,
POST_KERNEL, CONFIG_I2C_SLAVE_INIT_PRIORITY, POST_KERNEL, CONFIG_I2C_SLAVE_INIT_PRIORITY,
@ -228,16 +228,16 @@ DEVICE_AND_API_INIT(i2c_eeprom_slave_0, DT_ATMEL_AT24_0_LABEL,
static struct i2c_eeprom_slave_data i2c_eeprom_slave_1_dev_data; static struct i2c_eeprom_slave_data i2c_eeprom_slave_1_dev_data;
static u8_t i2c_eeprom_slave_1_buffer[(DT_ATMEL_AT24_1_SIZE * 1024)]; static u8_t i2c_eeprom_slave_1_buffer[(DT_INST_1_ATMEL_AT24_SIZE * 1024)];
static const struct i2c_eeprom_slave_config i2c_eeprom_slave_1_cfg = { static const struct i2c_eeprom_slave_config i2c_eeprom_slave_1_cfg = {
.controller_dev_name = DT_ATMEL_AT24_1_BUS_NAME, .controller_dev_name = DT_INST_1_ATMEL_AT24_BUS_NAME,
.address = DT_ATMEL_AT24_1_BASE_ADDRESS, .address = DT_INST_1_ATMEL_AT24_BASE_ADDRESS,
.buffer_size = (DT_ATMEL_AT24_1_SIZE * 1024), .buffer_size = (DT_INST_1_ATMEL_AT24_SIZE * 1024),
.buffer = i2c_eeprom_slave_1_buffer .buffer = i2c_eeprom_slave_1_buffer
}; };
DEVICE_AND_API_INIT(i2c_eeprom_slave_1, DT_ATMEL_AT24_1_LABEL, DEVICE_AND_API_INIT(i2c_eeprom_slave_1, DT_INST_1_ATMEL_AT24_LABEL,
&i2c_eeprom_slave_init, &i2c_eeprom_slave_init,
&i2c_eeprom_slave_1_dev_data, &i2c_eeprom_slave_1_cfg, &i2c_eeprom_slave_1_dev_data, &i2c_eeprom_slave_1_cfg,
POST_KERNEL, CONFIG_I2C_SLAVE_INIT_PRIORITY, POST_KERNEL, CONFIG_I2C_SLAVE_INIT_PRIORITY,

View file

@ -977,7 +977,7 @@ static inline int configure_spi(struct device *dev)
{ {
struct cc2520_context *cc2520 = dev->driver_data; struct cc2520_context *cc2520 = dev->driver_data;
cc2520->spi = device_get_binding(DT_TI_CC2520_0_BUS_NAME); cc2520->spi = device_get_binding(DT_INST_0_TI_CC2520_BUS_NAME);
if (!cc2520->spi) { if (!cc2520->spi) {
LOG_ERR("Unable to get SPI device"); LOG_ERR("Unable to get SPI device");
return -ENODEV; return -ENODEV;
@ -985,25 +985,25 @@ static inline int configure_spi(struct device *dev)
#if defined(CONFIG_IEEE802154_CC2520_GPIO_SPI_CS) #if defined(CONFIG_IEEE802154_CC2520_GPIO_SPI_CS)
cs_ctrl.gpio_dev = device_get_binding( cs_ctrl.gpio_dev = device_get_binding(
DT_TI_CC2520_0_CS_GPIO_CONTROLLER); DT_INST_0_TI_CC2520_CS_GPIO_CONTROLLER);
if (!cs_ctrl.gpio_dev) { if (!cs_ctrl.gpio_dev) {
LOG_ERR("Unable to get GPIO SPI CS device"); LOG_ERR("Unable to get GPIO SPI CS device");
return -ENODEV; return -ENODEV;
} }
cs_ctrl.gpio_pin = DT_TI_CC2520_0_CS_GPIO_PIN; cs_ctrl.gpio_pin = DT_INST_0_TI_CC2520_CS_GPIO_PIN;
cs_ctrl.delay = 0U; cs_ctrl.delay = 0U;
cc2520->spi_cfg.cs = &cs_ctrl; cc2520->spi_cfg.cs = &cs_ctrl;
LOG_DBG("SPI GPIO CS configured on %s:%u", LOG_DBG("SPI GPIO CS configured on %s:%u",
DT_TI_CC2520_0_CS_GPIO_CONTROLLER, DT_INST_0_TI_CC2520_CS_GPIO_CONTROLLER,
DT_TI_CC2520_0_CS_GPIO_PIN); DT_INST_0_TI_CC2520_CS_GPIO_PIN);
#endif /* CONFIG_IEEE802154_CC2520_GPIO_SPI_CS */ #endif /* CONFIG_IEEE802154_CC2520_GPIO_SPI_CS */
cc2520->spi_cfg.frequency = DT_TI_CC2520_0_SPI_MAX_FREQUENCY; cc2520->spi_cfg.frequency = DT_INST_0_TI_CC2520_SPI_MAX_FREQUENCY;
cc2520->spi_cfg.operation = SPI_WORD_SET(8); cc2520->spi_cfg.operation = SPI_WORD_SET(8);
cc2520->spi_cfg.slave = DT_TI_CC2520_0_BASE_ADDRESS; cc2520->spi_cfg.slave = DT_INST_0_TI_CC2520_BASE_ADDRESS;
return 0; return 0;
} }

View file

@ -797,7 +797,7 @@ static inline void set_reset(struct device *dev, u32_t value)
struct mcr20a_context *mcr20a = dev->driver_data; struct mcr20a_context *mcr20a = dev->driver_data;
gpio_pin_write(mcr20a->reset_gpio, gpio_pin_write(mcr20a->reset_gpio,
DT_NXP_MCR20A_0_RESET_GPIOS_PIN, value); DT_INST_0_NXP_MCR20A_RESET_GPIOS_PIN, value);
} }
static void enable_irqb_interrupt(struct mcr20a_context *mcr20a, static void enable_irqb_interrupt(struct mcr20a_context *mcr20a,
@ -805,10 +805,10 @@ static void enable_irqb_interrupt(struct mcr20a_context *mcr20a,
{ {
if (enable) { if (enable) {
gpio_pin_enable_callback(mcr20a->irq_gpio, gpio_pin_enable_callback(mcr20a->irq_gpio,
DT_NXP_MCR20A_0_IRQB_GPIOS_PIN); DT_INST_0_NXP_MCR20A_IRQB_GPIOS_PIN);
} else { } else {
gpio_pin_disable_callback(mcr20a->irq_gpio, gpio_pin_disable_callback(mcr20a->irq_gpio,
DT_NXP_MCR20A_0_IRQB_GPIOS_PIN); DT_INST_0_NXP_MCR20A_IRQB_GPIOS_PIN);
} }
} }
@ -816,7 +816,7 @@ static inline void setup_gpio_callbacks(struct mcr20a_context *mcr20a)
{ {
gpio_init_callback(&mcr20a->irqb_cb, gpio_init_callback(&mcr20a->irqb_cb,
irqb_int_handler, irqb_int_handler,
BIT(DT_NXP_MCR20A_0_IRQB_GPIOS_PIN)); BIT(DT_INST_0_NXP_MCR20A_IRQB_GPIOS_PIN));
gpio_add_callback(mcr20a->irq_gpio, &mcr20a->irqb_cb); gpio_add_callback(mcr20a->irq_gpio, &mcr20a->irqb_cb);
} }
@ -1281,7 +1281,7 @@ static int power_on_and_setup(struct device *dev)
z_usleep(50); z_usleep(50);
timeout--; timeout--;
gpio_pin_read(mcr20a->irq_gpio, gpio_pin_read(mcr20a->irq_gpio,
DT_NXP_MCR20A_0_IRQB_GPIOS_PIN, &status); DT_INST_0_NXP_MCR20A_IRQB_GPIOS_PIN, &status);
} while (status && timeout); } while (status && timeout);
if (status) { if (status) {
@ -1335,15 +1335,15 @@ static inline int configure_gpios(struct device *dev)
/* setup gpio for the modem interrupt */ /* setup gpio for the modem interrupt */
mcr20a->irq_gpio = mcr20a->irq_gpio =
device_get_binding(DT_NXP_MCR20A_0_IRQB_GPIOS_CONTROLLER); device_get_binding(DT_INST_0_NXP_MCR20A_IRQB_GPIOS_CONTROLLER);
if (mcr20a->irq_gpio == NULL) { if (mcr20a->irq_gpio == NULL) {
LOG_ERR("Failed to get pointer to %s device", LOG_ERR("Failed to get pointer to %s device",
DT_NXP_MCR20A_0_IRQB_GPIOS_CONTROLLER); DT_INST_0_NXP_MCR20A_IRQB_GPIOS_CONTROLLER);
return -EINVAL; return -EINVAL;
} }
gpio_pin_configure(mcr20a->irq_gpio, gpio_pin_configure(mcr20a->irq_gpio,
DT_NXP_MCR20A_0_IRQB_GPIOS_PIN, DT_INST_0_NXP_MCR20A_IRQB_GPIOS_PIN,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_PUD_PULL_UP | GPIO_PUD_PULL_UP |
GPIO_INT_ACTIVE_LOW); GPIO_INT_ACTIVE_LOW);
@ -1352,15 +1352,15 @@ static inline int configure_gpios(struct device *dev)
/* setup gpio for the modems reset */ /* setup gpio for the modems reset */
mcr20a->reset_gpio = mcr20a->reset_gpio =
device_get_binding( device_get_binding(
DT_NXP_MCR20A_0_RESET_GPIOS_CONTROLLER); DT_INST_0_NXP_MCR20A_RESET_GPIOS_CONTROLLER);
if (mcr20a->reset_gpio == NULL) { if (mcr20a->reset_gpio == NULL) {
LOG_ERR("Failed to get pointer to %s device", LOG_ERR("Failed to get pointer to %s device",
DT_NXP_MCR20A_0_RESET_GPIOS_CONTROLLER); DT_INST_0_NXP_MCR20A_RESET_GPIOS_CONTROLLER);
return -EINVAL; return -EINVAL;
} }
gpio_pin_configure(mcr20a->reset_gpio, gpio_pin_configure(mcr20a->reset_gpio,
DT_NXP_MCR20A_0_RESET_GPIOS_PIN, DT_INST_0_NXP_MCR20A_RESET_GPIOS_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
set_reset(dev, 0); set_reset(dev, 0);
} }
@ -1372,7 +1372,7 @@ static inline int configure_spi(struct device *dev)
{ {
struct mcr20a_context *mcr20a = dev->driver_data; struct mcr20a_context *mcr20a = dev->driver_data;
mcr20a->spi = device_get_binding(DT_NXP_MCR20A_0_BUS_NAME); mcr20a->spi = device_get_binding(DT_INST_0_NXP_MCR20A_BUS_NAME);
if (!mcr20a->spi) { if (!mcr20a->spi) {
LOG_ERR("Unable to get SPI device"); LOG_ERR("Unable to get SPI device");
return -ENODEV; return -ENODEV;
@ -1396,13 +1396,13 @@ static inline int configure_spi(struct device *dev)
DT_NXP_MCR20A_0_CS_GPIO_PIN); DT_NXP_MCR20A_0_CS_GPIO_PIN);
#endif /* DT_NXP_MCR20A_0_CS_GPIO_CONTROLLER */ #endif /* DT_NXP_MCR20A_0_CS_GPIO_CONTROLLER */
mcr20a->spi_cfg.frequency = DT_NXP_MCR20A_0_SPI_MAX_FREQUENCY; mcr20a->spi_cfg.frequency = DT_INST_0_NXP_MCR20A_SPI_MAX_FREQUENCY;
mcr20a->spi_cfg.operation = SPI_WORD_SET(8); mcr20a->spi_cfg.operation = SPI_WORD_SET(8);
mcr20a->spi_cfg.slave = DT_NXP_MCR20A_0_BASE_ADDRESS; mcr20a->spi_cfg.slave = DT_INST_0_NXP_MCR20A_BASE_ADDRESS;
LOG_DBG("SPI configured %s, %d", LOG_DBG("SPI configured %s, %d",
DT_NXP_MCR20A_0_BUS_NAME, DT_INST_0_NXP_MCR20A_BUS_NAME,
DT_NXP_MCR20A_0_BASE_ADDRESS); DT_INST_0_NXP_MCR20A_BASE_ADDRESS);
return 0; return 0;
} }

View file

@ -42,7 +42,7 @@ void riscv_plic_irq_enable(u32_t irq)
u32_t key; u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
key = irq_lock(); key = irq_lock();
en += (plic_irq >> 5); en += (plic_irq >> 5);
@ -68,7 +68,7 @@ void riscv_plic_irq_disable(u32_t irq)
u32_t key; u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
key = irq_lock(); key = irq_lock();
en += (plic_irq >> 5); en += (plic_irq >> 5);
@ -88,7 +88,7 @@ void riscv_plic_irq_disable(u32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq) int riscv_plic_irq_is_enabled(u32_t irq)
{ {
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
en += (plic_irq >> 5); en += (plic_irq >> 5);
@ -109,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
void riscv_plic_set_priority(u32_t irq, u32_t priority) void riscv_plic_set_priority(u32_t irq, u32_t priority)
{ {
volatile u32_t *prio = volatile u32_t *prio =
(volatile u32_t *)DT_RISCV_PLIC0_0_PRIO_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS;
/* Can set priority only for PLIC-specific interrupt line */ /* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ) if (irq <= RISCV_MAX_GENERIC_IRQ)
return; return;
if (priority > DT_RISCV_PLIC0_0_RISCV_MAX_PRIORITY) if (priority > DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY)
priority = DT_RISCV_PLIC0_0_RISCV_MAX_PRIORITY; priority = DT_INST_0_RISCV_PLIC0_RISCV_MAX_PRIORITY;
prio += (irq - RISCV_MAX_GENERIC_IRQ); prio += (irq - RISCV_MAX_GENERIC_IRQ);
*prio = priority; *prio = priority;
@ -140,7 +140,7 @@ int riscv_plic_get_irq(void)
static void plic_irq_handler(void *arg) static void plic_irq_handler(void *arg)
{ {
volatile struct plic_regs_t *regs = volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *) DT_RISCV_PLIC0_0_REG_BASE_ADDRESS; (volatile struct plic_regs_t *) DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS;
u32_t irq; u32_t irq;
struct _isr_table_entry *ite; struct _isr_table_entry *ite;
@ -186,11 +186,11 @@ static int plic_init(struct device *dev)
ARG_UNUSED(dev); ARG_UNUSED(dev);
volatile u32_t *en = volatile u32_t *en =
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_RISCV_PLIC0_IRQ_EN_BASE_ADDRESS;
volatile u32_t *prio = volatile u32_t *prio =
(volatile u32_t *)DT_RISCV_PLIC0_0_PRIO_BASE_ADDRESS; (volatile u32_t *)DT_INST_0_RISCV_PLIC0_PRIO_BASE_ADDRESS;
volatile struct plic_regs_t *regs = volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_RISCV_PLIC0_0_REG_BASE_ADDRESS; (volatile struct plic_regs_t *)DT_INST_0_RISCV_PLIC0_REG_BASE_ADDRESS;
int i; int i;
/* Ensure that all interrupts are disabled initially */ /* Ensure that all interrupts are disabled initially */

View file

@ -316,10 +316,10 @@ u32_t sam0_eic_interrupt_pending(int port)
#define SAM0_EIC_IRQ_CONNECT(n) \ #define SAM0_EIC_IRQ_CONNECT(n) \
do { \ do { \
IRQ_CONNECT(DT_ATMEL_SAM0_EIC_0_IRQ_ ## n, \ IRQ_CONNECT(DT_INST_0_ATMEL_SAM0_EIC_IRQ_ ## n, \
DT_ATMEL_SAM0_EIC_0_IRQ_ ## n ## _PRIORITY, \ DT_INST_0_ATMEL_SAM0_EIC_IRQ_ ## n ## _PRIORITY, \
sam0_eic_isr, DEVICE_GET(sam0_eic), 0); \ sam0_eic_isr, DEVICE_GET(sam0_eic), 0); \
irq_enable(DT_ATMEL_SAM0_EIC_0_IRQ_ ## n); \ irq_enable(DT_INST_0_ATMEL_SAM0_EIC_IRQ_ ## n); \
} while (0) } while (0)
static int sam0_eic_init(struct device *dev) static int sam0_eic_init(struct device *dev)
@ -333,7 +333,7 @@ static int sam0_eic_init(struct device *dev)
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 | GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN; GCLK_CLKCTRL_CLKEN;
#ifdef DT_ATMEL_SAM0_EIC_0_IRQ_0 #ifdef DT_INST_0_ATMEL_SAM0_EIC_IRQ_0
SAM0_EIC_IRQ_CONNECT(0); SAM0_EIC_IRQ_CONNECT(0);
#endif #endif
#ifdef DT_ATMEL_SAM0_EIC_0_IRQ_1 #ifdef DT_ATMEL_SAM0_EIC_0_IRQ_1
@ -389,6 +389,6 @@ static int sam0_eic_init(struct device *dev)
} }
static struct sam0_eic_data eic_data; static struct sam0_eic_data eic_data;
DEVICE_INIT(sam0_eic, DT_ATMEL_SAM0_EIC_0_LABEL, sam0_eic_init, DEVICE_INIT(sam0_eic, DT_INST_0_ATMEL_SAM0_EIC_LABEL, sam0_eic_init,
&eic_data, NULL, &eic_data, NULL,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

View file

@ -12,8 +12,8 @@
#include <zephyr.h> #include <zephyr.h>
#include <zephyr/types.h> #include <zephyr/types.h>
#define IRQ_MASK DT_VEXRISCV_INTC0_0_IRQ_MASK_BASE_ADDRESS #define IRQ_MASK DT_INST_0_VEXRISCV_INTC0_IRQ_MASK_BASE_ADDRESS
#define IRQ_PENDING DT_VEXRISCV_INTC0_0_IRQ_PENDING_BASE_ADDRESS #define IRQ_PENDING DT_INST_0_VEXRISCV_INTC0_IRQ_PENDING_BASE_ADDRESS
#define TIMER0_IRQ DT_LITEX_TIMER0_E0002800_IRQ_0 #define TIMER0_IRQ DT_LITEX_TIMER0_E0002800_IRQ_0
#define UART0_IRQ DT_LITEX_UART0_E0001800_IRQ_0 #define UART0_IRQ DT_LITEX_UART0_E0001800_IRQ_0

View file

@ -175,7 +175,7 @@ static const struct ipm_driver_api ipm_mhu_driver_api = {
static void ipm_mhu_irq_config_func_0(struct device *d); static void ipm_mhu_irq_config_func_0(struct device *d);
static const struct ipm_mhu_device_config ipm_mhu_cfg_0 = { static const struct ipm_mhu_device_config ipm_mhu_cfg_0 = {
.base = (u8_t *)DT_ARM_MHU_0_BASE_ADDRESS, .base = (u8_t *)DT_INST_0_ARM_MHU_BASE_ADDRESS,
.irq_config_func = ipm_mhu_irq_config_func_0, .irq_config_func = ipm_mhu_irq_config_func_0,
}; };
@ -185,7 +185,7 @@ static struct ipm_mhu_data ipm_mhu_data_0 = {
}; };
DEVICE_AND_API_INIT(mhu_0, DEVICE_AND_API_INIT(mhu_0,
DT_ARM_MHU_0_LABEL, DT_INST_0_ARM_MHU_LABEL,
&ipm_mhu_init, &ipm_mhu_init,
&ipm_mhu_data_0, &ipm_mhu_data_0,
&ipm_mhu_cfg_0, PRE_KERNEL_1, &ipm_mhu_cfg_0, PRE_KERNEL_1,
@ -195,18 +195,18 @@ DEVICE_AND_API_INIT(mhu_0,
static void ipm_mhu_irq_config_func_0(struct device *d) static void ipm_mhu_irq_config_func_0(struct device *d)
{ {
ARG_UNUSED(d); ARG_UNUSED(d);
IRQ_CONNECT(DT_ARM_MHU_0_IRQ_0, IRQ_CONNECT(DT_INST_0_ARM_MHU_IRQ_0,
DT_ARM_MHU_0_IRQ_0, DT_INST_0_ARM_MHU_IRQ_0,
ipm_mhu_isr, ipm_mhu_isr,
DEVICE_GET(mhu_0), DEVICE_GET(mhu_0),
0); 0);
irq_enable(DT_ARM_MHU_0_IRQ_0); irq_enable(DT_INST_0_ARM_MHU_IRQ_0);
} }
static void ipm_mhu_irq_config_func_1(struct device *d); static void ipm_mhu_irq_config_func_1(struct device *d);
static const struct ipm_mhu_device_config ipm_mhu_cfg_1 = { static const struct ipm_mhu_device_config ipm_mhu_cfg_1 = {
.base = (u8_t *)DT_ARM_MHU_1_BASE_ADDRESS, .base = (u8_t *)DT_INST_1_ARM_MHU_BASE_ADDRESS,
.irq_config_func = ipm_mhu_irq_config_func_1, .irq_config_func = ipm_mhu_irq_config_func_1,
}; };
@ -216,7 +216,7 @@ static struct ipm_mhu_data ipm_mhu_data_1 = {
}; };
DEVICE_AND_API_INIT(mhu_1, DEVICE_AND_API_INIT(mhu_1,
DT_ARM_MHU_1_LABEL, DT_INST_1_ARM_MHU_LABEL,
&ipm_mhu_init, &ipm_mhu_init,
&ipm_mhu_data_1, &ipm_mhu_data_1,
&ipm_mhu_cfg_1, PRE_KERNEL_1, &ipm_mhu_cfg_1, PRE_KERNEL_1,
@ -226,10 +226,10 @@ DEVICE_AND_API_INIT(mhu_1,
static void ipm_mhu_irq_config_func_1(struct device *d) static void ipm_mhu_irq_config_func_1(struct device *d)
{ {
ARG_UNUSED(d); ARG_UNUSED(d);
IRQ_CONNECT(DT_ARM_MHU_1_IRQ_0, IRQ_CONNECT(DT_INST_1_ARM_MHU_IRQ_0,
DT_ARM_MHU_1_IRQ_0_PRIORITY, DT_INST_1_ARM_MHU_IRQ_0_PRIORITY,
ipm_mhu_isr, ipm_mhu_isr,
DEVICE_GET(mhu_1), DEVICE_GET(mhu_1),
0); 0);
irq_enable(DT_ARM_MHU_1_IRQ_0); irq_enable(DT_INST_1_ARM_MHU_IRQ_0);
} }

View file

@ -465,14 +465,14 @@ static const struct led_driver_api ht16k33_leds_api = {
#define HT16K33_DEVICE(id) \ #define HT16K33_DEVICE(id) \
static const struct ht16k33_cfg ht16k33_##id##_cfg = { \ static const struct ht16k33_cfg ht16k33_##id##_cfg = { \
.i2c_dev_name = DT_HOLTEK_HT16K33_##id##_BUS_NAME, \ .i2c_dev_name = DT_INST_##id##_HOLTEK_HT16K33_BUS_NAME, \
.i2c_addr = DT_HOLTEK_HT16K33_##id##_BASE_ADDRESS, \ .i2c_addr = DT_INST_##id##_HOLTEK_HT16K33_BASE_ADDRESS, \
.irq_enabled = false, \ .irq_enabled = false, \
}; \ }; \
\ \
static struct ht16k33_data ht16k33_##id##_data; \ static struct ht16k33_data ht16k33_##id##_data; \
\ \
DEVICE_AND_API_INIT(ht16k33_##id, DT_HOLTEK_HT16K33_##id##_LABEL, \ DEVICE_AND_API_INIT(ht16k33_##id, DT_INST_##id##_HOLTEK_HT16K33_LABEL, \
&ht16k33_init, &ht16k33_##id##_data, \ &ht16k33_init, &ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \ &ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api) CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
@ -480,19 +480,19 @@ DEVICE_AND_API_INIT(ht16k33_##id, DT_HOLTEK_HT16K33_##id##_LABEL, \
#ifdef CONFIG_HT16K33_KEYSCAN #ifdef CONFIG_HT16K33_KEYSCAN
#define HT16K33_DEVICE_WITH_IRQ(id) \ #define HT16K33_DEVICE_WITH_IRQ(id) \
static const struct ht16k33_cfg ht16k33_##id##_cfg = { \ static const struct ht16k33_cfg ht16k33_##id##_cfg = { \
.i2c_dev_name = DT_HOLTEK_HT16K33_##id##_BUS_NAME, \ .i2c_dev_name = DT_INST_##id##_HOLTEK_HT16K33_BUS_NAME, \
.i2c_addr = DT_HOLTEK_HT16K33_##id##_BASE_ADDRESS, \ .i2c_addr = DT_INST_##id##_HOLTEK_HT16K33_BASE_ADDRESS, \
.irq_enabled = true, \ .irq_enabled = true, \
.irq_dev_name = \ .irq_dev_name = \
DT_HOLTEK_HT16K33_##id##_IRQ_GPIOS_CONTROLLER, \ DT_INST_##id##_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER, \
.irq_pin = DT_HOLTEK_HT16K33_##id##_IRQ_GPIOS_PIN, \ .irq_pin = DT_INST_##id##_HOLTEK_HT16K33_IRQ_GPIOS_PIN, \
.irq_flags = \ .irq_flags = \
DT_HOLTEK_HT16K33_##id##_IRQ_GPIOS_FLAGS, \ DT_INST_##id##_HOLTEK_HT16K33_IRQ_GPIOS_FLAGS, \
}; \ }; \
\ \
static struct ht16k33_data ht16k33_##id##_data; \ static struct ht16k33_data ht16k33_##id##_data; \
\ \
DEVICE_AND_API_INIT(ht16k33_##id, DT_HOLTEK_HT16K33_##id##_LABEL, \ DEVICE_AND_API_INIT(ht16k33_##id, DT_INST_##id##_HOLTEK_HT16K33_LABEL, \
&ht16k33_init, &ht16k33_##id##_data, \ &ht16k33_init, &ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \ &ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api) CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
@ -503,7 +503,7 @@ DEVICE_AND_API_INIT(ht16k33_##id, DT_HOLTEK_HT16K33_##id##_LABEL, \
/* Support up to eight HT16K33 devices */ /* Support up to eight HT16K33 devices */
#ifdef DT_HOLTEK_HT16K33_0 #ifdef DT_HOLTEK_HT16K33_0
#ifdef DT_HOLTEK_HT16K33_0_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_0_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(0); HT16K33_DEVICE_WITH_IRQ(0);
#else #else
HT16K33_DEVICE(0); HT16K33_DEVICE(0);
@ -511,7 +511,7 @@ HT16K33_DEVICE(0);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_1 #ifdef DT_HOLTEK_HT16K33_1
#ifdef DT_HOLTEK_HT16K33_1_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_1_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(1); HT16K33_DEVICE_WITH_IRQ(1);
#else #else
HT16K33_DEVICE(1); HT16K33_DEVICE(1);
@ -519,7 +519,7 @@ HT16K33_DEVICE(1);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_2 #ifdef DT_HOLTEK_HT16K33_2
#ifdef DT_HOLTEK_HT16K33_2_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_2_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(2); HT16K33_DEVICE_WITH_IRQ(2);
#else #else
HT16K33_DEVICE(2); HT16K33_DEVICE(2);
@ -527,7 +527,7 @@ HT16K33_DEVICE(2);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_3 #ifdef DT_HOLTEK_HT16K33_3
#ifdef DT_HOLTEK_HT16K33_3_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_3_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(3); HT16K33_DEVICE_WITH_IRQ(3);
#else #else
HT16K33_DEVICE(3); HT16K33_DEVICE(3);
@ -535,7 +535,7 @@ HT16K33_DEVICE(3);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_4 #ifdef DT_HOLTEK_HT16K33_4
#ifdef DT_HOLTEK_HT16K33_4_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_4_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(4); HT16K33_DEVICE_WITH_IRQ(4);
#else #else
HT16K33_DEVICE(4); HT16K33_DEVICE(4);
@ -543,7 +543,7 @@ HT16K33_DEVICE(4);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_5 #ifdef DT_HOLTEK_HT16K33_5
#ifdef DT_HOLTEK_HT16K33_5_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_5_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(5); HT16K33_DEVICE_WITH_IRQ(5);
#else #else
HT16K33_DEVICE(5); HT16K33_DEVICE(5);
@ -551,7 +551,7 @@ HT16K33_DEVICE(5);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_6 #ifdef DT_HOLTEK_HT16K33_6
#ifdef DT_HOLTEK_HT16K33_6_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_6_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(6); HT16K33_DEVICE_WITH_IRQ(6);
#else #else
HT16K33_DEVICE(6); HT16K33_DEVICE(6);
@ -559,7 +559,7 @@ HT16K33_DEVICE(6);
#endif #endif
#ifdef DT_HOLTEK_HT16K33_7 #ifdef DT_HOLTEK_HT16K33_7
#ifdef DT_HOLTEK_HT16K33_7_IRQ_GPIOS_CONTROLLER #ifdef DT_INST_7_HOLTEK_HT16K33_IRQ_GPIOS_CONTROLLER
HT16K33_DEVICE_WITH_IRQ(7); HT16K33_DEVICE_WITH_IRQ(7);
#else #else
HT16K33_DEVICE(7); HT16K33_DEVICE(7);

View file

@ -27,9 +27,9 @@
LOG_MODULE_REGISTER(lp3943); LOG_MODULE_REGISTER(lp3943);
#ifdef CONFIG_HAS_DTS_I2C #ifdef CONFIG_HAS_DTS_I2C
#define CONFIG_LP3943_DEV_NAME DT_TI_LP3943_0_LABEL #define CONFIG_LP3943_DEV_NAME DT_INST_0_TI_LP3943_LABEL
#define CONFIG_LP3943_I2C_ADDRESS DT_TI_LP3943_0_BASE_ADDRESS #define CONFIG_LP3943_I2C_ADDRESS DT_INST_0_TI_LP3943_BASE_ADDRESS
#define CONFIG_LP3943_I2C_MASTER_DEV_NAME DT_TI_LP3943_0_BUS_NAME #define CONFIG_LP3943_I2C_MASTER_DEV_NAME DT_INST_0_TI_LP3943_BUS_NAME
#endif #endif
#include "led_context.h" #include "led_context.h"

View file

@ -38,9 +38,9 @@
LOG_MODULE_REGISTER(lp5562); LOG_MODULE_REGISTER(lp5562);
#ifdef CONFIG_HAS_DTS_I2C #ifdef CONFIG_HAS_DTS_I2C
#define CONFIG_LP5562_DEV_NAME DT_TI_LP5562_0_LABEL #define CONFIG_LP5562_DEV_NAME DT_INST_0_TI_LP5562_LABEL
#define CONFIG_LP5562_I2C_ADDRESS DT_TI_LP5562_0_BASE_ADDRESS #define CONFIG_LP5562_I2C_ADDRESS DT_INST_0_TI_LP5562_BASE_ADDRESS
#define CONFIG_LP5562_I2C_MASTER_DEV_NAME DT_TI_LP5562_0_BUS_NAME #define CONFIG_LP5562_I2C_MASTER_DEV_NAME DT_INST_0_TI_LP5562_BUS_NAME
#endif #endif
#include "led_context.h" #include "led_context.h"

View file

@ -19,9 +19,9 @@
LOG_MODULE_REGISTER(pca9633); LOG_MODULE_REGISTER(pca9633);
#ifdef CONFIG_HAS_DTS_I2C #ifdef CONFIG_HAS_DTS_I2C
#define CONFIG_PCA9633_DEV_NAME DT_NXP_PCA9633_0_LABEL #define CONFIG_PCA9633_DEV_NAME DT_INST_0_NXP_PCA9633_LABEL
#define CONFIG_PCA9633_I2C_ADDRESS DT_NXP_PCA9633_0_BASE_ADDRESS #define CONFIG_PCA9633_I2C_ADDRESS DT_INST_0_NXP_PCA9633_BASE_ADDRESS
#define CONFIG_PCA9633_I2C_MASTER_DEV_NAME DT_NXP_PCA9633_0_BUS_NAME #define CONFIG_PCA9633_I2C_MASTER_DEV_NAME DT_INST_0_NXP_PCA9633_BUS_NAME
#endif #endif
#include "led_context.h" #include "led_context.h"

View file

@ -81,13 +81,13 @@ static int apa102_init(struct device *dev)
{ {
struct apa102_data *data = dev->driver_data; struct apa102_data *data = dev->driver_data;
data->spi = device_get_binding(DT_APA_APA102_0_BUS_NAME); data->spi = device_get_binding(DT_INST_0_APA_APA102_BUS_NAME);
if (!data->spi) { if (!data->spi) {
return -ENODEV; return -ENODEV;
} }
data->cfg.slave = DT_APA_APA102_0_BASE_ADDRESS; data->cfg.slave = DT_INST_0_APA_APA102_BASE_ADDRESS;
data->cfg.frequency = DT_APA_APA102_0_SPI_MAX_FREQUENCY; data->cfg.frequency = DT_INST_0_APA_APA102_SPI_MAX_FREQUENCY;
data->cfg.operation = data->cfg.operation =
SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8); SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8);
@ -101,6 +101,6 @@ static const struct led_strip_driver_api apa102_api = {
.update_channels = apa102_update_channels, .update_channels = apa102_update_channels,
}; };
DEVICE_AND_API_INIT(apa102_0, DT_APA_APA102_0_LABEL, apa102_init, DEVICE_AND_API_INIT(apa102_0, DT_INST_0_APA_APA102_LABEL, apa102_init,
&apa102_data_0, NULL, POST_KERNEL, &apa102_data_0, NULL, POST_KERNEL,
CONFIG_LED_STRIP_INIT_PRIORITY, &apa102_api); CONFIG_LED_STRIP_INIT_PRIORITY, &apa102_api);

View file

@ -10,17 +10,17 @@
#include <string.h> #include <string.h>
#ifdef DT_COLORWAY_LPD8806_0 #ifdef DT_COLORWAY_LPD8806_0
#define DT_COLORWAY_LPD880X_0 DT_COLORWAY_LPD8806_0 #define DT_INST_0_COLORWAY_LPD880X DT_INST_0_COLORWAY_LPD8806
#define DT_COLORWAY_LPD880X_0_BASE_ADDRESS DT_COLORWAY_LPD8806_0_BASE_ADDRESS #define DT_INST_0_COLORWAY_LPD880X_BASE_ADDRESS DT_INST_0_COLORWAY_LPD8806_BASE_ADDRESS
#define DT_COLORWAY_LPD880X_0_BUS_NAME DT_COLORWAY_LPD8806_0_BUS_NAME #define DT_INST_0_COLORWAY_LPD880X_BUS_NAME DT_INST_0_COLORWAY_LPD8806_BUS_NAME
#define DT_COLORWAY_LPD880X_0_LABEL DT_COLORWAY_LPD8806_0_LABEL #define DT_INST_0_COLORWAY_LPD880X_LABEL DT_INST_0_COLORWAY_LPD8806_LABEL
#define DT_COLORWAY_LPD880X_0_SPI_MAX_FREQUENCY DT_COLORWAY_LPD8806_0_SPI_MAX_FREQUENCY #define DT_INST_0_COLORWAY_LPD880X_SPI_MAX_FREQUENCY DT_INST_0_COLORWAY_LPD8806_SPI_MAX_FREQUENCY
#else #else
#define DT_COLORWAY_LPD880X_0 DT_COLORWAY_LPD8803_0 #define DT_INST_0_COLORWAY_LPD880X DT_INST_0_COLORWAY_LPD8803
#define DT_COLORWAY_LPD880X_0_BASE_ADDRESS DT_COLORWAY_LPD8803_0_BASE_ADDRESS #define DT_INST_0_COLORWAY_LPD880X_BASE_ADDRESS DT_INST_0_COLORWAY_LPD8803_BASE_ADDRESS
#define DT_COLORWAY_LPD880X_0_BUS_NAME DT_COLORWAY_LPD8803_0_BUS_NAME #define DT_INST_0_COLORWAY_LPD880X_BUS_NAME DT_INST_0_COLORWAY_LPD8803_BUS_NAME
#define DT_COLORWAY_LPD880X_0_LABEL DT_COLORWAY_LPD8803_0_LABEL #define DT_INST_0_COLORWAY_LPD880X_LABEL DT_INST_0_COLORWAY_LPD8803_LABEL
#define DT_COLORWAY_LPD880X_0_SPI_MAX_FREQUENCY DT_COLORWAY_LPD8803_0_SPI_MAX_FREQUENCY #define DT_INST_0_COLORWAY_LPD880X_SPI_MAX_FREQUENCY DT_INST_0_COLORWAY_LPD8803_SPI_MAX_FREQUENCY
#endif #endif
#define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL #define LOG_LEVEL CONFIG_LED_STRIP_LOG_LEVEL
@ -139,16 +139,16 @@ static int lpd880x_strip_init(struct device *dev)
struct lpd880x_data *data = dev->driver_data; struct lpd880x_data *data = dev->driver_data;
struct spi_config *config = &data->config; struct spi_config *config = &data->config;
data->spi = device_get_binding(DT_COLORWAY_LPD880X_0_BUS_NAME); data->spi = device_get_binding(DT_INST_0_COLORWAY_LPD880X_BUS_NAME);
if (!data->spi) { if (!data->spi) {
LOG_ERR("SPI device %s not found", LOG_ERR("SPI device %s not found",
DT_COLORWAY_LPD880X_0_BUS_NAME); DT_INST_0_COLORWAY_LPD880X_BUS_NAME);
return -ENODEV; return -ENODEV;
} }
config->frequency = DT_COLORWAY_LPD880X_0_SPI_MAX_FREQUENCY; config->frequency = DT_INST_0_COLORWAY_LPD880X_SPI_MAX_FREQUENCY;
config->operation = LPD880X_SPI_OPERATION; config->operation = LPD880X_SPI_OPERATION;
config->slave = DT_COLORWAY_LPD880X_0_BASE_ADDRESS; /* MOSI/CLK only; CS is not supported. */ config->slave = DT_INST_0_COLORWAY_LPD880X_BASE_ADDRESS; /* MOSI/CLK only; CS is not supported. */
config->cs = NULL; config->cs = NULL;
return 0; return 0;
@ -161,7 +161,7 @@ static const struct led_strip_driver_api lpd880x_strip_api = {
.update_channels = lpd880x_strip_update_channels, .update_channels = lpd880x_strip_update_channels,
}; };
DEVICE_AND_API_INIT(lpd880x_strip, DT_COLORWAY_LPD880X_0_LABEL, DEVICE_AND_API_INIT(lpd880x_strip, DT_INST_0_COLORWAY_LPD880X_LABEL,
lpd880x_strip_init, &lpd880x_strip_data, lpd880x_strip_init, &lpd880x_strip_data,
NULL, POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY,
&lpd880x_strip_api); &lpd880x_strip_api);

View file

@ -29,7 +29,7 @@ LOG_MODULE_REGISTER(ws2812);
SPI_WORD_SET(8) | \ SPI_WORD_SET(8) | \
SPI_LINES_SINGLE) SPI_LINES_SINGLE)
#define SPI_FREQ DT_WORLDSEMI_WS2812_0_SPI_MAX_FREQUENCY #define SPI_FREQ DT_INST_0_WORLDSEMI_WS2812_SPI_MAX_FREQUENCY
#define ONE_FRAME CONFIG_WS2812_STRIP_ONE_FRAME #define ONE_FRAME CONFIG_WS2812_STRIP_ONE_FRAME
#define ZERO_FRAME CONFIG_WS2812_STRIP_ZERO_FRAME #define ZERO_FRAME CONFIG_WS2812_STRIP_ZERO_FRAME
#define RED_OFFSET (8 * sizeof(u8_t) * CONFIG_WS2812_RED_ORDER) #define RED_OFFSET (8 * sizeof(u8_t) * CONFIG_WS2812_RED_ORDER)
@ -181,16 +181,16 @@ static int ws2812_strip_init(struct device *dev)
struct ws2812_data *data = dev->driver_data; struct ws2812_data *data = dev->driver_data;
struct spi_config *config = &data->config; struct spi_config *config = &data->config;
data->spi = device_get_binding(DT_WORLDSEMI_WS2812_0_BUS_NAME); data->spi = device_get_binding(DT_INST_0_WORLDSEMI_WS2812_BUS_NAME);
if (!data->spi) { if (!data->spi) {
LOG_ERR("SPI device %s not found", LOG_ERR("SPI device %s not found",
DT_WORLDSEMI_WS2812_0_BUS_NAME); DT_INST_0_WORLDSEMI_WS2812_BUS_NAME);
return -ENODEV; return -ENODEV;
} }
config->frequency = SPI_FREQ; config->frequency = SPI_FREQ;
config->operation = SPI_OPER; config->operation = SPI_OPER;
config->slave = DT_WORLDSEMI_WS2812_0_BASE_ADDRESS; config->slave = DT_INST_0_WORLDSEMI_WS2812_BASE_ADDRESS;
config->cs = NULL; config->cs = NULL;
return 0; return 0;
@ -203,7 +203,7 @@ static const struct led_strip_driver_api ws2812_strip_api = {
.update_channels = ws2812_strip_update_channels, .update_channels = ws2812_strip_update_channels,
}; };
DEVICE_AND_API_INIT(ws2812_strip, DT_WORLDSEMI_WS2812_0_LABEL, DEVICE_AND_API_INIT(ws2812_strip, DT_INST_0_WORLDSEMI_WS2812_LABEL,
ws2812_strip_init, &ws2812_strip_data, ws2812_strip_init, &ws2812_strip_data,
NULL, POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_LED_STRIP_INIT_PRIORITY,
&ws2812_strip_api); &ws2812_strip_api);

View file

@ -32,7 +32,7 @@ static int send_buf(u8_t *buf, size_t len)
*/ */
u32_t i = 0U; u32_t i = 0U;
clock = device_get_binding(DT_NORDIC_NRF_CLOCK_0_LABEL "_16M"); clock = device_get_binding(DT_INST_0_NORDIC_NRF_CLOCK_LABEL "_16M");
if (!clock) { if (!clock) {
LOG_ERR("Unable to get HF clock"); LOG_ERR("Unable to get HF clock");
return -EIO; return -EIO;

View file

@ -63,15 +63,15 @@ enum mdm_control_pins {
static const struct mdm_control_pinconfig pinconfig[] = { static const struct mdm_control_pinconfig pinconfig[] = {
/* MDM_POWER */ /* MDM_POWER */
PINCONFIG(DT_UBLOX_SARA_R4_0_MDM_POWER_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_UBLOX_SARA_R4_MDM_POWER_GPIOS_CONTROLLER,
DT_UBLOX_SARA_R4_0_MDM_POWER_GPIOS_PIN), DT_INST_0_UBLOX_SARA_R4_MDM_POWER_GPIOS_PIN),
/* MDM_RESET */ /* MDM_RESET */
PINCONFIG(DT_UBLOX_SARA_R4_0_MDM_RESET_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_UBLOX_SARA_R4_MDM_RESET_GPIOS_CONTROLLER,
DT_UBLOX_SARA_R4_0_MDM_RESET_GPIOS_PIN), DT_INST_0_UBLOX_SARA_R4_MDM_RESET_GPIOS_PIN),
}; };
#define MDM_UART_DEV_NAME DT_UBLOX_SARA_R4_0_BUS_NAME #define MDM_UART_DEV_NAME DT_INST_0_UBLOX_SARA_R4_BUS_NAME
#define MDM_POWER_ENABLE 1 #define MDM_POWER_ENABLE 1
#define MDM_POWER_DISABLE 0 #define MDM_POWER_DISABLE 0

View file

@ -57,7 +57,7 @@ enum mdm_control_pins {
MDM_KEEP_AWAKE, MDM_KEEP_AWAKE,
MDM_RESET, MDM_RESET,
SHLD_3V3_1V8_SIG_TRANS_ENA, SHLD_3V3_1V8_SIG_TRANS_ENA,
#ifdef DT_WNC_M14A2A_0_MDM_SEND_OK_GPIOS_PIN #ifdef DT_INST_0_WNC_M14A2A_MDM_SEND_OK_GPIOS_PIN
MDM_SEND_OK, MDM_SEND_OK,
#endif #endif
MAX_MDM_CONTROL_PINS, MAX_MDM_CONTROL_PINS,
@ -65,33 +65,33 @@ enum mdm_control_pins {
static const struct mdm_control_pinconfig pinconfig[] = { static const struct mdm_control_pinconfig pinconfig[] = {
/* MDM_BOOT_MODE_SEL */ /* MDM_BOOT_MODE_SEL */
PINCONFIG(DT_WNC_M14A2A_0_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_WNC_M14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER,
DT_WNC_M14A2A_0_MDM_BOOT_MODE_SEL_GPIOS_PIN), DT_INST_0_WNC_M14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN),
/* MDM_POWER */ /* MDM_POWER */
PINCONFIG(DT_WNC_M14A2A_0_MDM_POWER_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_WNC_M14A2A_MDM_POWER_GPIOS_CONTROLLER,
DT_WNC_M14A2A_0_MDM_POWER_GPIOS_PIN), DT_INST_0_WNC_M14A2A_MDM_POWER_GPIOS_PIN),
/* MDM_KEEP_AWAKE */ /* MDM_KEEP_AWAKE */
PINCONFIG(DT_WNC_M14A2A_0_MDM_KEEP_AWAKE_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_WNC_M14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER,
DT_WNC_M14A2A_0_MDM_KEEP_AWAKE_GPIOS_PIN), DT_INST_0_WNC_M14A2A_MDM_KEEP_AWAKE_GPIOS_PIN),
/* MDM_RESET */ /* MDM_RESET */
PINCONFIG(DT_WNC_M14A2A_0_MDM_RESET_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_WNC_M14A2A_MDM_RESET_GPIOS_CONTROLLER,
DT_WNC_M14A2A_0_MDM_RESET_GPIOS_PIN), DT_INST_0_WNC_M14A2A_MDM_RESET_GPIOS_PIN),
/* SHLD_3V3_1V8_SIG_TRANS_ENA */ /* SHLD_3V3_1V8_SIG_TRANS_ENA */
PINCONFIG(DT_WNC_M14A2A_0_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_WNC_M14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER,
DT_WNC_M14A2A_0_MDM_SHLD_TRANS_ENA_GPIOS_PIN), DT_INST_0_WNC_M14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN),
#ifdef DT_WNC_M14A2A_0_MDM_SEND_OK_GPIOS_PIN #ifdef DT_INST_0_WNC_M14A2A_MDM_SEND_OK_GPIOS_PIN
/* MDM_SEND_OK */ /* MDM_SEND_OK */
PINCONFIG(DT_WNC_M14A2A_0_MDM_SEND_OK_GPIOS_CONTROLLER, PINCONFIG(DT_INST_0_WNC_M14A2A_MDM_SEND_OK_GPIOS_CONTROLLER,
DT_WNC_M14A2A_0_MDM_SEND_OK_GPIOS_PIN), DT_INST_0_WNC_M14A2A_MDM_SEND_OK_GPIOS_PIN),
#endif #endif
}; };
#define MDM_UART_DEV_NAME DT_WNC_M14A2A_0_BUS_NAME #define MDM_UART_DEV_NAME DT_INST_0_WNC_M14A2A_BUS_NAME
#define MDM_BOOT_MODE_SPECIAL 0 #define MDM_BOOT_MODE_SPECIAL 0
#define MDM_BOOT_MODE_NORMAL 1 #define MDM_BOOT_MODE_NORMAL 1
@ -1248,7 +1248,7 @@ static int modem_pin_init(void)
LOG_DBG("MDM_KEEP_AWAKE_PIN -> ENABLED"); LOG_DBG("MDM_KEEP_AWAKE_PIN -> ENABLED");
gpio_pin_write(ictx.gpio_port_dev[MDM_KEEP_AWAKE], gpio_pin_write(ictx.gpio_port_dev[MDM_KEEP_AWAKE],
pinconfig[MDM_KEEP_AWAKE].pin, MDM_KEEP_AWAKE_ENABLED); pinconfig[MDM_KEEP_AWAKE].pin, MDM_KEEP_AWAKE_ENABLED);
#ifdef DT_WNC_M14A2A_0_MDM_SEND_OK_GPIOS_PIN #ifdef DT_INST_0_WNC_M14A2A_MDM_SEND_OK_GPIOS_PIN
LOG_DBG("MDM_SEND_OK_PIN -> ENABLED"); LOG_DBG("MDM_SEND_OK_PIN -> ENABLED");
gpio_pin_write(ictx.gpio_port_dev[MDM_SEND_OK], gpio_pin_write(ictx.gpio_port_dev[MDM_SEND_OK],
pinconfig[MDM_SEND_OK].pin, MDM_SEND_OK_ENABLED); pinconfig[MDM_SEND_OK].pin, MDM_SEND_OK_ENABLED);

View file

@ -14,13 +14,13 @@
LOG_MODULE_REGISTER(pwm_nrf5_sw); LOG_MODULE_REGISTER(pwm_nrf5_sw);
/* One compare channel is needed to set the PWM period, hence +1. */ /* One compare channel is needed to set the PWM period, hence +1. */
#if ((DT_NORDIC_NRF_SW_PWM_0_CHANNEL_COUNT + 1) > \ #if ((DT_INST_0_NORDIC_NRF_SW_PWM_CHANNEL_COUNT + 1) > \
(_CONCAT( \ (_CONCAT( \
_CONCAT(TIMER, DT_NORDIC_NRF_SW_PWM_0_TIMER_INSTANCE), \ _CONCAT(TIMER, DT_INST_0_NORDIC_NRF_SW_PWM_TIMER_INSTANCE), \
_CC_NUM))) _CC_NUM)))
#error "Invalid number of PWM channels configured." #error "Invalid number of PWM channels configured."
#endif #endif
#define PWM_0_MAP_SIZE DT_NORDIC_NRF_SW_PWM_0_CHANNEL_COUNT #define PWM_0_MAP_SIZE DT_INST_0_NORDIC_NRF_SW_PWM_CHANNEL_COUNT
struct pwm_config { struct pwm_config {
NRF_TIMER_Type *timer; NRF_TIMER_Type *timer;
@ -245,11 +245,11 @@ static int pwm_nrf5_sw_init(struct device *dev)
} }
static const struct pwm_config pwm_nrf5_sw_0_config = { static const struct pwm_config pwm_nrf5_sw_0_config = {
.timer = _CONCAT(NRF_TIMER, DT_NORDIC_NRF_SW_PWM_0_TIMER_INSTANCE), .timer = _CONCAT(NRF_TIMER, DT_INST_0_NORDIC_NRF_SW_PWM_TIMER_INSTANCE),
.ppi_base = DT_NORDIC_NRF_SW_PWM_0_PPI_BASE, .ppi_base = DT_INST_0_NORDIC_NRF_SW_PWM_PPI_BASE,
.gpiote_base = DT_NORDIC_NRF_SW_PWM_0_GPIOTE_BASE, .gpiote_base = DT_INST_0_NORDIC_NRF_SW_PWM_GPIOTE_BASE,
.map_size = PWM_0_MAP_SIZE, .map_size = PWM_0_MAP_SIZE,
.prescaler = DT_NORDIC_NRF_SW_PWM_0_CLOCK_PRESCALER, .prescaler = DT_INST_0_NORDIC_NRF_SW_PWM_CLOCK_PRESCALER,
}; };
static struct pwm_data pwm_nrf5_sw_0_data; static struct pwm_data pwm_nrf5_sw_0_data;

View file

@ -92,13 +92,13 @@ static const struct pwm_driver_api sam_pwm_driver_api = {
#ifdef DT_ATMEL_SAM_PWM_0 #ifdef DT_ATMEL_SAM_PWM_0
static const struct sam_pwm_config sam_pwm_config_0 = { static const struct sam_pwm_config sam_pwm_config_0 = {
.regs = (Pwm *)DT_ATMEL_SAM_PWM_0_BASE_ADDRESS, .regs = (Pwm *)DT_INST_0_ATMEL_SAM_PWM_BASE_ADDRESS,
.id = DT_ATMEL_SAM_PWM_0_PERIPHERAL_ID, .id = DT_INST_0_ATMEL_SAM_PWM_PERIPHERAL_ID,
.prescaler = DT_ATMEL_SAM_PWM_0_PRESCALER, .prescaler = DT_INST_0_ATMEL_SAM_PWM_PRESCALER,
.divider = DT_ATMEL_SAM_PWM_0_DIVIDER, .divider = DT_INST_0_ATMEL_SAM_PWM_DIVIDER,
}; };
DEVICE_AND_API_INIT(sam_pwm_0, DT_ATMEL_SAM_PWM_0_LABEL, &sam_pwm_init, DEVICE_AND_API_INIT(sam_pwm_0, DT_INST_0_ATMEL_SAM_PWM_LABEL, &sam_pwm_init,
NULL, &sam_pwm_config_0, NULL, &sam_pwm_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&sam_pwm_driver_api); &sam_pwm_driver_api);

View file

@ -238,15 +238,15 @@ static const struct pwm_driver_api pwm_sifive_api = {
CONFIG_PWM_SIFIVE_INIT_PRIORITY, \ CONFIG_PWM_SIFIVE_INIT_PRIORITY, \
&pwm_sifive_api) &pwm_sifive_api)
#ifdef DT_SIFIVE_PWM0_0_LABEL #ifdef DT_INST_0_SIFIVE_PWM0_LABEL
PWM_SIFIVE_INIT(0); PWM_SIFIVE_INIT(0);
#endif /* DT_SIFIVE_PWM0_0_LABEL */ #endif /* DT_INST_0_SIFIVE_PWM0_LABEL */
#ifdef DT_SIFIVE_PWM0_1_LABEL #ifdef DT_INST_1_SIFIVE_PWM0_LABEL
PWM_SIFIVE_INIT(1); PWM_SIFIVE_INIT(1);
#endif /* DT_SIFIVE_PWM0_1_LABEL */ #endif /* DT_INST_1_SIFIVE_PWM0_LABEL */
#ifdef DT_SIFIVE_PWM0_2_LABEL #ifdef DT_INST_2_SIFIVE_PWM0_LABEL
PWM_SIFIVE_INIT(2); PWM_SIFIVE_INIT(2);
#endif /* DT_SIFIVE_PWM0_2_LABEL */ #endif /* DT_INST_2_SIFIVE_PWM0_LABEL */

View file

@ -217,14 +217,14 @@ static int adt7420_init(struct device *dev)
static struct adt7420_data adt7420_driver; static struct adt7420_data adt7420_driver;
static const struct adt7420_dev_config adt7420_config = { static const struct adt7420_dev_config adt7420_config = {
.i2c_port = DT_ADI_ADT7420_0_BUS_NAME, .i2c_port = DT_INST_0_ADI_ADT7420_BUS_NAME,
.i2c_addr = DT_ADI_ADT7420_0_BASE_ADDRESS, .i2c_addr = DT_INST_0_ADI_ADT7420_BASE_ADDRESS,
#ifdef CONFIG_ADT7420_TRIGGER #ifdef CONFIG_ADT7420_TRIGGER
.gpio_port = DT_ADI_ADT7420_0_INT_GPIOS_CONTROLLER, .gpio_port = DT_INST_0_ADI_ADT7420_INT_GPIOS_CONTROLLER,
.int_gpio = DT_ADI_ADT7420_0_INT_GPIOS_PIN, .int_gpio = DT_INST_0_ADI_ADT7420_INT_GPIOS_PIN,
#endif #endif
}; };
DEVICE_AND_API_INIT(adt7420, DT_ADI_ADT7420_0_LABEL, adt7420_init, &adt7420_driver, DEVICE_AND_API_INIT(adt7420, DT_INST_0_ADI_ADT7420_LABEL, adt7420_init, &adt7420_driver,
&adt7420_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &adt7420_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&adt7420_driver_api); &adt7420_driver_api);

View file

@ -734,7 +734,7 @@ static int adxl362_init(struct device *dev)
data->spi_cfg.frequency = config->spi_max_frequency; data->spi_cfg.frequency = config->spi_max_frequency;
data->spi_cfg.slave = config->spi_slave; data->spi_cfg.slave = config->spi_slave;
#if defined(DT_ADI_ADXL362_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL362_CS_GPIO_CONTROLLER)
data->adxl362_cs_ctrl.gpio_dev = data->adxl362_cs_ctrl.gpio_dev =
device_get_binding(config->gpio_cs_port); device_get_binding(config->gpio_cs_port);
if (!data->adxl362_cs_ctrl.gpio_dev) { if (!data->adxl362_cs_ctrl.gpio_dev) {
@ -785,19 +785,19 @@ static int adxl362_init(struct device *dev)
} }
static const struct adxl362_config adxl362_config = { static const struct adxl362_config adxl362_config = {
.spi_name = DT_ADI_ADXL362_0_BUS_NAME, .spi_name = DT_INST_0_ADI_ADXL362_BUS_NAME,
.spi_slave = DT_ADI_ADXL362_0_BASE_ADDRESS, .spi_slave = DT_INST_0_ADI_ADXL362_BASE_ADDRESS,
.spi_max_frequency = DT_ADI_ADXL362_0_SPI_MAX_FREQUENCY, .spi_max_frequency = DT_INST_0_ADI_ADXL362_SPI_MAX_FREQUENCY,
#if defined(DT_ADI_ADXL362_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL362_CS_GPIO_CONTROLLER)
.gpio_cs_port = DT_ADI_ADXL362_0_CS_GPIO_CONTROLLER, .gpio_cs_port = DT_INST_0_ADI_ADXL362_CS_GPIO_CONTROLLER,
.cs_gpio = DT_ADI_ADXL362_0_CS_GPIO_PIN, .cs_gpio = DT_INST_0_ADI_ADXL362_CS_GPIO_PIN,
#endif #endif
#if defined(CONFIG_ADXL362_TRIGGER) #if defined(CONFIG_ADXL362_TRIGGER)
.gpio_port = DT_ADI_ADXL362_0_INT1_GPIOS_CONTROLLER, .gpio_port = DT_INST_0_ADI_ADXL362_INT1_GPIOS_CONTROLLER,
.int_gpio = DT_ADI_ADXL362_0_INT1_GPIOS_PIN, .int_gpio = DT_INST_0_ADI_ADXL362_INT1_GPIOS_PIN,
#endif #endif
}; };
DEVICE_AND_API_INIT(adxl362, DT_ADI_ADXL362_0_LABEL, adxl362_init, DEVICE_AND_API_INIT(adxl362, DT_INST_0_ADI_ADXL362_LABEL, adxl362_init,
&adxl362_data, &adxl362_config, POST_KERNEL, &adxl362_data, &adxl362_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &adxl362_api_funcs); CONFIG_SENSOR_INIT_PRIORITY, &adxl362_api_funcs);

View file

@ -174,7 +174,7 @@ struct adxl362_config {
char *spi_name; char *spi_name;
u32_t spi_max_frequency; u32_t spi_max_frequency;
u16_t spi_slave; u16_t spi_slave;
#if defined(DT_ADI_ADXL362_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL362_CS_GPIO_CONTROLLER)
const char *gpio_cs_port; const char *gpio_cs_port;
u8_t cs_gpio; u8_t cs_gpio;
#endif #endif
@ -189,7 +189,7 @@ struct adxl362_config {
struct adxl362_data { struct adxl362_data {
struct device *spi; struct device *spi;
struct spi_config spi_cfg; struct spi_config spi_cfg;
#if defined(DT_ADI_ADXL362_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL362_CS_GPIO_CONTROLLER)
struct spi_cs_control adxl362_cs_ctrl; struct spi_cs_control adxl362_cs_ctrl;
#endif #endif
s16_t acc_x; s16_t acc_x;

View file

@ -898,7 +898,7 @@ static int adxl372_init(struct device *dev)
data->spi_cfg.frequency = cfg->spi_max_frequency; data->spi_cfg.frequency = cfg->spi_max_frequency;
data->spi_cfg.slave = cfg->spi_slave; data->spi_cfg.slave = cfg->spi_slave;
#if defined(DT_ADI_ADXL372_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL372_CS_GPIO_CONTROLLER)
/* handle SPI CS thru GPIO if it is the case */ /* handle SPI CS thru GPIO if it is the case */
data->adxl372_cs_ctrl.gpio_dev = device_get_binding(cfg->gpio_cs_port); data->adxl372_cs_ctrl.gpio_dev = device_get_binding(cfg->gpio_cs_port);
@ -925,21 +925,21 @@ static struct adxl372_data adxl372_data;
static const struct adxl372_dev_config adxl372_config = { static const struct adxl372_dev_config adxl372_config = {
#ifdef CONFIG_ADXL372_I2C #ifdef CONFIG_ADXL372_I2C
.i2c_port = DT_ADI_ADXL372_0_BUS_NAME, .i2c_port = DT_INST_0_ADI_ADXL372_BUS_NAME,
.i2c_addr = DT_ADI_ADXL372_0_BASE_ADDRESS, .i2c_addr = DT_INST_0_ADI_ADXL372_BASE_ADDRESS,
#endif #endif
#ifdef CONFIG_ADXL372_SPI #ifdef CONFIG_ADXL372_SPI
.spi_port = DT_ADI_ADXL372_0_BUS_NAME, .spi_port = DT_INST_0_ADI_ADXL372_BUS_NAME,
.spi_slave = DT_ADI_ADXL372_0_BASE_ADDRESS, .spi_slave = DT_INST_0_ADI_ADXL372_BASE_ADDRESS,
.spi_max_frequency = DT_ADI_ADXL372_0_SPI_MAX_FREQUENCY, .spi_max_frequency = DT_INST_0_ADI_ADXL372_SPI_MAX_FREQUENCY,
#ifdef DT_ADI_ADXL372_0_CS_GPIO_CONTROLLER #ifdef DT_INST_0_ADI_ADXL372_CS_GPIO_CONTROLLER
.gpio_cs_port = DT_ADI_ADXL372_0_CS_GPIO_CONTROLLER, .gpio_cs_port = DT_INST_0_ADI_ADXL372_CS_GPIO_CONTROLLER,
.cs_gpio = DT_ADI_ADXL372_0_CS_GPIO_PIN, .cs_gpio = DT_INST_0_ADI_ADXL372_CS_GPIO_PIN,
#endif #endif
#endif #endif
#ifdef CONFIG_ADXL372_TRIGGER #ifdef CONFIG_ADXL372_TRIGGER
.gpio_port = DT_ADI_ADXL372_0_INT1_GPIOS_CONTROLLER, .gpio_port = DT_INST_0_ADI_ADXL372_INT1_GPIOS_CONTROLLER,
.int_gpio = DT_ADI_ADXL372_0_INT1_GPIOS_PIN, .int_gpio = DT_INST_0_ADI_ADXL372_INT1_GPIOS_PIN,
#endif #endif
.max_peak_detect_mode = IS_ENABLED(CONFIG_ADXL372_PEAK_DETECT_MODE), .max_peak_detect_mode = IS_ENABLED(CONFIG_ADXL372_PEAK_DETECT_MODE),
@ -1011,6 +1011,6 @@ static const struct adxl372_dev_config adxl372_config = {
.op_mode = ADXL372_FULL_BW_MEASUREMENT, .op_mode = ADXL372_FULL_BW_MEASUREMENT,
}; };
DEVICE_AND_API_INIT(adxl372, DT_ADI_ADXL372_0_LABEL, adxl372_init, DEVICE_AND_API_INIT(adxl372, DT_INST_0_ADI_ADXL372_LABEL, adxl372_init,
&adxl372_data, &adxl372_config, POST_KERNEL, &adxl372_data, &adxl372_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &adxl372_api_funcs); CONFIG_SENSOR_INIT_PRIORITY, &adxl372_api_funcs);

View file

@ -282,7 +282,7 @@ struct adxl372_data {
struct device *bus; struct device *bus;
#ifdef CONFIG_ADXL372_SPI #ifdef CONFIG_ADXL372_SPI
struct spi_config spi_cfg; struct spi_config spi_cfg;
#if defined(DT_ADI_ADXL372_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL372_CS_GPIO_CONTROLLER)
struct spi_cs_control adxl372_cs_ctrl; struct spi_cs_control adxl372_cs_ctrl;
#endif #endif
#endif #endif
@ -318,7 +318,7 @@ struct adxl372_dev_config {
const char *spi_port; const char *spi_port;
u16_t spi_slave; u16_t spi_slave;
u32_t spi_max_frequency; u32_t spi_max_frequency;
#if defined(DT_ADI_ADXL372_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ADI_ADXL372_CS_GPIO_CONTROLLER)
const char *gpio_cs_port; const char *gpio_cs_port;
u8_t cs_gpio; u8_t cs_gpio;
#endif #endif

View file

@ -34,7 +34,7 @@ static int iaqcore_sample_fetch(struct device *dev, enum sensor_channel chan)
for (tries = 0; tries < CONFIG_IAQ_CORE_MAX_READ_RETRIES; tries++) { for (tries = 0; tries < CONFIG_IAQ_CORE_MAX_READ_RETRIES; tries++) {
ret = i2c_transfer(drv_data->i2c, &msg, 1, ret = i2c_transfer(drv_data->i2c, &msg, 1,
DT_AMS_IAQCORE_0_BASE_ADDRESS); DT_INST_0_AMS_IAQCORE_BASE_ADDRESS);
if (ret < 0) { if (ret < 0) {
LOG_ERR("Failed to read registers data [%d].", ret); LOG_ERR("Failed to read registers data [%d].", ret);
return -EIO; return -EIO;
@ -100,10 +100,10 @@ static int iaq_core_init(struct device *dev)
{ {
struct iaq_core_data *drv_data = dev->driver_data; struct iaq_core_data *drv_data = dev->driver_data;
drv_data->i2c = device_get_binding(DT_AMS_IAQCORE_0_BUS_NAME); drv_data->i2c = device_get_binding(DT_INST_0_AMS_IAQCORE_BUS_NAME);
if (drv_data->i2c == NULL) { if (drv_data->i2c == NULL) {
LOG_ERR("Failed to get pointer to %s device!", LOG_ERR("Failed to get pointer to %s device!",
DT_AMS_IAQCORE_0_BUS_NAME); DT_INST_0_AMS_IAQCORE_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
@ -112,6 +112,6 @@ static int iaq_core_init(struct device *dev)
static struct iaq_core_data iaq_core_driver; static struct iaq_core_data iaq_core_driver;
DEVICE_AND_API_INIT(iaq_core, DT_AMS_IAQCORE_0_LABEL, iaq_core_init, DEVICE_AND_API_INIT(iaq_core, DT_INST_0_AMS_IAQCORE_LABEL, iaq_core_init,
&iaq_core_driver, NULL, POST_KERNEL, &iaq_core_driver, NULL, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &iaq_core_driver_api); CONFIG_SENSOR_INIT_PRIORITY, &iaq_core_driver_api);

View file

@ -482,10 +482,10 @@ static const struct sensor_driver_api apds9960_driver_api = {
}; };
static const struct apds9960_config apds9960_config = { static const struct apds9960_config apds9960_config = {
.i2c_name = DT_AVAGO_APDS9960_0_BUS_NAME, .i2c_name = DT_INST_0_AVAGO_APDS9960_BUS_NAME,
.i2c_address = DT_AVAGO_APDS9960_0_BASE_ADDRESS, .i2c_address = DT_INST_0_AVAGO_APDS9960_BASE_ADDRESS,
.gpio_name = DT_AVAGO_APDS9960_0_INT_GPIOS_CONTROLLER, .gpio_name = DT_INST_0_AVAGO_APDS9960_INT_GPIOS_CONTROLLER,
.gpio_pin = DT_AVAGO_APDS9960_0_INT_GPIOS_PIN, .gpio_pin = DT_INST_0_AVAGO_APDS9960_INT_GPIOS_PIN,
#if CONFIG_APDS9960_PGAIN_8X #if CONFIG_APDS9960_PGAIN_8X
.pgain = APDS9960_PGAIN_8X, .pgain = APDS9960_PGAIN_8X,
#elif CONFIG_APDS9960_PGAIN_4X #elif CONFIG_APDS9960_PGAIN_4X
@ -531,11 +531,11 @@ static const struct apds9960_config apds9960_config = {
static struct apds9960_data apds9960_data; static struct apds9960_data apds9960_data;
#ifndef CONFIG_DEVICE_POWER_MANAGEMENT #ifndef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_AND_API_INIT(apds9960, DT_AVAGO_APDS9960_0_LABEL, &apds9960_init, DEVICE_AND_API_INIT(apds9960, DT_INST_0_AVAGO_APDS9960_LABEL, &apds9960_init,
&apds9960_data, &apds9960_config, POST_KERNEL, &apds9960_data, &apds9960_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &apds9960_driver_api); CONFIG_SENSOR_INIT_PRIORITY, &apds9960_driver_api);
#else #else
DEVICE_DEFINE(apds9960, DT_AVAGO_APDS9960_0_LABEL, apds9960_init, DEVICE_DEFINE(apds9960, DT_INST_0_AVAGO_APDS9960_LABEL, apds9960_init,
apds9960_device_ctrl, &apds9960_data, &apds9960_config, apds9960_device_ctrl, &apds9960_data, &apds9960_config,
POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &apds9960_driver_api); POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &apds9960_driver_api);
#endif #endif

View file

@ -336,17 +336,17 @@ static int bme280_chip_init(struct device *dev)
#ifdef DT_BOSCH_BME280_BUS_SPI #ifdef DT_BOSCH_BME280_BUS_SPI
static inline int bme280_spi_init(struct bme280_data *data) static inline int bme280_spi_init(struct bme280_data *data)
{ {
data->spi = device_get_binding(DT_BOSCH_BME280_0_BUS_NAME); data->spi = device_get_binding(DT_INST_0_BOSCH_BME280_BUS_NAME);
if (!data->spi) { if (!data->spi) {
LOG_DBG("spi device not found: %s", LOG_DBG("spi device not found: %s",
DT_BOSCH_BME280_0_BUS_NAME); DT_INST_0_BOSCH_BME280_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
data->spi_cfg.operation = SPI_WORD_SET(8) | SPI_TRANSFER_MSB | data->spi_cfg.operation = SPI_WORD_SET(8) | SPI_TRANSFER_MSB |
SPI_MODE_CPOL | SPI_MODE_CPHA; SPI_MODE_CPOL | SPI_MODE_CPHA;
data->spi_cfg.frequency = DT_BOSCH_BME280_0_SPI_MAX_FREQUENCY; data->spi_cfg.frequency = DT_INST_0_BOSCH_BME280_SPI_MAX_FREQUENCY;
data->spi_cfg.slave = DT_BOSCH_BME280_0_BASE_ADDRESS; data->spi_cfg.slave = DT_INST_0_BOSCH_BME280_BASE_ADDRESS;
return 0; return 0;
} }
@ -357,18 +357,18 @@ int bme280_init(struct device *dev)
struct bme280_data *data = dev->driver_data; struct bme280_data *data = dev->driver_data;
#ifdef DT_BOSCH_BME280_BUS_I2C #ifdef DT_BOSCH_BME280_BUS_I2C
data->i2c_master = device_get_binding(DT_BOSCH_BME280_0_BUS_NAME); data->i2c_master = device_get_binding(DT_INST_0_BOSCH_BME280_BUS_NAME);
if (!data->i2c_master) { if (!data->i2c_master) {
LOG_DBG("i2c master not found: %s", LOG_DBG("i2c master not found: %s",
DT_BOSCH_BME280_0_BUS_NAME); DT_INST_0_BOSCH_BME280_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
data->i2c_slave_addr = DT_BOSCH_BME280_0_BASE_ADDRESS; data->i2c_slave_addr = DT_INST_0_BOSCH_BME280_BASE_ADDRESS;
#elif defined DT_BOSCH_BME280_BUS_SPI #elif defined DT_BOSCH_BME280_BUS_SPI
if (bme280_spi_init(data) < 0) { if (bme280_spi_init(data) < 0) {
LOG_DBG("spi master not found: %s", LOG_DBG("spi master not found: %s",
DT_BOSCH_BME280_0_BUS_NAME); DT_INST_0_BOSCH_BME280_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
#endif #endif
@ -382,6 +382,6 @@ int bme280_init(struct device *dev)
static struct bme280_data bme280_data; static struct bme280_data bme280_data;
DEVICE_AND_API_INIT(bme280, DT_BOSCH_BME280_0_LABEL, bme280_init, &bme280_data, DEVICE_AND_API_INIT(bme280, DT_INST_0_BOSCH_BME280_LABEL, bme280_init, &bme280_data,
NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&bme280_api_funcs); &bme280_api_funcs);

View file

@ -401,14 +401,14 @@ static int bme680_init(struct device *dev)
struct bme680_data *data = dev->driver_data; struct bme680_data *data = dev->driver_data;
data->i2c_master = device_get_binding( data->i2c_master = device_get_binding(
DT_BOSCH_BME680_0_BUS_NAME); DT_INST_0_BOSCH_BME680_BUS_NAME);
if (!data->i2c_master) { if (!data->i2c_master) {
LOG_ERR("I2C master not found: %s", LOG_ERR("I2C master not found: %s",
DT_BOSCH_BME680_0_BUS_NAME); DT_INST_0_BOSCH_BME680_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
data->i2c_slave_addr = DT_BOSCH_BME680_0_BASE_ADDRESS; data->i2c_slave_addr = DT_INST_0_BOSCH_BME680_BASE_ADDRESS;
if (bme680_chip_init(dev) < 0) { if (bme680_chip_init(dev) < 0) {
return -EINVAL; return -EINVAL;
@ -424,6 +424,6 @@ static const struct sensor_driver_api bme680_api_funcs = {
static struct bme680_data bme680_data; static struct bme680_data bme680_data;
DEVICE_AND_API_INIT(bme680, DT_BOSCH_BME680_0_LABEL, bme680_init, &bme680_data, DEVICE_AND_API_INIT(bme680, DT_INST_0_BOSCH_BME680_LABEL, bme680_init, &bme680_data,
NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&bme680_api_funcs); &bme680_api_funcs);

View file

@ -796,16 +796,16 @@ int bmi160_init(struct device *dev)
u8_t val = 0U; u8_t val = 0U;
s32_t acc_range, gyr_range; s32_t acc_range, gyr_range;
bmi160->spi = device_get_binding(DT_BOSCH_BMI160_0_BUS_NAME); bmi160->spi = device_get_binding(DT_INST_0_BOSCH_BMI160_BUS_NAME);
if (!bmi160->spi) { if (!bmi160->spi) {
LOG_DBG("SPI master controller not found: %s.", LOG_DBG("SPI master controller not found: %s.",
DT_BOSCH_BMI160_0_BUS_NAME); DT_INST_0_BOSCH_BMI160_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
bmi160->spi_cfg.operation = SPI_WORD_SET(8); bmi160->spi_cfg.operation = SPI_WORD_SET(8);
bmi160->spi_cfg.frequency = DT_BOSCH_BMI160_0_SPI_MAX_FREQUENCY; bmi160->spi_cfg.frequency = DT_INST_0_BOSCH_BMI160_SPI_MAX_FREQUENCY;
bmi160->spi_cfg.slave = DT_BOSCH_BMI160_0_BASE_ADDRESS; bmi160->spi_cfg.slave = DT_INST_0_BOSCH_BMI160_BASE_ADDRESS;
/* reboot the chip */ /* reboot the chip */
if (bmi160_byte_write(dev, BMI160_REG_CMD, BMI160_CMD_SOFT_RESET) < 0) { if (bmi160_byte_write(dev, BMI160_REG_CMD, BMI160_CMD_SOFT_RESET) < 0) {
@ -900,13 +900,13 @@ int bmi160_init(struct device *dev)
const struct bmi160_device_config bmi160_config = { const struct bmi160_device_config bmi160_config = {
#if defined(CONFIG_BMI160_TRIGGER) #if defined(CONFIG_BMI160_TRIGGER)
.gpio_port = DT_BOSCH_BMI160_0_INT_GPIOS_CONTROLLER, .gpio_port = DT_INST_0_BOSCH_BMI160_INT_GPIOS_CONTROLLER,
.int_pin = DT_BOSCH_BMI160_0_INT_GPIOS_PIN, .int_pin = DT_INST_0_BOSCH_BMI160_INT_GPIOS_PIN,
#endif #endif
}; };
DEVICE_AND_API_INIT(bmi160, DT_BOSCH_BMI160_0_LABEL, bmi160_init, &bmi160_data, DEVICE_AND_API_INIT(bmi160, DT_INST_0_BOSCH_BMI160_LABEL, bmi160_init, &bmi160_data,
&bmi160_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &bmi160_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&bmi160_api); &bmi160_api);

View file

@ -28,7 +28,7 @@ static int ccs811_sample_fetch(struct device *dev, enum sensor_channel chan)
/* Check data ready flag for the measurement interval of 1 seconds */ /* Check data ready flag for the measurement interval of 1 seconds */
while (tries-- > 0) { while (tries-- > 0) {
if (i2c_reg_read_byte(drv_data->i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_reg_read_byte(drv_data->i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_STATUS, &status) < 0) { CCS811_REG_STATUS, &status) < 0) {
LOG_ERR("Failed to read Status register"); LOG_ERR("Failed to read Status register");
return -EIO; return -EIO;
@ -46,7 +46,7 @@ static int ccs811_sample_fetch(struct device *dev, enum sensor_channel chan)
return -EIO; return -EIO;
} }
if (i2c_burst_read(drv_data->i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_burst_read(drv_data->i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_ALG_RESULT_DATA, (u8_t *)buf, 8) < 0) { CCS811_REG_ALG_RESULT_DATA, (u8_t *)buf, 8) < 0) {
LOG_ERR("Failed to read conversion data."); LOG_ERR("Failed to read conversion data.");
return -EIO; return -EIO;
@ -117,7 +117,7 @@ static int switch_to_app_mode(struct device *i2c)
LOG_DBG("Switching to Application mode..."); LOG_DBG("Switching to Application mode...");
if (i2c_reg_read_byte(i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_reg_read_byte(i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_STATUS, &status) < 0) { CCS811_REG_STATUS, &status) < 0) {
LOG_ERR("Failed to read Status register"); LOG_ERR("Failed to read Status register");
return -EIO; return -EIO;
@ -131,12 +131,12 @@ static int switch_to_app_mode(struct device *i2c)
buf = CCS811_REG_APP_START; buf = CCS811_REG_APP_START;
/* Set the device to application mode */ /* Set the device to application mode */
if (i2c_write(i2c, &buf, 1, DT_AMS_CCS811_0_BASE_ADDRESS) < 0) { if (i2c_write(i2c, &buf, 1, DT_INST_0_AMS_CCS811_BASE_ADDRESS) < 0) {
LOG_ERR("Failed to set Application mode"); LOG_ERR("Failed to set Application mode");
return -EIO; return -EIO;
} }
if (i2c_reg_read_byte(i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_reg_read_byte(i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_STATUS, &status) < 0) { CCS811_REG_STATUS, &status) < 0) {
LOG_ERR("Failed to read Status register"); LOG_ERR("Failed to read Status register");
return -EIO; return -EIO;
@ -159,10 +159,10 @@ int ccs811_init(struct device *dev)
int ret; int ret;
u8_t hw_id, status; u8_t hw_id, status;
drv_data->i2c = device_get_binding(DT_AMS_CCS811_0_BUS_NAME); drv_data->i2c = device_get_binding(DT_INST_0_AMS_CCS811_BUS_NAME);
if (drv_data->i2c == NULL) { if (drv_data->i2c == NULL) {
LOG_ERR("Failed to get pointer to %s device!", LOG_ERR("Failed to get pointer to %s device!",
DT_AMS_CCS811_0_BUS_NAME); DT_INST_0_AMS_CCS811_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
@ -202,7 +202,7 @@ int ccs811_init(struct device *dev)
} }
/* Check Hardware ID */ /* Check Hardware ID */
if (i2c_reg_read_byte(drv_data->i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_reg_read_byte(drv_data->i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_HW_ID, &hw_id) < 0) { CCS811_REG_HW_ID, &hw_id) < 0) {
LOG_ERR("Failed to read Hardware ID register"); LOG_ERR("Failed to read Hardware ID register");
return -EIO; return -EIO;
@ -214,7 +214,7 @@ int ccs811_init(struct device *dev)
} }
/* Set Measurement mode for 1 second */ /* Set Measurement mode for 1 second */
if (i2c_reg_write_byte(drv_data->i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_reg_write_byte(drv_data->i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_MEAS_MODE, CCS811_REG_MEAS_MODE,
CCS811_MODE_IAQ_1SEC) < 0) { CCS811_MODE_IAQ_1SEC) < 0) {
LOG_ERR("Failed to set Measurement mode"); LOG_ERR("Failed to set Measurement mode");
@ -222,7 +222,7 @@ int ccs811_init(struct device *dev)
} }
/* Check for error */ /* Check for error */
if (i2c_reg_read_byte(drv_data->i2c, DT_AMS_CCS811_0_BASE_ADDRESS, if (i2c_reg_read_byte(drv_data->i2c, DT_INST_0_AMS_CCS811_BASE_ADDRESS,
CCS811_REG_STATUS, &status) < 0) { CCS811_REG_STATUS, &status) < 0) {
LOG_ERR("Failed to read Status register"); LOG_ERR("Failed to read Status register");
return -EIO; return -EIO;
@ -238,6 +238,6 @@ int ccs811_init(struct device *dev)
static struct ccs811_data ccs811_driver; static struct ccs811_data ccs811_driver;
DEVICE_AND_API_INIT(ccs811, DT_AMS_CCS811_0_LABEL, ccs811_init, &ccs811_driver, DEVICE_AND_API_INIT(ccs811, DT_INST_0_AMS_CCS811_LABEL, ccs811_init, &ccs811_driver,
NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&ccs811_driver_api); &ccs811_driver_api);

View file

@ -50,7 +50,7 @@ static int ens210_sample_fetch(struct device *dev, enum sensor_channel chan)
__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
for (cnt = 0; cnt <= CONFIG_ENS210_MAX_READ_RETRIES; cnt++) { for (cnt = 0; cnt <= CONFIG_ENS210_MAX_READ_RETRIES; cnt++) {
ret = i2c_burst_read(drv_data->i2c, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_burst_read(drv_data->i2c, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_T_VAL, (u8_t *)&data, sizeof(data)); ENS210_REG_T_VAL, (u8_t *)&data, sizeof(data));
if (ret < 0) { if (ret < 0) {
LOG_ERR("Failed to read data"); LOG_ERR("Failed to read data");
@ -129,7 +129,7 @@ static int ens210_sys_reset(struct device *i2c_dev)
const struct ens210_sys_ctrl sys_ctrl = {.low_power = 0, .reset = 1}; const struct ens210_sys_ctrl sys_ctrl = {.low_power = 0, .reset = 1};
int ret; int ret;
ret = i2c_reg_write_byte(i2c_dev, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_reg_write_byte(i2c_dev, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_SYS_CTRL, *(u8_t *)&sys_ctrl); ENS210_REG_SYS_CTRL, *(u8_t *)&sys_ctrl);
if (ret < 0) { if (ret < 0) {
LOG_ERR("Failed to set SYS_CTRL to 0x%x", *(u8_t *)&sys_ctrl); LOG_ERR("Failed to set SYS_CTRL to 0x%x", *(u8_t *)&sys_ctrl);
@ -142,7 +142,7 @@ static int ens210_sys_enable(struct device *i2c_dev)
const struct ens210_sys_ctrl sys_ctrl = {.low_power = 0, .reset = 0}; const struct ens210_sys_ctrl sys_ctrl = {.low_power = 0, .reset = 0};
int ret; int ret;
ret = i2c_reg_write_byte(i2c_dev, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_reg_write_byte(i2c_dev, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_SYS_CTRL, *(u8_t *)&sys_ctrl); ENS210_REG_SYS_CTRL, *(u8_t *)&sys_ctrl);
if (ret < 0) { if (ret < 0) {
LOG_ERR("Failed to set SYS_CTRL to 0x%x", *(u8_t *)&sys_ctrl); LOG_ERR("Failed to set SYS_CTRL to 0x%x", *(u8_t *)&sys_ctrl);
@ -157,7 +157,7 @@ static int ens210_wait_boot(struct device *i2c_dev)
struct ens210_sys_stat sys_stat; struct ens210_sys_stat sys_stat;
for (cnt = 0; cnt <= CONFIG_ENS210_MAX_STAT_RETRIES; cnt++) { for (cnt = 0; cnt <= CONFIG_ENS210_MAX_STAT_RETRIES; cnt++) {
ret = i2c_reg_read_byte(i2c_dev, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_reg_read_byte(i2c_dev, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_SYS_STAT, ENS210_REG_SYS_STAT,
(u8_t *)&sys_stat); (u8_t *)&sys_stat);
@ -207,10 +207,10 @@ static int ens210_init(struct device *dev)
int ret; int ret;
u16_t part_id; u16_t part_id;
drv_data->i2c = device_get_binding(DT_AMS_ENS210_0_BUS_NAME); drv_data->i2c = device_get_binding(DT_INST_0_AMS_ENS210_BUS_NAME);
if (drv_data->i2c == NULL) { if (drv_data->i2c == NULL) {
LOG_ERR("Failed to get pointer to %s device!", LOG_ERR("Failed to get pointer to %s device!",
DT_AMS_ENS210_0_BUS_NAME); DT_INST_0_AMS_ENS210_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
@ -221,7 +221,7 @@ static int ens210_init(struct device *dev)
} }
/* Check Hardware ID. This is only possible after device is ready */ /* Check Hardware ID. This is only possible after device is ready */
ret = i2c_burst_read(drv_data->i2c, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_burst_read(drv_data->i2c, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_PART_ID, (u8_t *)&part_id, ENS210_REG_PART_ID, (u8_t *)&part_id,
sizeof(part_id)); sizeof(part_id));
if (ret < 0) { if (ret < 0) {
@ -236,7 +236,7 @@ static int ens210_init(struct device *dev)
} }
/* Set continuous measurement */ /* Set continuous measurement */
ret = i2c_reg_write_byte(drv_data->i2c, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_reg_write_byte(drv_data->i2c, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_SENS_RUN, *(u8_t *)&sense_run); ENS210_REG_SENS_RUN, *(u8_t *)&sense_run);
if (ret < 0) { if (ret < 0) {
LOG_ERR("Failed to set SENS_RUN to 0x%x", LOG_ERR("Failed to set SENS_RUN to 0x%x",
@ -245,7 +245,7 @@ static int ens210_init(struct device *dev)
} }
/* Start measuring */ /* Start measuring */
ret = i2c_reg_write_byte(drv_data->i2c, DT_AMS_ENS210_0_BASE_ADDRESS, ret = i2c_reg_write_byte(drv_data->i2c, DT_INST_0_AMS_ENS210_BASE_ADDRESS,
ENS210_REG_SENS_START, *(u8_t *)&sense_start); ENS210_REG_SENS_START, *(u8_t *)&sense_start);
if (ret < 0) { if (ret < 0) {
LOG_ERR("Failed to set SENS_START to 0x%x", LOG_ERR("Failed to set SENS_START to 0x%x",
@ -257,6 +257,6 @@ static int ens210_init(struct device *dev)
static struct ens210_data ens210_driver; static struct ens210_data ens210_driver;
DEVICE_AND_API_INIT(ens210, DT_AMS_ENS210_0_LABEL, ens210_init, &ens210_driver, DEVICE_AND_API_INIT(ens210, DT_INST_0_AMS_ENS210_LABEL, ens210_init, &ens210_driver,
NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&en210_driver_api); &en210_driver_api);

View file

@ -285,25 +285,25 @@ static const struct sensor_driver_api fxas21002_driver_api = {
}; };
static const struct fxas21002_config fxas21002_config = { static const struct fxas21002_config fxas21002_config = {
.i2c_name = DT_NXP_FXAS21002_0_BUS_NAME, .i2c_name = DT_INST_0_NXP_FXAS21002_BUS_NAME,
.i2c_address = DT_NXP_FXAS21002_0_BASE_ADDRESS, .i2c_address = DT_INST_0_NXP_FXAS21002_BASE_ADDRESS,
.whoami = CONFIG_FXAS21002_WHOAMI, .whoami = CONFIG_FXAS21002_WHOAMI,
.range = CONFIG_FXAS21002_RANGE, .range = CONFIG_FXAS21002_RANGE,
.dr = CONFIG_FXAS21002_DR, .dr = CONFIG_FXAS21002_DR,
#ifdef CONFIG_FXAS21002_TRIGGER #ifdef CONFIG_FXAS21002_TRIGGER
#ifdef CONFIG_FXAS21002_DRDY_INT1 #ifdef CONFIG_FXAS21002_DRDY_INT1
.gpio_name = DT_NXP_FXAS21002_0_INT1_GPIOS_CONTROLLER, .gpio_name = DT_INST_0_NXP_FXAS21002_INT1_GPIOS_CONTROLLER,
.gpio_pin = DT_NXP_FXAS21002_0_INT1_GPIOS_PIN, .gpio_pin = DT_INST_0_NXP_FXAS21002_INT1_GPIOS_PIN,
#else #else
.gpio_name = DT_NXP_FXAS21002_0_INT2_GPIOS_CONTROLLER, .gpio_name = DT_INST_0_NXP_FXAS21002_INT2_GPIOS_CONTROLLER,
.gpio_pin = DT_NXP_FXAS21002_0_INT2_GPIOS_PIN, .gpio_pin = DT_INST_0_NXP_FXAS21002_INT2_GPIOS_PIN,
#endif #endif
#endif #endif
}; };
static struct fxas21002_data fxas21002_data; static struct fxas21002_data fxas21002_data;
DEVICE_AND_API_INIT(fxas21002, DT_NXP_FXAS21002_0_LABEL, fxas21002_init, DEVICE_AND_API_INIT(fxas21002, DT_INST_0_NXP_FXAS21002_LABEL, fxas21002_init,
&fxas21002_data, &fxas21002_config, &fxas21002_data, &fxas21002_config,
POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&fxas21002_driver_api); &fxas21002_driver_api);

View file

@ -520,11 +520,11 @@ static const struct sensor_driver_api fxos8700_driver_api = {
}; };
static const struct fxos8700_config fxos8700_config = { static const struct fxos8700_config fxos8700_config = {
.i2c_name = DT_NXP_FXOS8700_0_BUS_NAME, .i2c_name = DT_INST_0_NXP_FXOS8700_BUS_NAME,
.i2c_address = DT_NXP_FXOS8700_0_BASE_ADDRESS, .i2c_address = DT_INST_0_NXP_FXOS8700_BASE_ADDRESS,
#ifdef DT_NXP_FXOS8700_0_RESET_GPIOS_CONTROLLER #ifdef DT_INST_0_NXP_FXOS8700_RESET_GPIOS_CONTROLLER
.reset_name = DT_NXP_FXOS8700_0_RESET_GPIOS_CONTROLLER, .reset_name = DT_INST_0_NXP_FXOS8700_RESET_GPIOS_CONTROLLER,
.reset_pin = DT_NXP_FXOS8700_0_RESET_GPIOS_PIN, .reset_pin = DT_INST_0_NXP_FXOS8700_RESET_GPIOS_PIN,
#else #else
.reset_name = NULL, .reset_name = NULL,
.reset_pin = 0, .reset_pin = 0,
@ -563,11 +563,11 @@ static const struct fxos8700_config fxos8700_config = {
#endif #endif
#ifdef CONFIG_FXOS8700_TRIGGER #ifdef CONFIG_FXOS8700_TRIGGER
#ifdef CONFIG_FXOS8700_DRDY_INT1 #ifdef CONFIG_FXOS8700_DRDY_INT1
.gpio_name = DT_NXP_FXOS8700_0_INT1_GPIOS_CONTROLLER, .gpio_name = DT_INST_0_NXP_FXOS8700_INT1_GPIOS_CONTROLLER,
.gpio_pin = DT_NXP_FXOS8700_0_INT1_GPIOS_PIN, .gpio_pin = DT_INST_0_NXP_FXOS8700_INT1_GPIOS_PIN,
#else #else
.gpio_name = DT_NXP_FXOS8700_0_INT2_GPIOS_CONTROLLER, .gpio_name = DT_INST_0_NXP_FXOS8700_INT2_GPIOS_CONTROLLER,
.gpio_pin = DT_NXP_FXOS8700_0_INT2_GPIOS_PIN, .gpio_pin = DT_INST_0_NXP_FXOS8700_INT2_GPIOS_PIN,
#endif #endif
#endif #endif
#ifdef CONFIG_FXOS8700_PULSE #ifdef CONFIG_FXOS8700_PULSE
@ -583,7 +583,7 @@ static const struct fxos8700_config fxos8700_config = {
static struct fxos8700_data fxos8700_data; static struct fxos8700_data fxos8700_data;
DEVICE_AND_API_INIT(fxos8700, DT_NXP_FXOS8700_0_LABEL, fxos8700_init, DEVICE_AND_API_INIT(fxos8700, DT_INST_0_NXP_FXOS8700_LABEL, fxos8700_init,
&fxos8700_data, &fxos8700_config, &fxos8700_data, &fxos8700_config,
POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&fxos8700_driver_api); &fxos8700_driver_api);

View file

@ -66,7 +66,7 @@ static int hts221_sample_fetch(struct device *dev, enum sensor_channel chan)
__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
if (i2c_burst_read(drv_data->i2c, DT_ST_HTS221_0_BASE_ADDRESS, if (i2c_burst_read(drv_data->i2c, DT_INST_0_ST_HTS221_BASE_ADDRESS,
HTS221_REG_DATA_START | HTS221_AUTOINCREMENT_ADDR, HTS221_REG_DATA_START | HTS221_AUTOINCREMENT_ADDR,
buf, 4) < 0) { buf, 4) < 0) {
LOG_ERR("Failed to fetch data sample."); LOG_ERR("Failed to fetch data sample.");
@ -83,7 +83,7 @@ static int hts221_read_conversion_data(struct hts221_data *drv_data)
{ {
u8_t buf[16]; u8_t buf[16];
if (i2c_burst_read(drv_data->i2c, DT_ST_HTS221_0_BASE_ADDRESS, if (i2c_burst_read(drv_data->i2c, DT_INST_0_ST_HTS221_BASE_ADDRESS,
HTS221_REG_CONVERSION_START | HTS221_REG_CONVERSION_START |
HTS221_AUTOINCREMENT_ADDR, buf, 16) < 0) { HTS221_AUTOINCREMENT_ADDR, buf, 16) < 0) {
LOG_ERR("Failed to read conversion data."); LOG_ERR("Failed to read conversion data.");
@ -115,15 +115,15 @@ int hts221_init(struct device *dev)
struct hts221_data *drv_data = dev->driver_data; struct hts221_data *drv_data = dev->driver_data;
u8_t id, idx; u8_t id, idx;
drv_data->i2c = device_get_binding(DT_ST_HTS221_0_BUS_NAME); drv_data->i2c = device_get_binding(DT_INST_0_ST_HTS221_BUS_NAME);
if (drv_data->i2c == NULL) { if (drv_data->i2c == NULL) {
LOG_ERR("Could not get pointer to %s device.", LOG_ERR("Could not get pointer to %s device.",
DT_ST_HTS221_0_BUS_NAME); DT_INST_0_ST_HTS221_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
/* check chip ID */ /* check chip ID */
if (i2c_reg_read_byte(drv_data->i2c, DT_ST_HTS221_0_BASE_ADDRESS, if (i2c_reg_read_byte(drv_data->i2c, DT_INST_0_ST_HTS221_BASE_ADDRESS,
HTS221_REG_WHO_AM_I, &id) < 0) { HTS221_REG_WHO_AM_I, &id) < 0) {
LOG_ERR("Failed to read chip ID."); LOG_ERR("Failed to read chip ID.");
return -EIO; return -EIO;
@ -146,7 +146,7 @@ int hts221_init(struct device *dev)
return -EINVAL; return -EINVAL;
} }
if (i2c_reg_write_byte(drv_data->i2c, DT_ST_HTS221_0_BASE_ADDRESS, if (i2c_reg_write_byte(drv_data->i2c, DT_INST_0_ST_HTS221_BASE_ADDRESS,
HTS221_REG_CTRL1, HTS221_REG_CTRL1,
(idx + 1) << HTS221_ODR_SHIFT | HTS221_BDU_BIT | (idx + 1) << HTS221_ODR_SHIFT | HTS221_BDU_BIT |
HTS221_PD_BIT) < 0) { HTS221_PD_BIT) < 0) {
@ -177,6 +177,6 @@ int hts221_init(struct device *dev)
struct hts221_data hts221_driver; struct hts221_data hts221_driver;
DEVICE_AND_API_INIT(hts221, DT_ST_HTS221_0_LABEL, hts221_init, &hts221_driver, DEVICE_AND_API_INIT(hts221, DT_INST_0_ST_HTS221_LABEL, hts221_init, &hts221_driver,
NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&hts221_driver_api); &hts221_driver_api);

View file

@ -26,7 +26,7 @@ int hts221_trigger_set(struct device *dev,
__ASSERT_NO_MSG(trig->type == SENSOR_TRIG_DATA_READY); __ASSERT_NO_MSG(trig->type == SENSOR_TRIG_DATA_READY);
gpio_pin_disable_callback(drv_data->gpio, gpio_pin_disable_callback(drv_data->gpio,
DT_ST_HTS221_0_DRDY_GPIOS_PIN); DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN);
drv_data->data_ready_handler = handler; drv_data->data_ready_handler = handler;
if (handler == NULL) { if (handler == NULL) {
@ -36,7 +36,7 @@ int hts221_trigger_set(struct device *dev,
drv_data->data_ready_trigger = *trig; drv_data->data_ready_trigger = *trig;
gpio_pin_enable_callback(drv_data->gpio, gpio_pin_enable_callback(drv_data->gpio,
DT_ST_HTS221_0_DRDY_GPIOS_PIN); DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN);
return 0; return 0;
} }
@ -49,7 +49,7 @@ static void hts221_gpio_callback(struct device *dev,
ARG_UNUSED(pins); ARG_UNUSED(pins);
gpio_pin_disable_callback(dev, DT_ST_HTS221_0_DRDY_GPIOS_PIN); gpio_pin_disable_callback(dev, DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN);
#if defined(CONFIG_HTS221_TRIGGER_OWN_THREAD) #if defined(CONFIG_HTS221_TRIGGER_OWN_THREAD)
k_sem_give(&drv_data->gpio_sem); k_sem_give(&drv_data->gpio_sem);
@ -68,7 +68,7 @@ static void hts221_thread_cb(void *arg)
&drv_data->data_ready_trigger); &drv_data->data_ready_trigger);
} }
gpio_pin_enable_callback(drv_data->gpio, DT_ST_HTS221_0_DRDY_GPIOS_PIN); gpio_pin_enable_callback(drv_data->gpio, DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN);
} }
#ifdef CONFIG_HTS221_TRIGGER_OWN_THREAD #ifdef CONFIG_HTS221_TRIGGER_OWN_THREAD
@ -102,20 +102,20 @@ int hts221_init_interrupt(struct device *dev)
/* setup data ready gpio interrupt */ /* setup data ready gpio interrupt */
drv_data->gpio = drv_data->gpio =
device_get_binding(DT_ST_HTS221_0_DRDY_GPIOS_CONTROLLER); device_get_binding(DT_INST_0_ST_HTS221_DRDY_GPIOS_CONTROLLER);
if (drv_data->gpio == NULL) { if (drv_data->gpio == NULL) {
LOG_ERR("Cannot get pointer to %s device.", LOG_ERR("Cannot get pointer to %s device.",
DT_ST_HTS221_0_DRDY_GPIOS_CONTROLLER); DT_INST_0_ST_HTS221_DRDY_GPIOS_CONTROLLER);
return -EINVAL; return -EINVAL;
} }
gpio_pin_configure(drv_data->gpio, DT_ST_HTS221_0_DRDY_GPIOS_PIN, gpio_pin_configure(drv_data->gpio, DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE); GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
gpio_init_callback(&drv_data->gpio_cb, gpio_init_callback(&drv_data->gpio_cb,
hts221_gpio_callback, hts221_gpio_callback,
BIT(DT_ST_HTS221_0_DRDY_GPIOS_PIN)); BIT(DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN));
if (gpio_add_callback(drv_data->gpio, &drv_data->gpio_cb) < 0) { if (gpio_add_callback(drv_data->gpio, &drv_data->gpio_cb) < 0) {
LOG_ERR("Could not set gpio callback."); LOG_ERR("Could not set gpio callback.");
@ -123,7 +123,7 @@ int hts221_init_interrupt(struct device *dev)
} }
/* enable data-ready interrupt */ /* enable data-ready interrupt */
if (i2c_reg_write_byte(drv_data->i2c, DT_ST_HTS221_0_BASE_ADDRESS, if (i2c_reg_write_byte(drv_data->i2c, DT_INST_0_ST_HTS221_BASE_ADDRESS,
HTS221_REG_CTRL3, HTS221_DRDY_EN) < 0) { HTS221_REG_CTRL3, HTS221_DRDY_EN) < 0) {
LOG_ERR("Could not enable data-ready interrupt."); LOG_ERR("Could not enable data-ready interrupt.");
return -EIO; return -EIO;
@ -142,7 +142,7 @@ int hts221_init_interrupt(struct device *dev)
drv_data->dev = dev; drv_data->dev = dev;
#endif #endif
gpio_pin_enable_callback(drv_data->gpio, DT_ST_HTS221_0_DRDY_GPIOS_PIN); gpio_pin_enable_callback(drv_data->gpio, DT_INST_0_ST_HTS221_DRDY_GPIOS_PIN);
return 0; return 0;
} }

View file

@ -367,6 +367,6 @@ int lis2dh_init(struct device *dev)
static struct lis2dh_data lis2dh_driver; static struct lis2dh_data lis2dh_driver;
DEVICE_AND_API_INIT(lis2dh, DT_ST_LIS2DH_0_LABEL, lis2dh_init, &lis2dh_driver, DEVICE_AND_API_INIT(lis2dh, DT_INST_0_ST_LIS2DH_LABEL, lis2dh_init, &lis2dh_driver,
NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,
&lis2dh_driver_api); &lis2dh_driver_api);

View file

@ -15,8 +15,8 @@
#include <sensor.h> #include <sensor.h>
#include <string.h> #include <string.h>
#define LIS2DH_BUS_ADDRESS DT_ST_LIS2DH_0_BASE_ADDRESS #define LIS2DH_BUS_ADDRESS DT_INST_0_ST_LIS2DH_BASE_ADDRESS
#define LIS2DH_BUS_DEV_NAME DT_ST_LIS2DH_0_BUS_NAME #define LIS2DH_BUS_DEV_NAME DT_INST_0_ST_LIS2DH_BUS_NAME
#if defined(DT_ST_LIS2DH_0_BUS_SPI) #if defined(DT_ST_LIS2DH_0_BUS_SPI)
#include <spi.h> #include <spi.h>
@ -28,7 +28,7 @@
/* LIS2DH supports only SPI mode 0, word size 8 bits, MSB first */ /* LIS2DH supports only SPI mode 0, word size 8 bits, MSB first */
#define LIS2DH_SPI_CFG SPI_WORD_SET(8) #define LIS2DH_SPI_CFG SPI_WORD_SET(8)
#elif defined(DT_ST_LIS2DH_0_BUS_I2C) #elif defined(DT_ST_LIS2DH_BUS_I2C)
#include <i2c.h> #include <i2c.h>
#else #else
#error "define bus type (I2C/SPI)" #error "define bus type (I2C/SPI)"
@ -169,16 +169,16 @@
#define LIS2DH_DATA_OFS 0 #define LIS2DH_DATA_OFS 0
#endif #endif
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
/* INT1 and INT2 are configured */ /* INT1 and INT2 are configured */
#define DT_LIS2DH_INT1_GPIO_PIN DT_ST_LIS2DH_0_IRQ_GPIOS_PIN_0 #define DT_LIS2DH_INT1_GPIO_PIN DT_INST_0_ST_LIS2DH_IRQ_GPIOS_PIN_0
#define DT_LIS2DH_INT1_GPIO_DEV_NAME DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_0 #define DT_LIS2DH_INT1_GPIO_DEV_NAME DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_0
#define DT_LIS2DH_INT2_GPIO_PIN DT_ST_LIS2DH_0_IRQ_GPIOS_PIN_1 #define DT_LIS2DH_INT2_GPIO_PIN DT_INST_0_ST_LIS2DH_IRQ_GPIOS_PIN_1
#define DT_LIS2DH_INT2_GPIO_DEV_NAME DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 #define DT_LIS2DH_INT2_GPIO_DEV_NAME DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1
#else #else
/* INT1 only */ /* INT1 only */
#define DT_LIS2DH_INT1_GPIO_PIN DT_ST_LIS2DH_0_IRQ_GPIOS_PIN #define DT_LIS2DH_INT1_GPIO_PIN DT_INST_0_ST_LIS2DH_IRQ_GPIOS_PIN
#define DT_LIS2DH_INT1_GPIO_DEV_NAME DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER #define DT_LIS2DH_INT1_GPIO_DEV_NAME DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER
#endif #endif
union lis2dh_sample { union lis2dh_sample {
@ -244,11 +244,11 @@ static inline int lis2dh_bus_configure(struct device *dev)
} }
lis2dh->spi_cfg.operation = LIS2DH_SPI_CFG; lis2dh->spi_cfg.operation = LIS2DH_SPI_CFG;
lis2dh->spi_cfg.frequency = DT_ST_LIS2DH_0_SPI_MAX_FREQUENCY; lis2dh->spi_cfg.frequency = DT_INST_0_ST_LIS2DH_SPI_MAX_FREQUENCY;
lis2dh->spi_cfg.slave = LIS2DH_BUS_ADDRESS; lis2dh->spi_cfg.slave = LIS2DH_BUS_ADDRESS;
return 0; return 0;
#elif defined(DT_ST_LIS2DH_0_BUS_I2C) #elif defined(DT_ST_LIS2DH_BUS_I2C)
lis2dh->bus = device_get_binding(LIS2DH_BUS_DEV_NAME); lis2dh->bus = device_get_binding(LIS2DH_BUS_DEV_NAME);
if (lis2dh->bus == NULL) { if (lis2dh->bus == NULL) {
LOG_ERR("Could not get pointer to %s device", LOG_ERR("Could not get pointer to %s device",
@ -271,7 +271,7 @@ static inline int lis2dh_burst_read(struct device *dev, u8_t start_addr,
start_addr |= LIS2DH_SPI_READ_BIT | LIS2DH_SPI_AUTOINC_ADDR; start_addr |= LIS2DH_SPI_READ_BIT | LIS2DH_SPI_AUTOINC_ADDR;
return lis2dh_spi_access(lis2dh, start_addr, buf, num_bytes); return lis2dh_spi_access(lis2dh, start_addr, buf, num_bytes);
#elif defined(DT_ST_LIS2DH_0_BUS_I2C) #elif defined(DT_ST_LIS2DH_BUS_I2C)
return i2c_burst_read(lis2dh->bus, LIS2DH_BUS_ADDRESS, return i2c_burst_read(lis2dh->bus, LIS2DH_BUS_ADDRESS,
start_addr | LIS2DH_AUTOINCREMENT_ADDR, start_addr | LIS2DH_AUTOINCREMENT_ADDR,
buf, num_bytes); buf, num_bytes);
@ -289,7 +289,7 @@ static inline int lis2dh_reg_read_byte(struct device *dev, u8_t reg_addr,
reg_addr |= LIS2DH_SPI_READ_BIT; reg_addr |= LIS2DH_SPI_READ_BIT;
return lis2dh_spi_access(lis2dh, reg_addr, value, 1); return lis2dh_spi_access(lis2dh, reg_addr, value, 1);
#elif defined(DT_ST_LIS2DH_0_BUS_I2C) #elif defined(DT_ST_LIS2DH_BUS_I2C)
return i2c_reg_read_byte(lis2dh->bus, LIS2DH_BUS_ADDRESS, return i2c_reg_read_byte(lis2dh->bus, LIS2DH_BUS_ADDRESS,
reg_addr, value); reg_addr, value);
#else #else
@ -306,7 +306,7 @@ static inline int lis2dh_burst_write(struct device *dev, u8_t start_addr,
start_addr |= LIS2DH_SPI_AUTOINC_ADDR; start_addr |= LIS2DH_SPI_AUTOINC_ADDR;
return lis2dh_spi_access(lis2dh, start_addr, buf, num_bytes); return lis2dh_spi_access(lis2dh, start_addr, buf, num_bytes);
#elif defined(DT_ST_LIS2DH_0_BUS_I2C) #elif defined(DT_ST_LIS2DH_BUS_I2C)
return i2c_burst_write(lis2dh->bus, LIS2DH_BUS_ADDRESS, return i2c_burst_write(lis2dh->bus, LIS2DH_BUS_ADDRESS,
start_addr | LIS2DH_AUTOINCREMENT_ADDR, start_addr | LIS2DH_AUTOINCREMENT_ADDR,
buf, num_bytes); buf, num_bytes);
@ -324,7 +324,7 @@ static inline int lis2dh_reg_write_byte(struct device *dev, u8_t reg_addr,
reg_addr &= LIS2DH_SPI_ADDR_MASK; reg_addr &= LIS2DH_SPI_ADDR_MASK;
return lis2dh_spi_access(lis2dh, reg_addr, &value, 1); return lis2dh_spi_access(lis2dh, reg_addr, &value, 1);
#elif defined(DT_ST_LIS2DH_0_BUS_I2C) #elif defined(DT_ST_LIS2DH_BUS_I2C)
u8_t tx_buf[2] = {reg_addr, value}; u8_t tx_buf[2] = {reg_addr, value};
return i2c_write(lis2dh->bus, tx_buf, sizeof(tx_buf), return i2c_write(lis2dh->bus, tx_buf, sizeof(tx_buf),

View file

@ -91,7 +91,7 @@ static int lis2dh_start_trigger_int1(struct device *dev)
LIS2DH_EN_DRDY1_INT1, 1); LIS2DH_EN_DRDY1_INT1, 1);
} }
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
#define LIS2DH_ANYM_CFG (LIS2DH_INT_CFG_ZHIE_ZUPE | LIS2DH_INT_CFG_YHIE_YUPE |\ #define LIS2DH_ANYM_CFG (LIS2DH_INT_CFG_ZHIE_ZUPE | LIS2DH_INT_CFG_YHIE_YUPE |\
LIS2DH_INT_CFG_XHIE_XUPE) LIS2DH_INT_CFG_XHIE_XUPE)
@ -144,7 +144,7 @@ static int lis2dh_start_trigger_int2(struct device *dev)
return lis2dh_reg_write_byte(dev, LIS2DH_REG_INT2_CFG, return lis2dh_reg_write_byte(dev, LIS2DH_REG_INT2_CFG,
LIS2DH_ANYM_CFG); LIS2DH_ANYM_CFG);
} }
#endif /* DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 */ #endif /* DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1 */
int lis2dh_trigger_set(struct device *dev, int lis2dh_trigger_set(struct device *dev,
const struct sensor_trigger *trig, const struct sensor_trigger *trig,
@ -153,10 +153,10 @@ int lis2dh_trigger_set(struct device *dev,
if (trig->type == SENSOR_TRIG_DATA_READY && if (trig->type == SENSOR_TRIG_DATA_READY &&
trig->chan == SENSOR_CHAN_ACCEL_XYZ) { trig->chan == SENSOR_CHAN_ACCEL_XYZ) {
return lis2dh_trigger_drdy_set(dev, trig->chan, handler); return lis2dh_trigger_drdy_set(dev, trig->chan, handler);
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
} else if (trig->type == SENSOR_TRIG_DELTA) { } else if (trig->type == SENSOR_TRIG_DELTA) {
return lis2dh_trigger_anym_set(dev, handler); return lis2dh_trigger_anym_set(dev, handler);
#endif /* DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 */ #endif /* DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1 */
} }
return -ENOTSUP; return -ENOTSUP;
@ -230,7 +230,7 @@ static void lis2dh_gpio_int1_callback(struct device *dev,
#endif #endif
} }
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
static void lis2dh_gpio_int2_callback(struct device *dev, static void lis2dh_gpio_int2_callback(struct device *dev,
struct gpio_callback *cb, u32_t pins) struct gpio_callback *cb, u32_t pins)
{ {
@ -247,7 +247,7 @@ static void lis2dh_gpio_int2_callback(struct device *dev,
k_work_submit(&lis2dh->work); k_work_submit(&lis2dh->work);
#endif #endif
} }
#endif /* DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 */ #endif /* DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1 */
static void lis2dh_thread_cb(void *arg) static void lis2dh_thread_cb(void *arg)
{ {
@ -265,7 +265,7 @@ static void lis2dh_thread_cb(void *arg)
return; return;
} }
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
if (unlikely(atomic_test_and_clear_bit(&lis2dh->trig_flags, if (unlikely(atomic_test_and_clear_bit(&lis2dh->trig_flags,
START_TRIG_INT2))) { START_TRIG_INT2))) {
status = lis2dh_start_trigger_int2(dev); status = lis2dh_start_trigger_int2(dev);
@ -275,7 +275,7 @@ static void lis2dh_thread_cb(void *arg)
} }
return; return;
} }
#endif /* DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 */ #endif /* DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1 */
if (atomic_test_and_clear_bit(&lis2dh->trig_flags, if (atomic_test_and_clear_bit(&lis2dh->trig_flags,
TRIGGED_INT1)) { TRIGGED_INT1)) {
@ -291,7 +291,7 @@ static void lis2dh_thread_cb(void *arg)
return; return;
} }
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
if (atomic_test_and_clear_bit(&lis2dh->trig_flags, if (atomic_test_and_clear_bit(&lis2dh->trig_flags,
TRIGGED_INT2)) { TRIGGED_INT2)) {
struct sensor_trigger anym_trigger = { struct sensor_trigger anym_trigger = {
@ -317,7 +317,7 @@ static void lis2dh_thread_cb(void *arg)
return; return;
} }
#endif /* DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 */ #endif /* DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1 */
} }
#ifdef CONFIG_LIS2DH_TRIGGER_OWN_THREAD #ifdef CONFIG_LIS2DH_TRIGGER_OWN_THREAD
@ -388,7 +388,7 @@ int lis2dh_init_interrupt(struct device *dev)
LOG_INF("int1 on pin=%d cfg=0x%x", LOG_INF("int1 on pin=%d cfg=0x%x",
DT_LIS2DH_INT1_GPIO_PIN, LIS2DH_INT1_CFG); DT_LIS2DH_INT1_GPIO_PIN, LIS2DH_INT1_CFG);
#if defined(DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1) #if defined(DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1)
/* setup any motion gpio interrupt */ /* setup any motion gpio interrupt */
lis2dh->gpio_int2 = device_get_binding(DT_LIS2DH_INT2_GPIO_DEV_NAME); lis2dh->gpio_int2 = device_get_binding(DT_LIS2DH_INT2_GPIO_DEV_NAME);
if (lis2dh->gpio_int2 == NULL) { if (lis2dh->gpio_int2 == NULL) {
@ -419,7 +419,7 @@ int lis2dh_init_interrupt(struct device *dev)
LOG_INF("int2 on pin=%d cfg=0x%x", LOG_INF("int2 on pin=%d cfg=0x%x",
DT_LIS2DH_INT2_GPIO_PIN, LIS2DH_INT2_CFG); DT_LIS2DH_INT2_GPIO_PIN, LIS2DH_INT2_CFG);
#endif /* DT_ST_LIS2DH_0_IRQ_GPIOS_CONTROLLER_1 */ #endif /* DT_INST_0_ST_LIS2DH_IRQ_GPIOS_CONTROLLER_1 */
#if defined(CONFIG_LIS2DH_TRIGGER_OWN_THREAD) #if defined(CONFIG_LIS2DH_TRIGGER_OWN_THREAD)
k_sem_init(&lis2dh->gpio_sem, 0, UINT_MAX); k_sem_init(&lis2dh->gpio_sem, 0, UINT_MAX);

View file

@ -25,7 +25,7 @@ LOG_MODULE_REGISTER(LIS2DS12);
static struct lis2ds12_data lis2ds12_data; static struct lis2ds12_data lis2ds12_data;
static struct lis2ds12_config lis2ds12_config = { static struct lis2ds12_config lis2ds12_config = {
.comm_master_dev_name = DT_ST_LIS2DS12_0_BUS_NAME, .comm_master_dev_name = DT_INST_0_ST_LIS2DS12_BUS_NAME,
#if defined(DT_ST_LIS2DS12_BUS_SPI) #if defined(DT_ST_LIS2DS12_BUS_SPI)
.bus_init = lis2ds12_spi_init, .bus_init = lis2ds12_spi_init,
#elif defined(DT_ST_LIS2DS12_BUS_I2C) #elif defined(DT_ST_LIS2DS12_BUS_I2C)
@ -312,6 +312,6 @@ static int lis2ds12_init(struct device *dev)
return 0; return 0;
} }
DEVICE_AND_API_INIT(lis2ds12, DT_ST_LIS2DS12_0_LABEL, lis2ds12_init, DEVICE_AND_API_INIT(lis2ds12, DT_INST_0_ST_LIS2DS12_LABEL, lis2ds12_init,
&lis2ds12_data, &lis2ds12_config, POST_KERNEL, &lis2ds12_data, &lis2ds12_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &lis2ds12_api_funcs); CONFIG_SENSOR_INIT_PRIORITY, &lis2ds12_api_funcs);

View file

@ -16,7 +16,7 @@
#ifdef DT_ST_LIS2DS12_BUS_I2C #ifdef DT_ST_LIS2DS12_BUS_I2C
static u16_t lis2ds12_i2c_slave_addr = DT_ST_LIS2DS12_0_BASE_ADDRESS; static u16_t lis2ds12_i2c_slave_addr = DT_INST_0_ST_LIS2DS12_BASE_ADDRESS;
#define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL #define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL
LOG_MODULE_DECLARE(LIS2DS12); LOG_MODULE_DECLARE(LIS2DS12);

View file

@ -21,15 +21,15 @@
#define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL #define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL
LOG_MODULE_DECLARE(LIS2DS12); LOG_MODULE_DECLARE(LIS2DS12);
#if defined(DT_ST_LIS2DS12_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ST_LIS2DS12_CS_GPIO_CONTROLLER)
static struct spi_cs_control lis2ds12_cs_ctrl; static struct spi_cs_control lis2ds12_cs_ctrl;
#endif #endif
static struct spi_config lis2ds12_spi_conf = { static struct spi_config lis2ds12_spi_conf = {
.frequency = DT_ST_LIS2DS12_0_SPI_MAX_FREQUENCY, .frequency = DT_INST_0_ST_LIS2DS12_SPI_MAX_FREQUENCY,
.operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL | .operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL |
SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE), SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE),
.slave = DT_ST_LIS2DS12_0_BASE_ADDRESS, .slave = DT_INST_0_ST_LIS2DS12_BASE_ADDRESS,
.cs = NULL, .cs = NULL,
}; };
@ -156,23 +156,23 @@ int lis2ds12_spi_init(struct device *dev)
data->hw_tf = &lis2ds12_spi_transfer_fn; data->hw_tf = &lis2ds12_spi_transfer_fn;
#if defined(DT_ST_LIS2DS12_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ST_LIS2DS12_CS_GPIO_CONTROLLER)
/* handle SPI CS thru GPIO if it is the case */ /* handle SPI CS thru GPIO if it is the case */
lis2ds12_cs_ctrl.gpio_dev = device_get_binding( lis2ds12_cs_ctrl.gpio_dev = device_get_binding(
DT_ST_LIS2DS12_0_CS_GPIO_CONTROLLER); DT_INST_0_ST_LIS2DS12_CS_GPIO_CONTROLLER);
if (!lis2ds12_cs_ctrl.gpio_dev) { if (!lis2ds12_cs_ctrl.gpio_dev) {
LOG_ERR("Unable to get GPIO SPI CS device"); LOG_ERR("Unable to get GPIO SPI CS device");
return -ENODEV; return -ENODEV;
} }
lis2ds12_cs_ctrl.gpio_pin = DT_ST_LIS2DS12_0_CS_GPIO_PIN; lis2ds12_cs_ctrl.gpio_pin = DT_INST_0_ST_LIS2DS12_CS_GPIO_PIN;
lis2ds12_cs_ctrl.delay = 0U; lis2ds12_cs_ctrl.delay = 0U;
lis2ds12_spi_conf.cs = &lis2ds12_cs_ctrl; lis2ds12_spi_conf.cs = &lis2ds12_cs_ctrl;
LOG_DBG("SPI GPIO CS configured on %s:%u", LOG_DBG("SPI GPIO CS configured on %s:%u",
DT_ST_LIS2DS12_0_CS_GPIO_CONTROLLER, DT_INST_0_ST_LIS2DS12_CS_GPIO_CONTROLLER,
DT_ST_LIS2DS12_0_CS_GPIO_PIN); DT_INST_0_ST_LIS2DS12_CS_GPIO_PIN);
#endif #endif
return 0; return 0;

View file

@ -29,7 +29,7 @@ static void lis2ds12_gpio_callback(struct device *dev,
ARG_UNUSED(pins); ARG_UNUSED(pins);
gpio_pin_disable_callback(dev, DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN); gpio_pin_disable_callback(dev, DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN);
#if defined(CONFIG_LIS2DS12_TRIGGER_OWN_THREAD) #if defined(CONFIG_LIS2DS12_TRIGGER_OWN_THREAD)
k_sem_give(&data->trig_sem); k_sem_give(&data->trig_sem);
@ -62,7 +62,7 @@ static void lis2ds12_handle_int(void *arg)
lis2ds12_handle_drdy_int(dev); lis2ds12_handle_drdy_int(dev);
} }
gpio_pin_enable_callback(data->gpio, DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN); gpio_pin_enable_callback(data->gpio, DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN);
} }
#ifdef CONFIG_LIS2DS12_TRIGGER_OWN_THREAD #ifdef CONFIG_LIS2DS12_TRIGGER_OWN_THREAD
@ -120,20 +120,20 @@ int lis2ds12_trigger_init(struct device *dev)
struct lis2ds12_data *data = dev->driver_data; struct lis2ds12_data *data = dev->driver_data;
/* setup data ready gpio interrupt */ /* setup data ready gpio interrupt */
data->gpio = device_get_binding(DT_ST_LIS2DS12_0_IRQ_GPIOS_CONTROLLER); data->gpio = device_get_binding(DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_CONTROLLER);
if (data->gpio == NULL) { if (data->gpio == NULL) {
LOG_ERR("Cannot get pointer to %s device.", LOG_ERR("Cannot get pointer to %s device.",
DT_ST_LIS2DS12_0_IRQ_GPIOS_CONTROLLER); DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_CONTROLLER);
return -EINVAL; return -EINVAL;
} }
gpio_pin_configure(data->gpio, DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN, gpio_pin_configure(data->gpio, DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN,
GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE |
GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE); GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE);
gpio_init_callback(&data->gpio_cb, gpio_init_callback(&data->gpio_cb,
lis2ds12_gpio_callback, lis2ds12_gpio_callback,
BIT(DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN)); BIT(DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN));
if (gpio_add_callback(data->gpio, &data->gpio_cb) < 0) { if (gpio_add_callback(data->gpio, &data->gpio_cb) < 0) {
LOG_ERR("Could not set gpio callback."); LOG_ERR("Could not set gpio callback.");
@ -153,7 +153,7 @@ int lis2ds12_trigger_init(struct device *dev)
data->dev = dev; data->dev = dev;
#endif #endif
gpio_pin_enable_callback(data->gpio, DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN); gpio_pin_enable_callback(data->gpio, DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN);
return 0; return 0;
} }
@ -167,7 +167,7 @@ int lis2ds12_trigger_set(struct device *dev,
__ASSERT_NO_MSG(trig->type == SENSOR_TRIG_DATA_READY); __ASSERT_NO_MSG(trig->type == SENSOR_TRIG_DATA_READY);
gpio_pin_disable_callback(data->gpio, DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN); gpio_pin_disable_callback(data->gpio, DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN);
data->data_ready_handler = handler; data->data_ready_handler = handler;
if (handler == NULL) { if (handler == NULL) {
@ -185,7 +185,7 @@ int lis2ds12_trigger_set(struct device *dev,
data->data_ready_trigger = *trig; data->data_ready_trigger = *trig;
lis2ds12_init_interrupt(dev); lis2ds12_init_interrupt(dev);
gpio_pin_enable_callback(data->gpio, DT_ST_LIS2DS12_0_IRQ_GPIOS_PIN); gpio_pin_enable_callback(data->gpio, DT_INST_0_ST_LIS2DS12_IRQ_GPIOS_PIN);
return 0; return 0;
} }

View file

@ -346,11 +346,11 @@ static int lis2dw12_init(struct device *dev)
} }
const struct lis2dw12_device_config lis2dw12_cfg = { const struct lis2dw12_device_config lis2dw12_cfg = {
.bus_name = DT_ST_LIS2DW12_0_BUS_NAME, .bus_name = DT_INST_0_ST_LIS2DW12_BUS_NAME,
.pm = CONFIG_LIS2DW12_POWER_MODE, .pm = CONFIG_LIS2DW12_POWER_MODE,
#ifdef CONFIG_LIS2DW12_TRIGGER #ifdef CONFIG_LIS2DW12_TRIGGER
.int_gpio_port = DT_ST_LIS2DW12_0_IRQ_GPIOS_CONTROLLER, .int_gpio_port = DT_INST_0_ST_LIS2DW12_IRQ_GPIOS_CONTROLLER,
.int_gpio_pin = DT_ST_LIS2DW12_0_IRQ_GPIOS_PIN, .int_gpio_pin = DT_INST_0_ST_LIS2DW12_IRQ_GPIOS_PIN,
#if defined(CONFIG_LIS2DW12_INT_PIN_1) #if defined(CONFIG_LIS2DW12_INT_PIN_1)
.int_pin = 1, .int_pin = 1,
#elif defined(CONFIG_LIS2DW12_INT_PIN_2) #elif defined(CONFIG_LIS2DW12_INT_PIN_2)
@ -362,6 +362,6 @@ const struct lis2dw12_device_config lis2dw12_cfg = {
struct lis2dw12_data lis2dw12_data; struct lis2dw12_data lis2dw12_data;
DEVICE_AND_API_INIT(lis2dw12, DT_ST_LIS2DW12_0_LABEL, lis2dw12_init, DEVICE_AND_API_INIT(lis2dw12, DT_INST_0_ST_LIS2DW12_LABEL, lis2dw12_init,
&lis2dw12_data, &lis2dw12_cfg, POST_KERNEL, &lis2dw12_data, &lis2dw12_cfg, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &lis2dw12_driver_api); CONFIG_SENSOR_INIT_PRIORITY, &lis2dw12_driver_api);

View file

@ -203,7 +203,7 @@ struct lis2dw12_data {
struct device *dev; struct device *dev;
#endif /* CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD */ #endif /* CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD */
#endif /* CONFIG_LIS2DW12_TRIGGER */ #endif /* CONFIG_LIS2DW12_TRIGGER */
#if defined(DT_ST_LIS2DW12_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ST_LIS2DW12_CS_GPIO_CONTROLLER)
struct spi_cs_control cs_ctrl; struct spi_cs_control cs_ctrl;
#endif #endif
}; };

View file

@ -16,7 +16,7 @@
#ifdef DT_ST_LIS2DW12_BUS_I2C #ifdef DT_ST_LIS2DW12_BUS_I2C
static u16_t lis2dw12_i2c_slave_addr = DT_ST_LIS2DW12_0_BASE_ADDRESS; static u16_t lis2dw12_i2c_slave_addr = DT_INST_0_ST_LIS2DW12_BASE_ADDRESS;
#define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL #define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL
LOG_MODULE_DECLARE(LIS2DW12); LOG_MODULE_DECLARE(LIS2DW12);

View file

@ -21,10 +21,10 @@
LOG_MODULE_DECLARE(LIS2DW12); LOG_MODULE_DECLARE(LIS2DW12);
static struct spi_config lis2dw12_spi_conf = { static struct spi_config lis2dw12_spi_conf = {
.frequency = DT_ST_LIS2DW12_0_SPI_MAX_FREQUENCY, .frequency = DT_INST_0_ST_LIS2DW12_SPI_MAX_FREQUENCY,
.operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL | .operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL |
SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE), SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE),
.slave = DT_ST_LIS2DW12_0_BASE_ADDRESS, .slave = DT_INST_0_ST_LIS2DW12_BASE_ADDRESS,
.cs = NULL, .cs = NULL,
}; };
@ -151,23 +151,23 @@ int lis2dw12_spi_init(struct device *dev)
data->hw_tf = &lis2dw12_spi_transfer_fn; data->hw_tf = &lis2dw12_spi_transfer_fn;
#if defined(DT_ST_LIS2DW12_0_CS_GPIO_CONTROLLER) #if defined(DT_INST_0_ST_LIS2DW12_CS_GPIO_CONTROLLER)
/* handle SPI CS thru GPIO if it is the case */ /* handle SPI CS thru GPIO if it is the case */
data->cs_ctrl.gpio_dev = device_get_binding( data->cs_ctrl.gpio_dev = device_get_binding(
DT_ST_LIS2DW12_0_CS_GPIO_CONTROLLER); DT_INST_0_ST_LIS2DW12_CS_GPIO_CONTROLLER);
if (!data->cs_ctrl.gpio_dev) { if (!data->cs_ctrl.gpio_dev) {
LOG_ERR("Unable to get GPIO SPI CS device"); LOG_ERR("Unable to get GPIO SPI CS device");
return -ENODEV; return -ENODEV;
} }
data->cs_ctrl.gpio_pin = DT_ST_LIS2DW12_0_CS_GPIO_PIN; data->cs_ctrl.gpio_pin = DT_INST_0_ST_LIS2DW12_CS_GPIO_PIN;
data->cs_ctrl.delay = 0U; data->cs_ctrl.delay = 0U;
lis2dw12_spi_conf.cs = &data->cs_ctrl; lis2dw12_spi_conf.cs = &data->cs_ctrl;
LOG_DBG("SPI GPIO CS configured on %s:%u", LOG_DBG("SPI GPIO CS configured on %s:%u",
DT_ST_LIS2DW12_0_CS_GPIO_CONTROLLER, DT_INST_0_ST_LIS2DW12_CS_GPIO_CONTROLLER,
DT_ST_LIS2DW12_0_CS_GPIO_PIN); DT_INST_0_ST_LIS2DW12_CS_GPIO_PIN);
#endif #endif
return 0; return 0;

View file

@ -310,12 +310,12 @@ static int lis2mdl_init_interface(struct device *dev)
} }
static const struct lis2mdl_device_config lis2mdl_dev_config = { static const struct lis2mdl_device_config lis2mdl_dev_config = {
.master_dev_name = DT_ST_LIS2MDL_MAGN_0_BUS_NAME, .master_dev_name = DT_INST_0_ST_LIS2MDL_MAGN_BUS_NAME,
#ifdef CONFIG_LIS2MDL_TRIGGER #ifdef CONFIG_LIS2MDL_TRIGGER
.gpio_name = DT_ST_LIS2MDL_MAGN_0_IRQ_GPIOS_CONTROLLER, .gpio_name = DT_INST_0_ST_LIS2MDL_MAGN_IRQ_GPIOS_CONTROLLER,
.gpio_pin = DT_ST_LIS2MDL_MAGN_0_IRQ_GPIOS_PIN, .gpio_pin = DT_INST_0_ST_LIS2MDL_MAGN_IRQ_GPIOS_PIN,
#endif /* CONFIG_LIS2MDL_TRIGGER */ #endif /* CONFIG_LIS2MDL_TRIGGER */
.i2c_addr_config = DT_ST_LIS2MDL_MAGN_0_BASE_ADDRESS, .i2c_addr_config = DT_INST_0_ST_LIS2MDL_MAGN_BASE_ADDRESS,
}; };
static int lis2mdl_init(struct device *dev) static int lis2mdl_init(struct device *dev)
@ -374,6 +374,6 @@ static int lis2mdl_init(struct device *dev)
return 0; return 0;
} }
DEVICE_AND_API_INIT(lis2mdl, DT_ST_LIS2MDL_MAGN_0_LABEL, lis2mdl_init, DEVICE_AND_API_INIT(lis2mdl, DT_INST_0_ST_LIS2MDL_MAGN_LABEL, lis2mdl_init,
&lis2mdl_device_data, &lis2mdl_dev_config, POST_KERNEL, &lis2mdl_device_data, &lis2mdl_dev_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &lis2mdl_driver_api); CONFIG_SENSOR_INIT_PRIORITY, &lis2mdl_driver_api);

View file

@ -65,7 +65,7 @@ int lis3mdl_sample_fetch(struct device *dev, enum sensor_channel chan)
__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
/* fetch magnetometer sample */ /* fetch magnetometer sample */
if (i2c_burst_read(drv_data->i2c, DT_ST_LIS3MDL_MAGN_0_BASE_ADDRESS, if (i2c_burst_read(drv_data->i2c, DT_INST_0_ST_LIS3MDL_MAGN_BASE_ADDRESS,
LIS3MDL_REG_SAMPLE_START, (u8_t *)buf, 8) < 0) { LIS3MDL_REG_SAMPLE_START, (u8_t *)buf, 8) < 0) {
LOG_DBG("Failed to fetch megnetometer sample."); LOG_DBG("Failed to fetch megnetometer sample.");
return -EIO; return -EIO;
@ -76,7 +76,7 @@ int lis3mdl_sample_fetch(struct device *dev, enum sensor_channel chan)
* the same read as magnetometer data, so do another * the same read as magnetometer data, so do another
* burst read to fetch the temperature sample * burst read to fetch the temperature sample
*/ */
if (i2c_burst_read(drv_data->i2c, DT_ST_LIS3MDL_MAGN_0_BASE_ADDRESS, if (i2c_burst_read(drv_data->i2c, DT_INST_0_ST_LIS3MDL_MAGN_BASE_ADDRESS,
LIS3MDL_REG_SAMPLE_START + 6, LIS3MDL_REG_SAMPLE_START + 6,
(u8_t *)(buf + 3), 2) < 0) { (u8_t *)(buf + 3), 2) < 0) {
LOG_DBG("Failed to fetch temperature sample."); LOG_DBG("Failed to fetch temperature sample.");
@ -105,16 +105,16 @@ int lis3mdl_init(struct device *dev)
u8_t chip_cfg[6]; u8_t chip_cfg[6];
u8_t id, idx; u8_t id, idx;
drv_data->i2c = device_get_binding(DT_ST_LIS3MDL_MAGN_0_BUS_NAME); drv_data->i2c = device_get_binding(DT_INST_0_ST_LIS3MDL_MAGN_BUS_NAME);
if (drv_data->i2c == NULL) { if (drv_data->i2c == NULL) {
LOG_ERR("Could not get pointer to %s device.", LOG_ERR("Could not get pointer to %s device.",
DT_ST_LIS3MDL_MAGN_0_BUS_NAME); DT_INST_0_ST_LIS3MDL_MAGN_BUS_NAME);
return -EINVAL; return -EINVAL;
} }
/* check chip ID */ /* check chip ID */
if (i2c_reg_read_byte(drv_data->i2c, DT_ST_LIS3MDL_MAGN_0_BASE_ADDRESS, if (i2c_reg_read_byte(drv_data->i2c, DT_INST_0_ST_LIS3MDL_MAGN_BASE_ADDRESS,
LIS3MDL_REG_WHO_AM_I, &id) < 0) { LIS3MDL_REG_WHO_AM_I, &id) < 0) {
LOG_ERR("Failed to read chip ID."); LOG_ERR("Failed to read chip ID.");
return -EIO; return -EIO;
@ -148,7 +148,7 @@ int lis3mdl_init(struct device *dev)
chip_cfg[5] = LIS3MDL_BDU_EN; chip_cfg[5] = LIS3MDL_BDU_EN;
if (i2c_write(drv_data->i2c, if (i2c_write(drv_data->i2c,
chip_cfg, 6, DT_ST_LIS3MDL_MAGN_0_BASE_ADDRESS) < 0) { chip_cfg, 6, DT_INST_0_ST_LIS3MDL_MAGN_BASE_ADDRESS) < 0) {
LOG_DBG("Failed to configure chip."); LOG_DBG("Failed to configure chip.");
return -EIO; return -EIO;
} }
@ -165,6 +165,6 @@ int lis3mdl_init(struct device *dev)
struct lis3mdl_data lis3mdl_driver; struct lis3mdl_data lis3mdl_driver;
DEVICE_AND_API_INIT(lis3mdl, DT_ST_LIS3MDL_MAGN_0_LABEL, lis3mdl_init, DEVICE_AND_API_INIT(lis3mdl, DT_INST_0_ST_LIS3MDL_MAGN_LABEL, lis3mdl_init,
&lis3mdl_driver, NULL, POST_KERNEL, &lis3mdl_driver, NULL, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &lis3mdl_driver_api); CONFIG_SENSOR_INIT_PRIORITY, &lis3mdl_driver_api);

View file

@ -126,7 +126,7 @@ int lis3mdl_init_interrupt(struct device *dev)
} }
/* enable interrupt */ /* enable interrupt */
if (i2c_reg_write_byte(drv_data->i2c, DT_ST_LIS3MDL_MAGN_0_BASE_ADDRESS, if (i2c_reg_write_byte(drv_data->i2c, DT_INST_0_ST_LIS3MDL_MAGN_BASE_ADDRESS,
LIS3MDL_REG_INT_CFG, LIS3MDL_INT_XYZ_EN) < 0) { LIS3MDL_REG_INT_CFG, LIS3MDL_INT_XYZ_EN) < 0) {
LOG_DBG("Could not enable interrupt."); LOG_DBG("Could not enable interrupt.");
return -EIO; return -EIO;

View file

@ -152,12 +152,12 @@ static int lps22hb_init(struct device *dev)
} }
static const struct lps22hb_config lps22hb_config = { static const struct lps22hb_config lps22hb_config = {
.i2c_master_dev_name = DT_ST_LPS22HB_PRESS_0_BUS_NAME, .i2c_master_dev_name = DT_INST_0_ST_LPS22HB_PRESS_BUS_NAME,
.i2c_slave_addr = DT_ST_LPS22HB_PRESS_0_BASE_ADDRESS, .i2c_slave_addr = DT_INST_0_ST_LPS22HB_PRESS_BASE_ADDRESS,
}; };
static struct lps22hb_data lps22hb_data; static struct lps22hb_data lps22hb_data;
DEVICE_AND_API_INIT(lps22hb, DT_ST_LPS22HB_PRESS_0_LABEL, lps22hb_init, DEVICE_AND_API_INIT(lps22hb, DT_INST_0_ST_LPS22HB_PRESS_LABEL, lps22hb_init,
&lps22hb_data, &lps22hb_config, POST_KERNEL, &lps22hb_data, &lps22hb_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &lps22hb_api_funcs); CONFIG_SENSOR_INIT_PRIORITY, &lps22hb_api_funcs);

View file

@ -180,12 +180,12 @@ static int lps25hb_init(struct device *dev)
} }
static const struct lps25hb_config lps25hb_config = { static const struct lps25hb_config lps25hb_config = {
.i2c_master_dev_name = DT_ST_LPS25HB_PRESS_0_BUS_NAME, .i2c_master_dev_name = DT_INST_0_ST_LPS25HB_PRESS_BUS_NAME,
.i2c_slave_addr = DT_ST_LPS25HB_PRESS_0_BASE_ADDRESS, .i2c_slave_addr = DT_INST_0_ST_LPS25HB_PRESS_BASE_ADDRESS,
}; };
static struct lps25hb_data lps25hb_data; static struct lps25hb_data lps25hb_data;
DEVICE_AND_API_INIT(lps25hb, DT_ST_LPS25HB_PRESS_0_LABEL, lps25hb_init, DEVICE_AND_API_INIT(lps25hb, DT_INST_0_ST_LPS25HB_PRESS_LABEL, lps25hb_init,
&lps25hb_data, &lps25hb_config, POST_KERNEL, &lps25hb_data, &lps25hb_config, POST_KERNEL,
CONFIG_SENSOR_INIT_PRIORITY, &lps25hb_api_funcs); CONFIG_SENSOR_INIT_PRIORITY, &lps25hb_api_funcs);

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