dts: Convert from DT_<COMPAT>_<INSTANCE>_<PROP> to DT_INST...
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP> defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
01e54a5472
commit
a2693975d7
206 changed files with 1480 additions and 1479 deletions
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@ -58,53 +58,53 @@ u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
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#define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)
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/* System Clock configuration */
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_SLOW, 2, 8,
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_SLOW, 2, 8,
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"Invalid SCG slow clock divider value");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_BUS, 1, 16,
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_BUS, 1, 16,
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"Invalid SCG bus clock divider value");
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#if DT_NXP_KINETIS_SCG_0_CLK_SOURCE == KINETIS_SCG_SCLK_SRC_SPLL
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#if DT_INST_0_NXP_KINETIS_SCG_CLK_SOURCE == KINETIS_SCG_SCLK_SRC_SPLL
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/* Core divider range is 1 to 4 with SPLL as clock source */
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_CORE, 1, 4,
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_CORE, 1, 4,
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"Invalid SCG core clock divider value");
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#else
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_CORE, 1, 16,
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_CORE, 1, 16,
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"Invalid SCG core clock divider value");
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#endif
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static const scg_sys_clk_config_t scg_sys_clk_config = {
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.divSlow = TO_SYS_CLK_DIV(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_SLOW),
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.divBus = TO_SYS_CLK_DIV(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_BUS),
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.divCore = TO_SYS_CLK_DIV(DT_NXP_KINETIS_SCG_0_CLK_DIVIDER_CORE),
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.src = DT_NXP_KINETIS_SCG_0_CLK_SOURCE
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.divSlow = TO_SYS_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_SLOW),
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.divBus = TO_SYS_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_BUS),
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.divCore = TO_SYS_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_CORE),
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.src = DT_INST_0_NXP_KINETIS_SCG_CLK_SOURCE
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};
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#ifdef DT_NXP_KINETIS_SCG_0_SOSC_FREQ
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#ifdef DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ
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/* System Oscillator (SOSC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_1,
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"Invalid SCG SOSC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_2,
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"Invalid SCG SOSC divider 2 value");
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static const scg_sosc_config_t scg_sosc_config = {
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.freq = DT_NXP_KINETIS_SCG_0_SOSC_FREQ,
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.freq = DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ,
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.monitorMode = kSCG_SysOscMonitorDisable,
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SOSC_DIVIDER_2),
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.workMode = DT_NXP_KINETIS_SCG_0_SOSC_MODE
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_2),
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.workMode = DT_INST_0_NXP_KINETIS_SCG_SOSC_MODE
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};
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#endif /* DT_NXP_KINETIS_SCG_0_SOSC_FREQ */
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#endif /* DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ */
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/* Slow Internal Reference Clock (SIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_1,
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"Invalid SCG SIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_2,
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"Invalid SCG SIRC divider 2 value");
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static const scg_sirc_config_t scg_sirc_config = {
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.enableMode = kSCG_SircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SIRC_DIVIDER_2),
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#if MHZ(2) == DT_NXP_KINETIS_SCG_0_SIRC_RANGE
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_2),
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#if MHZ(2) == DT_INST_0_NXP_KINETIS_SCG_SIRC_RANGE
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.range = kSCG_SircRangeLow
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#elif MHZ(8) == DT_NXP_KINETIS_SCG_0_SIRC_RANGE
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#elif MHZ(8) == DT_INST_0_NXP_KINETIS_SCG_SIRC_RANGE
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.range = kSCG_SircRangeHigh
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#else
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#error Invalid SCG SIRC range
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@ -112,21 +112,21 @@ static const scg_sirc_config_t scg_sirc_config = {
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};
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/* Fast Internal Reference Clock (FIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_1,
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"Invalid SCG FIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_2,
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"Invalid SCG FIRC divider 2 value");
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static const scg_firc_config_t scg_firc_config = {
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.enableMode = kSCG_FircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_FIRC_DIVIDER_2),
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#if MHZ(48) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_2),
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#if MHZ(48) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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.range = kSCG_FircRange48M,
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#elif MHZ(52) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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#elif MHZ(52) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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.range = kSCG_FircRange52M,
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#elif MHZ(56) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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#elif MHZ(56) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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.range = kSCG_FircRange56M,
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#elif MHZ(60) == DT_NXP_KINETIS_SCG_0_FIRC_RANGE
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#elif MHZ(60) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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.range = kSCG_FircRange60M,
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#else
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#error Invalid SCG FIRC range
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@ -135,28 +135,28 @@ static const scg_firc_config_t scg_firc_config = {
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};
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/* System Phase-Locked Loop (SPLL) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_1,
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"Invalid SCG SPLL divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_2,
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"Invalid SCG SPLL divider 2 value");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_PRE, 1, 8,
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_PRE, 1, 8,
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"Invalid SCG SPLL pre divider value");
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ASSERT_WITHIN_RANGE(DT_NXP_KINETIS_SCG_0_SPLL_MULTIPLIER, 16, 47,
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_SPLL_MULTIPLIER, 16, 47,
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"Invalid SCG SPLL multiplier value");
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static const scg_spll_config_t scg_spll_config = {
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.enableMode = kSCG_SysPllEnable,
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.monitorMode = kSCG_SysPllMonitorDisable,
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.div1 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_2),
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#if DT_NXP_KINETIS_SCG_0_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_SOSC
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_2),
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#if DT_INST_0_NXP_KINETIS_SCG_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_SOSC
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.src = kSCG_SysPllSrcSysOsc,
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#elif DT_NXP_KINETIS_SCG_0_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_FIRC
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#elif DT_INST_0_NXP_KINETIS_SCG_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_FIRC
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.src = kSCG_SysPllSrcFirc,
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#else
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#error Invalid SCG SPLL source
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#endif
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.prediv = (DT_NXP_KINETIS_SCG_0_SPLL_DIVIDER_PRE - 1U),
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.mult = (DT_NXP_KINETIS_SCG_0_SPLL_MULTIPLIER - 16U)
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.prediv = (DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_PRE - 1U),
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.mult = (DT_INST_0_NXP_KINETIS_SCG_SPLL_MULTIPLIER - 16U)
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};
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static ALWAYS_INLINE void clk_init(void)
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@ -169,7 +169,7 @@ static ALWAYS_INLINE void clk_init(void)
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};
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scg_sys_clk_config_t current;
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#ifdef DT_NXP_KINETIS_SCG_0_SOSC_FREQ
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#ifdef DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ
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/* Optionally initialize system oscillator */
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CLOCK_InitSysOsc(&scg_sosc_config);
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CLOCK_SetXtal0Freq(scg_sosc_config.freq);
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@ -223,8 +223,8 @@ static ALWAYS_INLINE void clk_init(void)
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#ifdef CONFIG_ADC_2
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CLOCK_SetIpSrc(kCLOCK_Adc2, kCLOCK_IpSrcFircAsync);
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#endif
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#ifdef DT_NXP_KINETIS_SCG_0_CLKOUT_SOURCE
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CLOCK_SetClkOutSel(DT_NXP_KINETIS_SCG_0_CLKOUT_SOURCE);
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#ifdef DT_INST_0_NXP_KINETIS_SCG_CLKOUT_SOURCE
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CLOCK_SetClkOutSel(DT_INST_0_NXP_KINETIS_SCG_CLKOUT_SOURCE);
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#endif
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}
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