diff --git a/CODEOWNERS b/CODEOWNERS index c023de0fa02..9d08bc29197 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -30,6 +30,7 @@ /soc/nios2/ @nashif /soc/arm/ @MaureenHelm @galak @ioannisg /soc/arm/arm/mps2/ @fvincenzo +/soc/arm/aspeed/ @aspeeddylan /soc/arm/atmel_sam/common/*_sam4l_*.c @nandojve /soc/arm/atmel_sam/sam3x/ @ioannisg /soc/arm/atmel_sam/sam4e/ @nandojve @@ -436,6 +437,7 @@ /drivers/xen/ @lorc @firscity /dts/arc/ @abrodkin @ruuddw @iriszzw @evgeniy-paltsev /dts/arm/acsip/ @NorthernDean +/dts/arm/aspeed/ @aspeeddylan /dts/arm/atmel/sam4e* @nandojve /dts/arm/atmel/sam4l* @nandojve /dts/arm/atmel/samr21.dtsi @benpicco diff --git a/dts/arm/aspeed/ast10x0.dtsi b/dts/arm/aspeed/ast10x0.dtsi new file mode 100644 index 00000000000..0bfd67bd1be --- /dev/null +++ b/dts/arm/aspeed/ast10x0.dtsi @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 ASPEED Technology Inc. + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + sram0: memory@0 { + compatible = "mmio-sram"; + }; + + soc { + syscon: syscon@7e6e2000 { + reg = <0x7e6e2000 0x1000>; + }; + + uart5: serial@7e784000 { + compatible = "ns16550"; + reg = <0x7e784000 0x1000>; + interrupts = <8 0>; + status = "disabled"; + label = "UART_5"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/soc/arm/aspeed/CMakeLists.txt b/soc/arm/aspeed/CMakeLists.txt new file mode 100644 index 00000000000..fb19478ca2e --- /dev/null +++ b/soc/arm/aspeed/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +add_subdirectory(${SOC_SERIES}) + +zephyr_include_directories(.) diff --git a/soc/arm/aspeed/Kconfig b/soc/arm/aspeed/Kconfig new file mode 100644 index 00000000000..78df65d605b --- /dev/null +++ b/soc/arm/aspeed/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_FAMILY_ASPEED + select PLATFORM_SPECIFIC_INIT + bool + +if SOC_FAMILY_ASPEED + +config SOC_FAMILY + string + default "aspeed" + +source "soc/arm/aspeed/*/Kconfig.soc" + +endif # SOC_FAMILY_ASPEED diff --git a/soc/arm/aspeed/Kconfig.defconfig b/soc/arm/aspeed/Kconfig.defconfig new file mode 100644 index 00000000000..bbfbf4de751 --- /dev/null +++ b/soc/arm/aspeed/Kconfig.defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +source "soc/arm/aspeed/*/Kconfig.defconfig.series" diff --git a/soc/arm/aspeed/Kconfig.soc b/soc/arm/aspeed/Kconfig.soc new file mode 100644 index 00000000000..3bd886a676a --- /dev/null +++ b/soc/arm/aspeed/Kconfig.soc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +source "soc/arm/aspeed/*/Kconfig.series" diff --git a/soc/arm/aspeed/aspeed_util.h b/soc/arm/aspeed/aspeed_util.h new file mode 100644 index 00000000000..c2fe31252a8 --- /dev/null +++ b/soc/arm/aspeed/aspeed_util.h @@ -0,0 +1,58 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 ASPEED Technology Inc. + */ +#ifndef ZEPHYR_SOC_ARM_ASPEED_UTIL_H_ +#define ZEPHYR_SOC_ARM_ASPEED_UTIL_H_ +#include +#include +#include + +/* gcc.h doesn't define __section but checkpatch.pl will complain for this. so + * temporarily add a macro here. + */ +#ifndef __section +#define __section(x) __attribute__((__section__(x))) +#endif + +/* to make checkpatch.pl happy */ +#define ALIGNED16_SECTION(name) (aligned(16), section(name)) +#define __section_aligned16(name) __attribute__(ALIGNED16_SECTION(name)) + +/* non-cached (DMA) memory */ +#if (CONFIG_SRAM_NC_SIZE > 0) +#define NON_CACHED_BSS __section(".nocache.bss") +#define NON_CACHED_BSS_ALIGN16 __section_aligned16(".nocache.bss") +#else +#define NON_CACHED_BSS +#define NON_CACHED_BSS_ALIGN16 __aligned(16) +#endif + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#define reg_read_poll_timeout(map, reg, val, cond, sleep_ms, timeout_ms) \ + ({ \ + uint32_t __timeout_tick = Z_TIMEOUT_MS(timeout_ms).ticks; \ + uint32_t __start = sys_clock_tick_get_32(); \ + int __ret = 0; \ + for (;;) { \ + val.value = map->reg.value; \ + if (cond) { \ + break; \ + } \ + if ((sys_clock_tick_get_32() - __start) > __timeout_tick) { \ + __ret = -ETIMEDOUT; \ + break; \ + } \ + if (sleep_ms) { \ + k_msleep(sleep_ms); \ + } \ + } \ + __ret; \ + }) + +/* Common reset control device name for all ASPEED SOC family */ +#define ASPEED_RST_CTRL_NAME DT_INST_RESETS_LABEL(0) +#define DEBUG_HALT() { volatile int halt = 1; while (halt) { __asm__ volatile("nop"); } } +#endif diff --git a/soc/arm/aspeed/ast10x0/CMakeLists.txt b/soc/arm/aspeed/ast10x0/CMakeLists.txt new file mode 100644 index 00000000000..fc5628a425e --- /dev/null +++ b/soc/arm/aspeed/ast10x0/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2021 ASPEED Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m) +zephyr_linker_sources(ROM_START SORT_KEY 0x1sboot sboot.ld) +zephyr_linker_sources(RAM_SECTIONS nocache.ld) + +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/${SOC_SERIES}/tools/gen_uart_booting_image.py + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ${PROJECT_BINARY_DIR}/uart_${CONFIG_KERNEL_BIN_NAME}.bin +) diff --git a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 b/soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 new file mode 100644 index 00000000000..6e106bb2232 --- /dev/null +++ b/soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +if SOC_AST1030 + +config NUM_IRQS + default 240 + +DT_NODE_SRAM := /memory@0 + +config SRAM_NC_SIZE + default $(dt_node_reg_size_int,$(DT_NODE_SRAM),1,K) + +config SRAM_NC_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_NODE_SRAM),1) + +endif # SOC_AST1030 diff --git a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series b/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series new file mode 100644 index 00000000000..a178c45f672 --- /dev/null +++ b/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +if SOC_SERIES_AST10X0 + +source "soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast10*0" + +config SOC_SERIES + default "ast10x0" + +config ICACHE_LINE_SIZE + default 32 + +config DCACHE_LINE_SIZE + default 32 + +choice CACHE_TYPE + default HAS_EXTERNAL_CACHE +endchoice + +endif # SOC_SERIES_AST10X0 diff --git a/soc/arm/aspeed/ast10x0/Kconfig.series b/soc/arm/aspeed/ast10x0/Kconfig.series new file mode 100644 index 00000000000..ff81b600e95 --- /dev/null +++ b/soc/arm/aspeed/ast10x0/Kconfig.series @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_SERIES_AST10X0 + bool "Aspeed AST10X0 Series" + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CORTEX_M_SYSTICK + select SOC_FAMILY_ASPEED + select CACHE + select CACHE_MANAGEMENT + help + Enable support for ASPEED AST10X0 series diff --git a/soc/arm/aspeed/ast10x0/Kconfig.soc b/soc/arm/aspeed/ast10x0/Kconfig.soc new file mode 100644 index 00000000000..84436257625 --- /dev/null +++ b/soc/arm/aspeed/ast10x0/Kconfig.soc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +choice + prompt "ASPEED AST10X0 Selection" + depends on SOC_SERIES_AST10X0 + +config SOC_AST1030 + bool "AST1030" + +endchoice + +config SRAM_NC_SIZE + int "noncached SRAM Size in kB" + help + The non-cached SRAM size in kB. The default value comes from reg[1] + of /chosen/zephyr,sram in devicetree. The user should generally avoid + changing it via menuconfig or in configuration files. + +config SRAM_NC_BASE_ADDRESS + hex "noncached SRAM Base Address" + help + The non-cached SRAM base address. The default value comes from from + reg[1] of /chosen/zephyr,sram in devicetree. The user should + generally avoid changing it via menuconfig or in configuration files. diff --git a/soc/arm/aspeed/ast10x0/linker.ld b/soc/arm/aspeed/ast10x0/linker.ld new file mode 100644 index 00000000000..065c950b64b --- /dev/null +++ b/soc/arm/aspeed/ast10x0/linker.ld @@ -0,0 +1,10 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2020 Linumiz + */ +MEMORY +{ + SRAM_NC (wx) : ORIGIN = CONFIG_SRAM_NC_BASE_ADDRESS, LENGTH = CONFIG_SRAM_NC_SIZE * 1024 +} +#include diff --git a/soc/arm/aspeed/ast10x0/nocache.ld b/soc/arm/aspeed/ast10x0/nocache.ld new file mode 100644 index 00000000000..c792df5e52a --- /dev/null +++ b/soc/arm/aspeed/ast10x0/nocache.ld @@ -0,0 +1,12 @@ +/* + * Copyright (c) ASPEED Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +.bss_nc (NOLOAD) : +{ + __bss_nc_start__ = .; + *(.nocache.bss*) + . = ALIGN(4); + __bss_nc_end__ = .; +} > SRAM_NC diff --git a/soc/arm/aspeed/ast10x0/sboot.ld b/soc/arm/aspeed/ast10x0/sboot.ld new file mode 100644 index 00000000000..60df960becf --- /dev/null +++ b/soc/arm/aspeed/ast10x0/sboot.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) ASPEED Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +KEEP(*(.sboot)) diff --git a/soc/arm/aspeed/ast10x0/soc.c b/soc/arm/aspeed/ast10x0/soc.c new file mode 100644 index 00000000000..4d7fc4153ca --- /dev/null +++ b/soc/arm/aspeed/ast10x0/soc.c @@ -0,0 +1,153 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern char __bss_nc_start__[]; +extern char __bss_nc_end__[]; + +/* SCU registers */ +#define JTAG_PINMUX_REG 0x41c + +/* ASPEED System reset contrl/status register */ +#define SYS_WDT4_SW_RESET BIT(31) +#define SYS_WDT4_ARM_RESET BIT(30) +#define SYS_WDT4_FULL_RESET BIT(29) +#define SYS_WDT4_SOC_RESET BIT(28) +#define SYS_WDT3_SW_RESET BIT(27) +#define SYS_WDT3_ARM_RESET BIT(26) +#define SYS_WDT3_FULL_RESET BIT(25) +#define SYS_WDT3_SOC_RESET BIT(24) +#define SYS_WDT2_SW_RESET BIT(23) +#define SYS_WDT2_ARM_RESET BIT(22) +#define SYS_WDT2_FULL_RESET BIT(21) +#define SYS_WDT2_SOC_RESET BIT(20) +#define SYS_WDT1_SW_RESET BIT(19) +#define SYS_WDT1_ARM_RESET BIT(18) +#define SYS_WDT1_FULL_RESET BIT(17) +#define SYS_WDT1_SOC_RESET BIT(16) + +#define SYS_FLASH_ABR_RESET BIT(2) +#define SYS_EXT_RESET BIT(1) +#define SYS_PWR_RESET_FLAG BIT(0) + +#define BIT_WDT_SOC(x) SYS_WDT ## x ## _SOC_RESET +#define BIT_WDT_FULL(x) SYS_WDT ## x ## _FULL_RESET +#define BIT_WDT_ARM(x) SYS_WDT ## x ## _ARM_RESET +#define BIT_WDT_SW(x) SYS_WDT ## x ## _SW_RESET + +#define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \ + if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \ + printk("RST: WDT%d ", x); \ + if (event_log & BIT_WDT_SOC(x)) { \ + printk("SOC "); \ + sys_write32(BIT_WDT_SOC(x), event_log_reg); \ + } \ + if (event_log & BIT_WDT_FULL(x)) { \ + printk("FULL "); \ + sys_write32(BIT_WDT_FULL(x), event_log_reg); \ + } \ + if (event_log & BIT_WDT_ARM(x)) { \ + printk("ARM "); \ + sys_write32(BIT_WDT_ARM(x), event_log_reg); \ + } \ + if (event_log & BIT_WDT_SW(x)) { \ + printk("SW "); \ + sys_write32(BIT_WDT_SW(x), event_log_reg); \ + } \ + printk("\n"); \ + } \ + (void)(x) + +/* secure boot header : provide image size to bootROM for SPI boot */ +struct sb_header { + uint32_t key_location; + uint32_t enc_img_addr; + uint32_t img_size; + uint32_t sign_location; + uint32_t header_rev[2]; + uint32_t patch_location; + uint32_t checksum; +}; + +struct sb_header sbh __attribute((used, section(".sboot"))) = { + .img_size = (uint32_t)&__bss_start, +}; + +void z_arm_platform_init(void) +{ + uint32_t jtag_pinmux; + uint32_t base = DT_REG_ADDR(DT_NODELABEL(syscon)); + + /* enable JTAG pins */ + jtag_pinmux = sys_read32(base + JTAG_PINMUX_REG); + jtag_pinmux |= (0x1f << 25); + sys_write32(jtag_pinmux, base + JTAG_PINMUX_REG); + + /* clear non-cached .bss */ + if (CONFIG_SRAM_NC_SIZE > 0) { + (void)memset(__bss_nc_start__, 0, __bss_nc_end__ - __bss_nc_start__); + } +} + +void aspeed_print_abr_wdt_mode(void) +{ + /* ABR enable */ + if (sys_read32(HW_STRAP2_SCU510) & BIT(11)) { + printk("FMC ABR: Enable"); + if (sys_read32(HW_STRAP2_SCU510) & BIT(12)) + printk(", Single flash"); + else + printk(", Dual flashes"); + + printk(", Source: %s (%d)", + (sys_read32(ASPEED_FMC_WDT2_CTRL) & BIT(4)) ? "Alternate" : "Primary", + (sys_read32(HW_STRAP1_SCU500) & BIT(3)) ? 1 : 0); + + if (sys_read32(HW_STRAP2_SCU510) & GENMASK(15, 13)) { + printk(", bspi sz: %ldMB", + BIT((sys_read32(HW_STRAP2_SCU510) >> 13) & 0x7) / 2); + } + printk("\n"); + } +} + +void aspeed_print_sysrst_info(void) +{ + uint32_t rest1 = sys_read32(SYS_RESET_LOG_REG1); + uint32_t rest2 = sys_read32(SYS_RESET_LOG_REG2); + + if (rest1 & SYS_PWR_RESET_FLAG) { + printk("RST: Power On\n"); + sys_write32(rest1, SYS_RESET_LOG_REG1); + } else { + HANDLE_WDTx_RESET(4, rest1, SYS_RESET_LOG_REG1); + HANDLE_WDTx_RESET(3, rest1, SYS_RESET_LOG_REG1); + HANDLE_WDTx_RESET(2, rest1, SYS_RESET_LOG_REG1); + HANDLE_WDTx_RESET(1, rest1, SYS_RESET_LOG_REG1); + + if (rest1 & SYS_FLASH_ABR_RESET) { + printk("RST: SYS_FLASH_ABR_RESET\n"); + sys_write32(SYS_FLASH_ABR_RESET, SYS_RESET_LOG_REG1); + } + + if (rest1 & SYS_EXT_RESET) { + printk("RST: External\n"); + sys_write32(SYS_EXT_RESET, SYS_RESET_LOG_REG1); + } + } + + ARG_UNUSED(rest2); + + aspeed_print_abr_wdt_mode(); +} diff --git a/soc/arm/aspeed/ast10x0/soc.h b/soc/arm/aspeed/ast10x0/soc.h new file mode 100644 index 00000000000..f45df84c128 --- /dev/null +++ b/soc/arm/aspeed/ast10x0/soc.h @@ -0,0 +1,28 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 ASPEED Technology Inc. + */ + +#ifndef ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_ +#define ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_ +#include + +#define __VTOR_PRESENT 1U +#define __FPU_PRESENT CONFIG_CPU_HAS_FPU +#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU + +#define PHY_SRAM_ADDR 0x80000000UL +#define TO_PHY_ADDR(addr) (PHY_SRAM_ADDR + (uint32_t)(addr)) +#define TO_VIR_ADDR(addr) ((uint32_t)(addr) - PHY_SRAM_ADDR) + +#define SYS_RESET_LOG_REG1 0x7e6e2074 +#define SYS_RESET_LOG_REG2 0x7e6e2078 + +#define HW_STRAP1_SCU500 0x7e6e2500 +#define HW_STRAP2_SCU510 0x7e6e2510 +#define ASPEED_FMC_WDT2_CTRL 0x7e620064 + +void aspeed_print_sysrst_info(void); + +#endif /* ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_*/ diff --git a/soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py b/soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py new file mode 100755 index 00000000000..146e2ecaf51 --- /dev/null +++ b/soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2021 ASPEED Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +import sys + +if __name__ == "__main__": + src = sys.argv[1] + dst = sys.argv[2] + + with open(src,'rb') as r: + src_image = r.read() + + # get src size and round up to 4-byte align + src_len = len(src_image) + src_len_align = (src_len + 3) & (~3) + src_len_byte = src_len_align.to_bytes(4, byteorder='little', signed=False) + + dst_image = src_len_byte + src_image + + with open(dst, 'w+b') as w: + w.write(dst_image)