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tests/drivers/gpio: Added udoo_neo_full_m4 board to gpio_basic_api test

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Added configuration for the udoo_neo_full_m4 board and
the initialization of its GPIO test pins via IOMUX controller.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
This commit is contained in:
Stanislav Poboril 2019-10-07 13:26:06 +02:00 • committed by Carles Cufí
commit a230633d3d
3 changed files with 58 additions and 0 deletions
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1
tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.conf Normal file
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@ -0,0 +1 @@
CONFIG_GPIO_IMX_PORT_5=y

13
tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay Normal file
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@ -0,0 +1,13 @@
/*
* Copyright (c) 2019 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
resources {
compatible = "test,gpio_basic_api";
out-gpios = <&gpio5 14 0>; /* J4 pin 4 */
in-gpios = <&gpio5 15 0>; /* J4 pin 3 */
};
};

44
tests/drivers/gpio/gpio_basic_api/src/main.c
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@ -11,6 +11,8 @@
#ifdef CONFIG_BOARD_FRDM_K64F
#include <drivers/pinmux.h>
#include <fsl_port.h>
#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4)
#include "device_imx.h"
#endif
#ifdef CONFIG_BOARD_MIMXRT1050_EVK
@ -37,6 +39,48 @@ static void board_setup(void)
pinmux_pin_set(pmx, PIN_OUT, PORT_PCR_MUX(kPORT_MuxAsGpio));
pinmux_pin_set(pmx, PIN_IN, PORT_PCR_MUX(kPORT_MuxAsGpio));
#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4)
/*
* Configure pin mux.
* The following code needs to configure the same GPIOs which were
* selected as test pins in device tree.
*/
if (strcmp(DEV_NAME, "GPIO_5") != 0) {
printk("FATAL: controller set in DTS %s != controller %s\n",
DEV_NAME, "GPIO_5");
k_panic();
}
if (PIN_IN != 15) {
printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15);
k_panic();
}
if (PIN_OUT != 14) {
printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14);
k_panic();
}
/* Configure pin RGMII2_RD2 as GPIO5_IO14. */
IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 =
IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(5);
/* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 =
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(6);
/* Configure pin RGMII2_RD3 as GPIO5_IO15. */
IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 =
IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(5);
/* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 =
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(6);
#endif
#ifdef CONFIG_BOARD_MIMXRT1050_EVK