aarch64: Fix registers naming in cpu.h
The name for registers and bit-field in the cpu.h file is incoherent and messy. Refactor the whole file using the proper suffixes for bits, shifts and masks. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
Anas Nashif
parent
9023dd4633
commit
a2226f5200
12 changed files with 167 additions and 136 deletions
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@ -49,7 +49,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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__asm__ volatile("mrs %0, daif;"
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"msr daifset, %1;"
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: "=r" (key)
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: "i" (DAIFSET_IRQ)
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: "i" (DAIFSET_IRQ_BIT)
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: "memory");
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return key;
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@ -66,7 +66,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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{
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/* We only check the (I)RQ bit on the DAIF register */
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return (key & DAIF_IRQ) == 0;
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return (key & DAIF_IRQ_BIT) == 0;
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}
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#ifdef __cplusplus
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@ -9,64 +9,129 @@
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#include <sys/util.h>
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#define DAIFSET_FIQ BIT(0)
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#define DAIFSET_IRQ BIT(1)
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#define DAIFSET_ABT BIT(2)
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#define DAIFSET_DBG BIT(3)
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#define DAIFSET_FIQ_BIT BIT(0)
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#define DAIFSET_IRQ_BIT BIT(1)
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#define DAIFSET_ABT_BIT BIT(2)
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#define DAIFSET_DBG_BIT BIT(3)
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#define DAIF_FIQ BIT(6)
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#define DAIF_IRQ BIT(7)
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#define DAIF_ABT BIT(8)
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#define DAIF_DBG BIT(9)
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#define DAIF_MASK (0xf << 6)
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#define DAIFCLR_FIQ_BIT BIT(0)
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#define DAIFCLR_IRQ_BIT BIT(1)
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#define DAIFCLR_ABT_BIT BIT(2)
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#define DAIFCLR_DBG_BIT BIT(3)
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#define DAIF_FIQ_BIT BIT(6)
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#define DAIF_IRQ_BIT BIT(7)
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#define DAIF_ABT_BIT BIT(8)
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#define DAIF_DBG_BIT BIT(9)
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#define SPSR_DAIF_SHIFT (6)
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#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
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#define SPSR_MODE_EL0T (0x0)
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#define SPSR_MODE_EL1T (0x4)
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#define SPSR_MODE_EL1H (0x5)
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#define SPSR_MODE_EL2T (0x8)
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#define SPSR_MODE_EL2H (0x9)
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#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(5) | BIT(4))
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(5) | BIT(4))
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#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(5) | BIT(4))
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#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(20) | BIT(11))
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#define SCTLR_M BIT(0)
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#define SCTLR_A BIT(1)
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#define SCTLR_C BIT(2)
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#define SCTLR_SA BIT(3)
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#define SCTLR_I BIT(12)
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BIT(22) | BIT(20) | BIT(11))
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#define SCTLR_M_BIT BIT(0)
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#define SCTLR_A_BIT BIT(1)
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#define SCTLR_C_BIT BIT(2)
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#define SCTLR_SA_BIT BIT(3)
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#define SCTLR_I_BIT BIT(12)
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#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
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#define SCR_EL3_NS BIT(0)
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#define SCR_EL3_IRQ BIT(1)
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#define SCR_EL3_FIQ BIT(2)
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#define SCR_EL3_EA BIT(3)
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#define SCR_EL3_RW BIT(10)
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#define SCR_NS_BIT BIT(0)
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#define SCR_IRQ_BIT BIT(1)
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#define SCR_FIQ_BIT BIT(2)
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#define SCR_EA_BIT BIT(3)
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#define SCR_SMD_BIT BIT(7)
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#define SCR_HCE_BIT BIT(8)
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#define SCR_RW_BIT BIT(10)
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#define SCR_ST_BIT BIT(11)
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#define SCR_RES1 (BIT(4) | BIT(5))
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/* MPIDR */
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#define MPIDR_AFFLVL_MASK (0xff)
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#define MPIDR_AFF0_SHIFT (0)
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#define MPIDR_AFF1_SHIFT (8)
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#define MPIDR_AFF2_SHIFT (16)
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#define MPIDR_AFF3_SHIFT (32)
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#define MPIDR_AFFLVL(mpidr, aff_level) \
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(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
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#define GET_MPIDR() read_sysreg(mpidr_el1)
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#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
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#define MODE_EL_SHIFT (0x2)
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#define MODE_EL_MASK (0x3)
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#define MODE_EL3 (0x3)
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#define MODE_EL2 (0x2)
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#define MODE_EL1 (0x1)
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#define MODE_EL0 (0x0)
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#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
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#define ESR_EC_SHIFT (26)
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#define ESR_EC_MASK BIT_MASK(6)
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#define ESR_ISS_SHIFT (0)
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#define ESR_ISS_MASK BIT_MASK(25)
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#define ESR_IL_SHIFT (25)
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#define ESR_IL_MASK BIT_MASK(1)
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#define GET_ESR_EC(esr) (((esr) >> ESR_EC_SHIFT) & ESR_EC_MASK)
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#define GET_ESR_IL(esr) (((esr) >> ESR_IL_SHIFT) & ESR_IL_MASK)
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#define GET_ESR_ISS(esr) (((esr) >> ESR_ISS_SHIFT) & ESR_ISS_MASK)
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#define CNTV_CTL_ENABLE_BIT BIT(0)
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#define CNTV_CTL_IMASK_BIT BIT(1)
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#define ID_AA64PFR0_EL0_SHIFT (0)
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#define ID_AA64PFR0_EL1_SHIFT (4)
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#define ID_AA64PFR0_EL2_SHIFT (8)
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#define ID_AA64PFR0_EL3_SHIFT (12)
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#define ID_AA64PFR0_ELX_MASK (0xf)
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#define ID_AA64PFR0_SEL2_SHIFT (36)
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#define ID_AA64PFR0_SEL2_MASK (0xf)
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/*
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* TODO: ACTLR is of class implementation defined. All core implementations
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* in armv8a have the same implementation so far w.r.t few controls.
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* When there will be differences we have to create core specific headers.
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*/
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#define ACTLR_EL3_CPUACTLR BIT(0)
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#define ACTLR_EL3_CPUECTLR BIT(1)
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#define ACTLR_EL3_L2CTLR BIT(4)
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#define ACTLR_EL3_L2ECTLR BIT(5)
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#define ACTLR_EL3_L2ACTLR BIT(6)
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#define ACTLR_EL3_CPUACTLR_BIT BIT(0)
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#define ACTLR_EL3_CPUECTLR_BIT BIT(1)
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#define ACTLR_EL3_L2CTLR_BIT BIT(4)
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#define ACTLR_EL3_L2ECTLR_BIT BIT(5)
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#define ACTLR_EL3_L2ACTLR_BIT BIT(6)
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#define CPTR_EL3_RES_VAL (0x0)
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#define CPTR_EL3_EZ BIT(8)
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#define CPTR_EL3_TFP BIT(9)
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#define CPTR_EL3_TTA BIT(20)
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#define CPTR_EL3_TCPAC BIT(31)
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#define CPTR_EZ_BIT BIT(8)
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#define CPTR_TFP_BIT BIT(10)
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#define CPTR_TTA_BIT BIT(20)
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#define CPTR_TCPAC_BIT BIT(31)
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#define HCR_EL2_FMO BIT(3)
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#define HCR_EL2_IMO BIT(4)
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#define HCR_EL2_AMO BIT(5)
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#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
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#define SPSR_EL3_h BIT(0)
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#define SPSR_EL3_TO_EL1 (0x2 << 1)
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#define HCR_FMO_BIT BIT(3)
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#define HCR_IMO_BIT BIT(4)
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#define HCR_AMO_BIT BIT(5)
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#define HCR_RW_BIT BIT(31)
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/* System register interface to GICv3 */
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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@ -89,23 +154,22 @@
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#define ICC_SGI0R_EL1 S3_0_C12_C11_7
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/* register constants */
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#define ICC_SRE_ELx_SRE BIT(0)
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#define ICC_SRE_ELx_DFB BIT(1)
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#define ICC_SRE_ELx_DIB BIT(2)
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#define ICC_SRE_EL3_EN BIT(3)
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#define ICC_SRE_ELx_SRE_BIT BIT(0)
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#define ICC_SRE_ELx_DFB_BIT BIT(1)
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#define ICC_SRE_ELx_DIB_BIT BIT(2)
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#define ICC_SRE_EL3_EN_BIT BIT(3)
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/* ICC SGI macros */
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#define SGIR_TGT_MASK 0xffff
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#define SGIR_AFF1_SHIFT 16
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#define SGIR_INTID_SHIFT 24
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#define SGIR_INTID_MASK 0xf
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#define SGIR_AFF2_SHIFT 32
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#define SGIR_IRM_SHIFT 40
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#define SGIR_IRM_MASK 0x1
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#define SGIR_AFF3_SHIFT 48
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#define SGIR_AFF_MASK 0xf
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#define SGIR_IRM_TO_AFF 0
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#define SGIR_TGT_MASK (0xffff)
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#define SGIR_AFF1_SHIFT (16)
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#define SGIR_AFF2_SHIFT (32)
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#define SGIR_AFF3_SHIFT (48)
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#define SGIR_AFF_MASK (0xf)
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#define SGIR_INTID_SHIFT (24)
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#define SGIR_INTID_MASK (0xf)
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#define SGIR_IRM_SHIFT (40)
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#define SGIR_IRM_MASK (0x1)
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#define SGIR_IRM_TO_AFF (0)
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#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
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((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
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@ -119,26 +183,26 @@
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#if defined(CONFIG_CPU_CORTEX_A72)
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#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT 5
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT 9
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 2
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK 7
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#define CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE 1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 2
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK 7
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#define CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE 1
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT (0)
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#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT (5)
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT (6)
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#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT (9)
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES (2)
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK (0x7)
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#define CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE (1)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES (1)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES (2)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK (0x7)
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#define CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE (1)
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#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT BIT(6)
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#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (1 << 6)
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#endif /* CONFIG_CPU_CORTEX_A72 */
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#ifndef _ASMLANGUAGE
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/* Core sysreg macros */
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#define read_sysreg(reg) ({ \
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uint64_t val; \
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@ -152,31 +216,4 @@
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#endif /* !_ASMLANGUAGE */
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#define MODE_EL_SHIFT (0x2)
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#define MODE_EL_MASK (0x3)
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#define MODE_EL3 (0x3)
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#define MODE_EL2 (0x2)
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#define MODE_EL1 (0x1)
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#define MODE_EL0 (0x0)
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#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
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#define ESR_EC(esr) (((esr) >> 26) & BIT_MASK(6))
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#define ESR_IL(esr) (((esr) >> 25) & BIT_MASK(1))
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#define ESR_ISS(esr) ((esr) & BIT_MASK(25))
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/* mpidr */
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#define MPIDR_AFFLVL_MASK 0xff
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#define MPIDR_AFF0_SHIFT 0
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#define MPIDR_AFF1_SHIFT 8
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#define MPIDR_AFF2_SHIFT 16
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#define MPIDR_AFF3_SHIFT 32
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#define MPIDR_AFFLVL(mpidr, aff_level) \
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(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
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#define GET_MPIDR() read_sysreg(mpidr_el1)
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#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_ */
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@ -20,9 +20,6 @@ extern "C" {
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#define ARM_ARCH_TIMER_PRIO ARM_TIMER_VIRTUAL_PRIO
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#define ARM_ARCH_TIMER_FLAGS ARM_TIMER_VIRTUAL_FLAGS
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#define CNTV_CTL_ENABLE ((1) << 0)
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#define CNTV_CTL_IMASK ((1) << 1)
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static ALWAYS_INLINE void arm_arch_timer_init(void)
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{
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}
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@ -41,9 +38,9 @@ static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
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: "=r" (cntv_ctl) : : "memory");
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if (enable) {
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cntv_ctl |= CNTV_CTL_ENABLE;
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cntv_ctl |= CNTV_CTL_ENABLE_BIT;
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} else {
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cntv_ctl &= ~CNTV_CTL_ENABLE;
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cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
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}
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__asm__ volatile("msr cntv_ctl_el0, %0\n\t"
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@ -58,9 +55,9 @@ static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
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: "=r" (cntv_ctl) : : "memory");
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if (mask) {
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cntv_ctl |= CNTV_CTL_IMASK;
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cntv_ctl |= CNTV_CTL_IMASK_BIT;
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} else {
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cntv_ctl &= ~CNTV_CTL_IMASK;
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cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
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}
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__asm__ volatile("msr cntv_ctl_el0, %0\n\t"
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