zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
ee6fa31af6
commit
a1b77fd589
2364 changed files with 32505 additions and 32505 deletions
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@ -79,8 +79,8 @@ int disk_access_status(const char *pdrv)
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return rc;
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}
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int disk_access_read(const char *pdrv, u8_t *data_buf,
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u32_t start_sector, u32_t num_sector)
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int disk_access_read(const char *pdrv, uint8_t *data_buf,
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uint32_t start_sector, uint32_t num_sector)
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{
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struct disk_info *disk = disk_access_get_di(pdrv);
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int rc = -EINVAL;
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@ -93,8 +93,8 @@ int disk_access_read(const char *pdrv, u8_t *data_buf,
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return rc;
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}
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int disk_access_write(const char *pdrv, const u8_t *data_buf,
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u32_t start_sector, u32_t num_sector)
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int disk_access_write(const char *pdrv, const uint8_t *data_buf,
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uint32_t start_sector, uint32_t num_sector)
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{
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struct disk_info *disk = disk_access_get_di(pdrv);
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int rc = -EINVAL;
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@ -107,7 +107,7 @@ int disk_access_write(const char *pdrv, const u8_t *data_buf,
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return rc;
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}
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int disk_access_ioctl(const char *pdrv, u8_t cmd, void *buf)
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int disk_access_ioctl(const char *pdrv, uint8_t cmd, void *buf)
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{
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struct disk_info *disk = disk_access_get_di(pdrv);
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int rc = -EINVAL;
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@ -19,8 +19,8 @@
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static struct device *flash_dev;
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/* flash read-copy-erase-write operation */
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static u8_t __aligned(4) read_copy_buf[CONFIG_DISK_ERASE_BLOCK_SIZE];
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static u8_t *fs_buff = read_copy_buf;
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static uint8_t __aligned(4) read_copy_buf[CONFIG_DISK_ERASE_BLOCK_SIZE];
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static uint8_t *fs_buff = read_copy_buf;
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/* calculate number of blocks required for a given size */
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#define GET_NUM_BLOCK(total_size, block_size) \
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@ -29,7 +29,7 @@ static u8_t *fs_buff = read_copy_buf;
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#define GET_SIZE_TO_BOUNDARY(start, block_size) \
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(block_size - (start & (block_size - 1)))
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static off_t lba_to_address(u32_t sector_num)
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static off_t lba_to_address(uint32_t sector_num)
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{
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off_t flash_addr;
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@ -64,13 +64,13 @@ static int disk_flash_access_init(struct disk_info *disk)
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return 0;
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}
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static int disk_flash_access_read(struct disk_info *disk, u8_t *buff,
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u32_t start_sector, u32_t sector_count)
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static int disk_flash_access_read(struct disk_info *disk, uint8_t *buff,
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uint32_t start_sector, uint32_t sector_count)
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{
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off_t fl_addr;
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u32_t remaining;
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u32_t len;
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u32_t num_read;
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uint32_t remaining;
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uint32_t len;
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uint32_t num_read;
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fl_addr = lba_to_address(start_sector);
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remaining = (sector_count * SECTOR_SIZE);
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@ -78,7 +78,7 @@ static int disk_flash_access_read(struct disk_info *disk, u8_t *buff,
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num_read = GET_NUM_BLOCK(remaining, CONFIG_DISK_FLASH_MAX_RW_SIZE);
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for (u32_t i = 0; i < num_read; i++) {
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for (uint32_t i = 0; i < num_read; i++) {
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if (remaining < CONFIG_DISK_FLASH_MAX_RW_SIZE) {
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len = remaining;
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}
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@ -96,13 +96,13 @@ static int disk_flash_access_read(struct disk_info *disk, u8_t *buff,
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}
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/* This performs read-copy into an output buffer */
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static int read_copy_flash_block(off_t start_addr, u32_t size,
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static int read_copy_flash_block(off_t start_addr, uint32_t size,
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const void *src_buff,
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u8_t *dest_buff)
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uint8_t *dest_buff)
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{
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off_t fl_addr;
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u32_t num_read;
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u32_t offset = 0U;
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uint32_t num_read;
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uint32_t offset = 0U;
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/* adjust offset if starting address is not erase-aligned address */
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if (start_addr & (CONFIG_DISK_FLASH_ERASE_ALIGNMENT - 1)) {
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@ -116,7 +116,7 @@ static int read_copy_flash_block(off_t start_addr, u32_t size,
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CONFIG_DISK_FLASH_MAX_RW_SIZE);
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/* read one block from flash */
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for (u32_t i = 0; i < num_read; i++) {
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for (uint32_t i = 0; i < num_read; i++) {
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int rc;
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rc = flash_read(flash_dev,
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@ -137,11 +137,11 @@ static int read_copy_flash_block(off_t start_addr, u32_t size,
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/* input size is either less or equal to a block size,
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* CONFIG_DISK_ERASE_BLOCK_SIZE.
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*/
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static int update_flash_block(off_t start_addr, u32_t size, const void *buff)
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static int update_flash_block(off_t start_addr, uint32_t size, const void *buff)
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{
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off_t fl_addr;
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u8_t *src = (u8_t *)buff;
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u32_t num_write;
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uint8_t *src = (uint8_t *)buff;
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uint32_t num_write;
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/* if size is a partial block, perform read-copy with user data */
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if (size < CONFIG_DISK_ERASE_BLOCK_SIZE) {
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@ -153,7 +153,7 @@ static int update_flash_block(off_t start_addr, u32_t size, const void *buff)
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}
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/* now use the local buffer as the source */
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src = (u8_t *)fs_buff;
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src = (uint8_t *)fs_buff;
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}
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/* always align starting address for flash write operation */
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@ -170,7 +170,7 @@ static int update_flash_block(off_t start_addr, u32_t size, const void *buff)
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num_write = GET_NUM_BLOCK(CONFIG_DISK_ERASE_BLOCK_SIZE,
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CONFIG_DISK_FLASH_MAX_RW_SIZE);
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for (u32_t i = 0; i < num_write; i++) {
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for (uint32_t i = 0; i < num_write; i++) {
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/* flash_write reenabled write-protection so disable it again */
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flash_write_protection_set(flash_dev, false);
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@ -186,12 +186,12 @@ static int update_flash_block(off_t start_addr, u32_t size, const void *buff)
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return 0;
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}
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static int disk_flash_access_write(struct disk_info *disk, const u8_t *buff,
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u32_t start_sector, u32_t sector_count)
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static int disk_flash_access_write(struct disk_info *disk, const uint8_t *buff,
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uint32_t start_sector, uint32_t sector_count)
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{
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off_t fl_addr;
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u32_t remaining;
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u32_t size;
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uint32_t remaining;
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uint32_t size;
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fl_addr = lba_to_address(start_sector);
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remaining = (sector_count * SECTOR_SIZE);
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@ -255,19 +255,19 @@ static int disk_flash_access_write(struct disk_info *disk, const u8_t *buff,
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return 0;
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}
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static int disk_flash_access_ioctl(struct disk_info *disk, u8_t cmd, void *buff)
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static int disk_flash_access_ioctl(struct disk_info *disk, uint8_t cmd, void *buff)
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{
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switch (cmd) {
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case DISK_IOCTL_CTRL_SYNC:
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return 0;
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case DISK_IOCTL_GET_SECTOR_COUNT:
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*(u32_t *)buff = CONFIG_DISK_VOLUME_SIZE / SECTOR_SIZE;
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*(uint32_t *)buff = CONFIG_DISK_VOLUME_SIZE / SECTOR_SIZE;
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return 0;
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case DISK_IOCTL_GET_SECTOR_SIZE:
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*(u32_t *) buff = SECTOR_SIZE;
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*(uint32_t *) buff = SECTOR_SIZE;
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return 0;
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case DISK_IOCTL_GET_ERASE_BLOCK_SZ: /* in sectors */
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*(u32_t *)buff = CONFIG_DISK_ERASE_BLOCK_SIZE / SECTOR_SIZE;
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*(uint32_t *)buff = CONFIG_DISK_ERASE_BLOCK_SIZE / SECTOR_SIZE;
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return 0;
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default:
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break;
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@ -24,10 +24,10 @@
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* target's RAM limits).
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*/
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#define RAMDISK_VOLUME_SIZE (CONFIG_DISK_RAM_VOLUME_SIZE * 1024)
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static u8_t ramdisk_buf[RAMDISK_VOLUME_SIZE];
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static uint8_t ramdisk_buf[RAMDISK_VOLUME_SIZE];
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#endif
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static void *lba_to_address(u32_t lba)
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static void *lba_to_address(uint32_t lba)
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{
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__ASSERT(((lba * RAMDISK_SECTOR_SIZE) < RAMDISK_VOLUME_SIZE),
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"FS bound error");
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@ -45,35 +45,35 @@ static int disk_ram_access_init(struct disk_info *disk)
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return 0;
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}
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static int disk_ram_access_read(struct disk_info *disk, u8_t *buff,
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u32_t sector, u32_t count)
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static int disk_ram_access_read(struct disk_info *disk, uint8_t *buff,
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uint32_t sector, uint32_t count)
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{
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memcpy(buff, lba_to_address(sector), count * RAMDISK_SECTOR_SIZE);
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return 0;
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}
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static int disk_ram_access_write(struct disk_info *disk, const u8_t *buff,
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u32_t sector, u32_t count)
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static int disk_ram_access_write(struct disk_info *disk, const uint8_t *buff,
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uint32_t sector, uint32_t count)
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{
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memcpy(lba_to_address(sector), buff, count * RAMDISK_SECTOR_SIZE);
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return 0;
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}
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static int disk_ram_access_ioctl(struct disk_info *disk, u8_t cmd, void *buff)
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static int disk_ram_access_ioctl(struct disk_info *disk, uint8_t cmd, void *buff)
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{
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switch (cmd) {
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case DISK_IOCTL_CTRL_SYNC:
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break;
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case DISK_IOCTL_GET_SECTOR_COUNT:
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*(u32_t *)buff = RAMDISK_VOLUME_SIZE / RAMDISK_SECTOR_SIZE;
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*(uint32_t *)buff = RAMDISK_VOLUME_SIZE / RAMDISK_SECTOR_SIZE;
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break;
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case DISK_IOCTL_GET_SECTOR_SIZE:
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*(u32_t *)buff = RAMDISK_SECTOR_SIZE;
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*(uint32_t *)buff = RAMDISK_SECTOR_SIZE;
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break;
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case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
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*(u32_t *)buff = 1U;
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*(uint32_t *)buff = 1U;
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break;
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default:
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return -EINVAL;
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@ -224,76 +224,76 @@ enum sd_ocr_flag {
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#define SD_PRODUCT_NAME_BYTES (5U)
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struct sd_cid {
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u8_t manufacturer;
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uint8_t manufacturer;
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/*!< Manufacturer ID [127:120] */
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u16_t application;
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uint16_t application;
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/*!< OEM/Application ID [119:104] */
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u8_t name[SD_PRODUCT_NAME_BYTES];
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uint8_t name[SD_PRODUCT_NAME_BYTES];
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/*!< Product name [103:64] */
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u8_t version;
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uint8_t version;
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/*!< Product revision [63:56] */
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u32_t ser_num;
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uint32_t ser_num;
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/*!< Product serial number [55:24] */
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u16_t date;
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uint16_t date;
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/*!< Manufacturing date [19:8] */
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};
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struct sd_csd {
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u8_t csd_structure;
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uint8_t csd_structure;
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/*!< CSD structure [127:126] */
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u8_t read_time1;
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uint8_t read_time1;
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/*!< Data read access-time-1 [119:112] */
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u8_t read_time2;
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uint8_t read_time2;
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/*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */
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u8_t xfer_rate;
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uint8_t xfer_rate;
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/*!< Maximum data transfer rate [103:96] */
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u16_t cmd_class;
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uint16_t cmd_class;
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/*!< Card command classes [95:84] */
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u8_t read_blk_len;
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uint8_t read_blk_len;
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/*!< Maximum read data block length [83:80] */
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u16_t flags;
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uint16_t flags;
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/*!< Flags in _sd_csd_flag */
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u32_t device_size;
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uint32_t device_size;
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/*!< Device size [73:62] */
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u8_t read_current_min;
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uint8_t read_current_min;
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/*!< Maximum read current at VDD min [61:59] */
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u8_t read_current_max;
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uint8_t read_current_max;
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/*!< Maximum read current at VDD max [58:56] */
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u8_t write_current_min;
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uint8_t write_current_min;
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/*!< Maximum write current at VDD min [55:53] */
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u8_t write_current_max;
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uint8_t write_current_max;
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/*!< Maximum write current at VDD max [52:50] */
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u8_t dev_size_mul;
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uint8_t dev_size_mul;
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/*!< Device size multiplier [49:47] */
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u8_t erase_size;
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uint8_t erase_size;
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/*!< Erase sector size [45:39] */
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u8_t write_prtect_size;
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uint8_t write_prtect_size;
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/*!< Write protect group size [38:32] */
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u8_t write_speed_factor;
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uint8_t write_speed_factor;
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/*!< Write speed factor [28:26] */
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u8_t write_blk_len;
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uint8_t write_blk_len;
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/*!< Maximum write data block length [25:22] */
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u8_t file_fmt;
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uint8_t file_fmt;
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/*!< File format [11:10] */
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};
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struct sd_scr {
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u8_t scr_structure;
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uint8_t scr_structure;
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/*!< SCR Structure [63:60] */
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u8_t sd_spec;
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uint8_t sd_spec;
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/*!< SD memory card specification version [59:56] */
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u16_t flags;
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uint16_t flags;
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/*!< SCR flags in _sd_scr_flag */
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u8_t sd_sec;
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uint8_t sd_sec;
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/*!< Security specification supported [54:52] */
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u8_t sd_width;
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uint8_t sd_width;
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/*!< Data bus widths supported [51:48] */
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u8_t sd_ext_sec;
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uint8_t sd_ext_sec;
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/*!< Extended security support [46:43] */
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u8_t cmd_support;
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uint8_t cmd_support;
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/*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/
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u32_t rsvd;
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uint32_t rsvd;
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/*!< reserved for manufacturer usage [31:0] */
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};
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@ -336,10 +336,10 @@ enum sd_voltage {
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#define SDMMC_DEFAULT_BLOCK_SIZE (512U)
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struct sd_data_op {
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u32_t start_block;
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u32_t block_size;
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u32_t block_count;
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u32_t *buf;
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uint32_t start_block;
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uint32_t block_size;
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uint32_t block_count;
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uint32_t *buf;
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};
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enum sd_switch_arg {
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@ -436,20 +436,20 @@ enum sd_command_class {
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};
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struct sdhc_retry {
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u32_t end;
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s16_t tries;
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u16_t sleep;
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uint32_t end;
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int16_t tries;
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uint16_t sleep;
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};
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struct sdhc_flag_map {
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u8_t mask;
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u8_t err;
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uint8_t mask;
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uint8_t err;
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};
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/* The SD protocol requires sending ones while reading but Zephyr
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* defaults to writing zeros.
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*/
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static const u8_t sdhc_ones[] = {
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static const uint8_t sdhc_ones[] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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@ -550,8 +550,8 @@ static inline int sdhc_map_data_status(int status)
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}
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/* Initialises a retry helper */
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static inline void sdhc_retry_init(struct sdhc_retry *retry, u32_t timeout,
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u16_t sleep)
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static inline void sdhc_retry_init(struct sdhc_retry *retry, uint32_t timeout,
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uint16_t sleep)
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{
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retry->end = k_uptime_get_32() + timeout;
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retry->tries = 0;
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@ -563,7 +563,7 @@ static inline void sdhc_retry_init(struct sdhc_retry *retry, u32_t timeout,
|
|||
*/
|
||||
static inline bool sdhc_retry_ok(struct sdhc_retry *retry)
|
||||
{
|
||||
s32_t remain = retry->end - k_uptime_get_32();
|
||||
int32_t remain = retry->end - k_uptime_get_32();
|
||||
|
||||
if (retry->tries < SDHC_MIN_TRIES) {
|
||||
retry->tries++;
|
||||
|
|
@ -588,21 +588,21 @@ static inline bool sdhc_retry_ok(struct sdhc_retry *retry)
|
|||
}
|
||||
|
||||
static inline void sdhc_decode_csd(struct sd_csd *csd,
|
||||
u32_t *raw_csd, u32_t *blk_cout, u32_t *blk_size)
|
||||
uint32_t *raw_csd, uint32_t *blk_cout, uint32_t *blk_size)
|
||||
{
|
||||
u32_t tmp_blk_cout, tmp_blk_size;
|
||||
uint32_t tmp_blk_cout, tmp_blk_size;
|
||||
|
||||
csd->csd_structure = (u8_t)((raw_csd[3U] &
|
||||
csd->csd_structure = (uint8_t)((raw_csd[3U] &
|
||||
0xC0000000U) >> 30U);
|
||||
csd->read_time1 = (u8_t)((raw_csd[3U] &
|
||||
csd->read_time1 = (uint8_t)((raw_csd[3U] &
|
||||
0xFF0000U) >> 16U);
|
||||
csd->read_time2 = (u8_t)((raw_csd[3U] &
|
||||
csd->read_time2 = (uint8_t)((raw_csd[3U] &
|
||||
0xFF00U) >> 8U);
|
||||
csd->xfer_rate = (u8_t)(raw_csd[3U] &
|
||||
csd->xfer_rate = (uint8_t)(raw_csd[3U] &
|
||||
0xFFU);
|
||||
csd->cmd_class = (u16_t)((raw_csd[2U] &
|
||||
csd->cmd_class = (uint16_t)((raw_csd[2U] &
|
||||
0xFFF00000U) >> 20U);
|
||||
csd->read_blk_len = (u8_t)((raw_csd[2U] &
|
||||
csd->read_blk_len = (uint8_t)((raw_csd[2U] &
|
||||
0xF0000U) >> 16U);
|
||||
if (raw_csd[2U] & 0x8000U)
|
||||
csd->flags |= SD_CSD_READ_BLK_PARTIAL_FLAG;
|
||||
|
|
@ -615,19 +615,19 @@ static inline void sdhc_decode_csd(struct sd_csd *csd,
|
|||
|
||||
switch (csd->csd_structure) {
|
||||
case 0:
|
||||
csd->device_size = (u32_t)((raw_csd[2U] &
|
||||
csd->device_size = (uint32_t)((raw_csd[2U] &
|
||||
0x3FFU) << 2U);
|
||||
csd->device_size |= (u32_t)((raw_csd[1U] &
|
||||
csd->device_size |= (uint32_t)((raw_csd[1U] &
|
||||
0xC0000000U) >> 30U);
|
||||
csd->read_current_min = (u8_t)((raw_csd[1U] &
|
||||
csd->read_current_min = (uint8_t)((raw_csd[1U] &
|
||||
0x38000000U) >> 27U);
|
||||
csd->read_current_max = (u8_t)((raw_csd[1U] &
|
||||
csd->read_current_max = (uint8_t)((raw_csd[1U] &
|
||||
0x7000000U) >> 24U);
|
||||
csd->write_current_min = (u8_t)((raw_csd[1U] &
|
||||
csd->write_current_min = (uint8_t)((raw_csd[1U] &
|
||||
0xE00000U) >> 20U);
|
||||
csd->write_current_max = (u8_t)((raw_csd[1U] &
|
||||
csd->write_current_max = (uint8_t)((raw_csd[1U] &
|
||||
0x1C0000U) >> 18U);
|
||||
csd->dev_size_mul = (u8_t)((raw_csd[1U] &
|
||||
csd->dev_size_mul = (uint8_t)((raw_csd[1U] &
|
||||
0x38000U) >> 15U);
|
||||
|
||||
/* Get card total block count and block size. */
|
||||
|
|
@ -647,9 +647,9 @@ static inline void sdhc_decode_csd(struct sd_csd *csd,
|
|||
case 1:
|
||||
tmp_blk_size = SDMMC_DEFAULT_BLOCK_SIZE;
|
||||
|
||||
csd->device_size = (u32_t)((raw_csd[2U] &
|
||||
csd->device_size = (uint32_t)((raw_csd[2U] &
|
||||
0x3FU) << 16U);
|
||||
csd->device_size |= (u32_t)((raw_csd[1U] &
|
||||
csd->device_size |= (uint32_t)((raw_csd[1U] &
|
||||
0xFFFF0000U) >> 16U);
|
||||
|
||||
tmp_blk_cout = ((csd->device_size + 1U) * 1024U);
|
||||
|
|
@ -662,46 +662,46 @@ static inline void sdhc_decode_csd(struct sd_csd *csd,
|
|||
break;
|
||||
}
|
||||
|
||||
if ((u8_t)((raw_csd[1U] & 0x4000U) >> 14U))
|
||||
if ((uint8_t)((raw_csd[1U] & 0x4000U) >> 14U))
|
||||
csd->flags |= SD_CSD_ERASE_BLK_EN_FLAG;
|
||||
csd->erase_size = (u8_t)((raw_csd[1U] &
|
||||
csd->erase_size = (uint8_t)((raw_csd[1U] &
|
||||
0x3F80U) >> 7U);
|
||||
csd->write_prtect_size = (u8_t)(raw_csd[1U] &
|
||||
csd->write_prtect_size = (uint8_t)(raw_csd[1U] &
|
||||
0x7FU);
|
||||
csd->write_speed_factor = (u8_t)((raw_csd[0U] &
|
||||
csd->write_speed_factor = (uint8_t)((raw_csd[0U] &
|
||||
0x1C000000U) >> 26U);
|
||||
csd->write_blk_len = (u8_t)((raw_csd[0U] &
|
||||
csd->write_blk_len = (uint8_t)((raw_csd[0U] &
|
||||
0x3C00000U) >> 22U);
|
||||
if ((u8_t)((raw_csd[0U] & 0x200000U) >> 21U))
|
||||
if ((uint8_t)((raw_csd[0U] & 0x200000U) >> 21U))
|
||||
csd->flags |= SD_CSD_WRITE_BLK_PARTIAL_FLAG;
|
||||
if ((u8_t)((raw_csd[0U] & 0x8000U) >> 15U))
|
||||
if ((uint8_t)((raw_csd[0U] & 0x8000U) >> 15U))
|
||||
csd->flags |= SD_CSD_FILE_FMT_GRP_FLAG;
|
||||
if ((u8_t)((raw_csd[0U] & 0x4000U) >> 14U))
|
||||
if ((uint8_t)((raw_csd[0U] & 0x4000U) >> 14U))
|
||||
csd->flags |= SD_CSD_COPY_FLAG;
|
||||
if ((u8_t)((raw_csd[0U] & 0x2000U) >> 13U))
|
||||
if ((uint8_t)((raw_csd[0U] & 0x2000U) >> 13U))
|
||||
csd->flags |=
|
||||
SD_CSD_PERMANENT_WRITE_PROTECT_FLAG;
|
||||
if ((u8_t)((raw_csd[0U] & 0x1000U) >> 12U))
|
||||
if ((uint8_t)((raw_csd[0U] & 0x1000U) >> 12U))
|
||||
csd->flags |=
|
||||
SD_CSD_TMP_WRITE_PROTECT_FLAG;
|
||||
csd->file_fmt = (u8_t)((raw_csd[0U] & 0xC00U) >> 10U);
|
||||
csd->file_fmt = (uint8_t)((raw_csd[0U] & 0xC00U) >> 10U);
|
||||
}
|
||||
|
||||
static inline void sdhc_decode_scr(struct sd_scr *scr,
|
||||
u32_t *raw_scr, u32_t *version)
|
||||
uint32_t *raw_scr, uint32_t *version)
|
||||
{
|
||||
u32_t tmp_version = 0;
|
||||
uint32_t tmp_version = 0;
|
||||
|
||||
scr->scr_structure = (u8_t)((raw_scr[0U] & 0xF0000000U) >> 28U);
|
||||
scr->sd_spec = (u8_t)((raw_scr[0U] & 0xF000000U) >> 24U);
|
||||
if ((u8_t)((raw_scr[0U] & 0x800000U) >> 23U))
|
||||
scr->scr_structure = (uint8_t)((raw_scr[0U] & 0xF0000000U) >> 28U);
|
||||
scr->sd_spec = (uint8_t)((raw_scr[0U] & 0xF000000U) >> 24U);
|
||||
if ((uint8_t)((raw_scr[0U] & 0x800000U) >> 23U))
|
||||
scr->flags |= SD_SCR_DATA_STATUS_AFTER_ERASE;
|
||||
scr->sd_sec = (u8_t)((raw_scr[0U] & 0x700000U) >> 20U);
|
||||
scr->sd_width = (u8_t)((raw_scr[0U] & 0xF0000U) >> 16U);
|
||||
if ((u8_t)((raw_scr[0U] & 0x8000U) >> 15U))
|
||||
scr->sd_sec = (uint8_t)((raw_scr[0U] & 0x700000U) >> 20U);
|
||||
scr->sd_width = (uint8_t)((raw_scr[0U] & 0xF0000U) >> 16U);
|
||||
if ((uint8_t)((raw_scr[0U] & 0x8000U) >> 15U))
|
||||
scr->flags |= SD_SCR_SPEC3;
|
||||
scr->sd_ext_sec = (u8_t)((raw_scr[0U] & 0x7800U) >> 10U);
|
||||
scr->cmd_support = (u8_t)(raw_scr[0U] & 0x3U);
|
||||
scr->sd_ext_sec = (uint8_t)((raw_scr[0U] & 0x7800U) >> 10U);
|
||||
scr->cmd_support = (uint8_t)(raw_scr[0U] & 0x3U);
|
||||
scr->rsvd = raw_scr[1U];
|
||||
/* Get specification version. */
|
||||
switch (scr->sd_spec) {
|
||||
|
|
@ -726,23 +726,23 @@ static inline void sdhc_decode_scr(struct sd_scr *scr,
|
|||
}
|
||||
|
||||
static inline void sdhc_decode_cid(struct sd_cid *cid,
|
||||
u32_t *raw_cid)
|
||||
uint32_t *raw_cid)
|
||||
{
|
||||
cid->manufacturer = (u8_t)((raw_cid[3U] & 0xFF000000U) >> 24U);
|
||||
cid->application = (u16_t)((raw_cid[3U] & 0xFFFF00U) >> 8U);
|
||||
cid->manufacturer = (uint8_t)((raw_cid[3U] & 0xFF000000U) >> 24U);
|
||||
cid->application = (uint16_t)((raw_cid[3U] & 0xFFFF00U) >> 8U);
|
||||
|
||||
cid->name[0U] = (u8_t)((raw_cid[3U] & 0xFFU));
|
||||
cid->name[1U] = (u8_t)((raw_cid[2U] & 0xFF000000U) >> 24U);
|
||||
cid->name[2U] = (u8_t)((raw_cid[2U] & 0xFF0000U) >> 16U);
|
||||
cid->name[3U] = (u8_t)((raw_cid[2U] & 0xFF00U) >> 8U);
|
||||
cid->name[4U] = (u8_t)((raw_cid[2U] & 0xFFU));
|
||||
cid->name[0U] = (uint8_t)((raw_cid[3U] & 0xFFU));
|
||||
cid->name[1U] = (uint8_t)((raw_cid[2U] & 0xFF000000U) >> 24U);
|
||||
cid->name[2U] = (uint8_t)((raw_cid[2U] & 0xFF0000U) >> 16U);
|
||||
cid->name[3U] = (uint8_t)((raw_cid[2U] & 0xFF00U) >> 8U);
|
||||
cid->name[4U] = (uint8_t)((raw_cid[2U] & 0xFFU));
|
||||
|
||||
cid->version = (u8_t)((raw_cid[1U] & 0xFF000000U) >> 24U);
|
||||
cid->version = (uint8_t)((raw_cid[1U] & 0xFF000000U) >> 24U);
|
||||
|
||||
cid->ser_num = (u32_t)((raw_cid[1U] & 0xFFFFFFU) << 8U);
|
||||
cid->ser_num |= (u32_t)((raw_cid[0U] & 0xFF000000U) >> 24U);
|
||||
cid->ser_num = (uint32_t)((raw_cid[1U] & 0xFFFFFFU) << 8U);
|
||||
cid->ser_num |= (uint32_t)((raw_cid[0U] & 0xFF000000U) >> 24U);
|
||||
|
||||
cid->date = (u16_t)((raw_cid[0U] & 0xFFF00U) >> 8U);
|
||||
cid->date = (uint16_t)((raw_cid[0U] & 0xFFF00U) >> 8U);
|
||||
}
|
||||
|
||||
#endif /*ZEPHYR_INCLUDE_DISK_ACCESS_SDHC_H_*/
|
||||
|
|
|
|||
|
|
@ -27,12 +27,12 @@ struct sdhc_spi_data {
|
|||
struct device *spi;
|
||||
struct spi_config cfg;
|
||||
struct device *cs;
|
||||
u32_t pin;
|
||||
uint32_t pin;
|
||||
gpio_dt_flags_t flags;
|
||||
|
||||
bool high_capacity;
|
||||
u32_t sector_count;
|
||||
u8_t status;
|
||||
uint32_t sector_count;
|
||||
uint8_t status;
|
||||
#if LOG_LEVEL >= LOG_LEVEL_DBG
|
||||
int trace_dir;
|
||||
#endif
|
||||
|
|
@ -42,7 +42,7 @@ DEVICE_DECLARE(sdhc_spi_0);
|
|||
|
||||
/* Traces card traffic for LOG_LEVEL_DBG */
|
||||
static int sdhc_spi_trace(struct sdhc_spi_data *data, int dir, int err,
|
||||
const u8_t *buf, int len)
|
||||
const uint8_t *buf, int len)
|
||||
{
|
||||
#if LOG_LEVEL >= LOG_LEVEL_DBG
|
||||
if (err != 0) {
|
||||
|
|
@ -76,11 +76,11 @@ static void sdhc_spi_set_cs(struct sdhc_spi_data *data, int value)
|
|||
}
|
||||
|
||||
/* Receives a fixed number of bytes */
|
||||
static int sdhc_spi_rx_bytes(struct sdhc_spi_data *data, u8_t *buf, int len)
|
||||
static int sdhc_spi_rx_bytes(struct sdhc_spi_data *data, uint8_t *buf, int len)
|
||||
{
|
||||
struct spi_buf tx_bufs[] = {
|
||||
{
|
||||
.buf = (u8_t *)sdhc_ones,
|
||||
.buf = (uint8_t *)sdhc_ones,
|
||||
.len = len
|
||||
}
|
||||
};
|
||||
|
|
@ -110,7 +110,7 @@ static int sdhc_spi_rx_bytes(struct sdhc_spi_data *data, u8_t *buf, int len)
|
|||
/* Receives and returns a single byte */
|
||||
static int sdhc_spi_rx_u8(struct sdhc_spi_data *data)
|
||||
{
|
||||
u8_t buf[1];
|
||||
uint8_t buf[1];
|
||||
int err = sdhc_spi_rx_bytes(data, buf, sizeof(buf));
|
||||
|
||||
if (err != 0) {
|
||||
|
|
@ -121,11 +121,11 @@ static int sdhc_spi_rx_u8(struct sdhc_spi_data *data)
|
|||
}
|
||||
|
||||
/* Transmits a block of bytes */
|
||||
static int sdhc_spi_tx(struct sdhc_spi_data *data, const u8_t *buf, int len)
|
||||
static int sdhc_spi_tx(struct sdhc_spi_data *data, const uint8_t *buf, int len)
|
||||
{
|
||||
struct spi_buf spi_bufs[] = {
|
||||
{
|
||||
.buf = (u8_t *)buf,
|
||||
.buf = (uint8_t *)buf,
|
||||
.len = len
|
||||
}
|
||||
};
|
||||
|
|
@ -141,9 +141,9 @@ static int sdhc_spi_tx(struct sdhc_spi_data *data, const u8_t *buf, int len)
|
|||
}
|
||||
|
||||
/* Transmits the command and payload */
|
||||
static int sdhc_spi_tx_cmd(struct sdhc_spi_data *data, u8_t cmd, u32_t payload)
|
||||
static int sdhc_spi_tx_cmd(struct sdhc_spi_data *data, uint8_t cmd, uint32_t payload)
|
||||
{
|
||||
u8_t buf[SDHC_CMD_SIZE];
|
||||
uint8_t buf[SDHC_CMD_SIZE];
|
||||
|
||||
LOG_DBG("cmd%d payload=%u", cmd, payload);
|
||||
sdhc_spi_trace(data, 0, 0, NULL, 0);
|
||||
|
|
@ -241,7 +241,7 @@ static int sdhc_spi_skip_until_ready(struct sdhc_spi_data *data)
|
|||
|
||||
/* Sends a command and returns the received R1 status code */
|
||||
static int sdhc_spi_cmd_r1_raw(struct sdhc_spi_data *data,
|
||||
u8_t cmd, u32_t payload)
|
||||
uint8_t cmd, uint32_t payload)
|
||||
{
|
||||
int err;
|
||||
|
||||
|
|
@ -264,13 +264,13 @@ static int sdhc_spi_cmd_r1_raw(struct sdhc_spi_data *data,
|
|||
|
||||
/* Sends a command and returns the mapped error code */
|
||||
static int sdhc_spi_cmd_r1(struct sdhc_spi_data *data,
|
||||
u8_t cmd, uint32_t payload)
|
||||
uint8_t cmd, uint32_t payload)
|
||||
{
|
||||
return sdhc_map_r1_status(sdhc_spi_cmd_r1_raw(data, cmd, payload));
|
||||
}
|
||||
|
||||
/* Sends a command in idle mode returns the mapped error code */
|
||||
static int sdhc_spi_cmd_r1_idle(struct sdhc_spi_data *data, u8_t cmd,
|
||||
static int sdhc_spi_cmd_r1_idle(struct sdhc_spi_data *data, uint8_t cmd,
|
||||
uint32_t payload)
|
||||
{
|
||||
return sdhc_map_r1_idle_status(sdhc_spi_cmd_r1_raw(data, cmd, payload));
|
||||
|
|
@ -278,7 +278,7 @@ static int sdhc_spi_cmd_r1_idle(struct sdhc_spi_data *data, u8_t cmd,
|
|||
|
||||
/* Sends a command and returns the received multi-byte R2 status code */
|
||||
static int sdhc_spi_cmd_r2(struct sdhc_spi_data *data,
|
||||
u8_t cmd, uint32_t payload)
|
||||
uint8_t cmd, uint32_t payload)
|
||||
{
|
||||
int err;
|
||||
int r1;
|
||||
|
|
@ -305,11 +305,11 @@ static int sdhc_spi_cmd_r2(struct sdhc_spi_data *data,
|
|||
|
||||
/* Sends a command and returns the received multi-byte status code */
|
||||
static int sdhc_spi_cmd_r37_raw(struct sdhc_spi_data *data,
|
||||
u8_t cmd, u32_t payload, u32_t *reply)
|
||||
uint8_t cmd, uint32_t payload, uint32_t *reply)
|
||||
{
|
||||
int err;
|
||||
int status;
|
||||
u8_t buf[sizeof(*reply)];
|
||||
uint8_t buf[sizeof(*reply)];
|
||||
|
||||
err = sdhc_spi_tx_cmd(data, cmd, payload);
|
||||
if (err != 0) {
|
||||
|
|
@ -334,7 +334,7 @@ static int sdhc_spi_cmd_r37_raw(struct sdhc_spi_data *data,
|
|||
|
||||
/* Sends a command in idle mode returns the mapped error code */
|
||||
static int sdhc_spi_cmd_r7_idle(struct sdhc_spi_data *data,
|
||||
u8_t cmd, u32_t payload, u32_t *reply)
|
||||
uint8_t cmd, uint32_t payload, uint32_t *reply)
|
||||
{
|
||||
return sdhc_map_r1_idle_status(
|
||||
sdhc_spi_cmd_r37_raw(data, cmd, payload, reply));
|
||||
|
|
@ -342,7 +342,7 @@ static int sdhc_spi_cmd_r7_idle(struct sdhc_spi_data *data,
|
|||
|
||||
/* Sends a command and returns the received multi-byte R3 error code */
|
||||
static int sdhc_spi_cmd_r3(struct sdhc_spi_data *data,
|
||||
u8_t cmd, uint32_t payload, u32_t *reply)
|
||||
uint8_t cmd, uint32_t payload, uint32_t *reply)
|
||||
{
|
||||
return sdhc_map_r1_status(
|
||||
sdhc_spi_cmd_r37_raw(data, cmd, payload, reply));
|
||||
|
|
@ -350,7 +350,7 @@ static int sdhc_spi_cmd_r3(struct sdhc_spi_data *data,
|
|||
|
||||
/* Receives a SDHC data block */
|
||||
static int sdhc_spi_rx_block(struct sdhc_spi_data *data,
|
||||
u8_t *buf, int len)
|
||||
uint8_t *buf, int len)
|
||||
{
|
||||
int err;
|
||||
int token;
|
||||
|
|
@ -358,7 +358,7 @@ static int sdhc_spi_rx_block(struct sdhc_spi_data *data,
|
|||
/* Note the one extra byte to ensure there's an idle byte
|
||||
* between commands.
|
||||
*/
|
||||
u8_t crc[SDHC_CRC16_SIZE + 1];
|
||||
uint8_t crc[SDHC_CRC16_SIZE + 1];
|
||||
|
||||
token = sdhc_spi_skip(data, 0xFF);
|
||||
if (token < 0) {
|
||||
|
|
@ -376,7 +376,7 @@ static int sdhc_spi_rx_block(struct sdhc_spi_data *data,
|
|||
|
||||
struct spi_buf tx_bufs[] = {
|
||||
{
|
||||
.buf = (u8_t *)sdhc_ones,
|
||||
.buf = (uint8_t *)sdhc_ones,
|
||||
.len = remain
|
||||
}
|
||||
};
|
||||
|
|
@ -422,9 +422,9 @@ static int sdhc_spi_rx_block(struct sdhc_spi_data *data,
|
|||
|
||||
/* Transmits a SDHC data block */
|
||||
static int sdhc_spi_tx_block(struct sdhc_spi_data *data,
|
||||
u8_t *send, int len)
|
||||
uint8_t *send, int len)
|
||||
{
|
||||
u8_t buf[SDHC_CRC16_SIZE];
|
||||
uint8_t buf[SDHC_CRC16_SIZE];
|
||||
int err;
|
||||
|
||||
/* Start the block */
|
||||
|
|
@ -473,7 +473,7 @@ static int sdhc_spi_go_idle(struct sdhc_spi_data *data)
|
|||
/* Checks the supported host voltage and basic protocol of a SDHC card */
|
||||
static int sdhc_spi_check_interface(struct sdhc_spi_data *data)
|
||||
{
|
||||
u32_t cond;
|
||||
uint32_t cond;
|
||||
int err;
|
||||
|
||||
/* Check that the current voltage is supported */
|
||||
|
|
@ -500,13 +500,13 @@ static int sdhc_spi_check_interface(struct sdhc_spi_data *data)
|
|||
static int sdhc_spi_detect(struct sdhc_spi_data *data)
|
||||
{
|
||||
int err;
|
||||
u32_t ocr;
|
||||
uint32_t ocr;
|
||||
struct sdhc_retry retry;
|
||||
u8_t structure;
|
||||
u8_t readbllen;
|
||||
u32_t csize;
|
||||
u8_t csizemult;
|
||||
u8_t buf[SDHC_CSD_SIZE];
|
||||
uint8_t structure;
|
||||
uint8_t readbllen;
|
||||
uint32_t csize;
|
||||
uint8_t csizemult;
|
||||
uint8_t buf[SDHC_CSD_SIZE];
|
||||
bool is_v2;
|
||||
|
||||
data->cfg.frequency = SDHC_SPI_INITIAL_SPEED;
|
||||
|
|
@ -608,7 +608,7 @@ static int sdhc_spi_detect(struct sdhc_spi_data *data)
|
|||
* blocks.
|
||||
*/
|
||||
csize = (sys_get_be32(&buf[6]) >> 14) & ((1 << 12) - 1);
|
||||
csizemult = (u8_t) ((sys_get_be16(&buf[9]) >> 7) & ((1 << 3) - 1));
|
||||
csizemult = (uint8_t) ((sys_get_be16(&buf[9]) >> 7) & ((1 << 3) - 1));
|
||||
data->sector_count = ((csize + 1) << (csizemult + 2 + readbllen - 9));
|
||||
break;
|
||||
case SDHC_CSD_V2:
|
||||
|
|
@ -654,10 +654,10 @@ static int sdhc_spi_detect(struct sdhc_spi_data *data)
|
|||
}
|
||||
|
||||
static int sdhc_spi_read(struct sdhc_spi_data *data,
|
||||
u8_t *buf, u32_t sector, u32_t count)
|
||||
uint8_t *buf, uint32_t sector, uint32_t count)
|
||||
{
|
||||
int err;
|
||||
u32_t addr;
|
||||
uint32_t addr;
|
||||
|
||||
err = sdhc_map_disk_status(data->status);
|
||||
if (err != 0) {
|
||||
|
|
@ -704,10 +704,10 @@ error:
|
|||
}
|
||||
|
||||
static int sdhc_spi_write(struct sdhc_spi_data *data,
|
||||
const u8_t *buf, u32_t sector, u32_t count)
|
||||
const uint8_t *buf, uint32_t sector, uint32_t count)
|
||||
{
|
||||
int err;
|
||||
u32_t addr;
|
||||
uint32_t addr;
|
||||
|
||||
err = sdhc_map_disk_status(data->status);
|
||||
if (err != 0) {
|
||||
|
|
@ -732,7 +732,7 @@ static int sdhc_spi_write(struct sdhc_spi_data *data,
|
|||
goto error;
|
||||
}
|
||||
|
||||
err = sdhc_spi_tx_block(data, (u8_t *)buf,
|
||||
err = sdhc_spi_tx_block(data, (uint8_t *)buf,
|
||||
SDMMC_DEFAULT_BLOCK_SIZE);
|
||||
if (err != 0) {
|
||||
goto error;
|
||||
|
|
@ -793,7 +793,7 @@ static int disk_spi_sdhc_access_status(struct disk_info *disk)
|
|||
}
|
||||
|
||||
static int disk_spi_sdhc_access_read(struct disk_info *disk,
|
||||
u8_t *buf, u32_t sector, u32_t count)
|
||||
uint8_t *buf, uint32_t sector, uint32_t count)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct sdhc_spi_data *data = dev->driver_data;
|
||||
|
|
@ -811,7 +811,7 @@ static int disk_spi_sdhc_access_read(struct disk_info *disk,
|
|||
}
|
||||
|
||||
static int disk_spi_sdhc_access_write(struct disk_info *disk,
|
||||
const u8_t *buf, u32_t sector, u32_t count)
|
||||
const uint8_t *buf, uint32_t sector, uint32_t count)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct sdhc_spi_data *data = dev->driver_data;
|
||||
|
|
@ -829,7 +829,7 @@ static int disk_spi_sdhc_access_write(struct disk_info *disk,
|
|||
}
|
||||
|
||||
static int disk_spi_sdhc_access_ioctl(struct disk_info *disk,
|
||||
u8_t cmd, void *buf)
|
||||
uint8_t cmd, void *buf)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct sdhc_spi_data *data = dev->driver_data;
|
||||
|
|
@ -844,13 +844,13 @@ static int disk_spi_sdhc_access_ioctl(struct disk_info *disk,
|
|||
case DISK_IOCTL_CTRL_SYNC:
|
||||
break;
|
||||
case DISK_IOCTL_GET_SECTOR_COUNT:
|
||||
*(u32_t *)buf = data->sector_count;
|
||||
*(uint32_t *)buf = data->sector_count;
|
||||
break;
|
||||
case DISK_IOCTL_GET_SECTOR_SIZE:
|
||||
*(u32_t *)buf = SDMMC_DEFAULT_BLOCK_SIZE;
|
||||
*(uint32_t *)buf = SDMMC_DEFAULT_BLOCK_SIZE;
|
||||
break;
|
||||
case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
|
||||
*(u32_t *)buf = SDMMC_DEFAULT_BLOCK_SIZE;
|
||||
*(uint32_t *)buf = SDMMC_DEFAULT_BLOCK_SIZE;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -126,8 +126,8 @@ static int stm32_sdmmc_access_status(struct disk_info *disk)
|
|||
return priv->status;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc_access_read(struct disk_info *disk, u8_t *data_buf,
|
||||
u32_t start_sector, u32_t num_sector)
|
||||
static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf,
|
||||
uint32_t start_sector, uint32_t num_sector)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct stm32_sdmmc_priv *priv = dev->driver_data;
|
||||
|
|
@ -147,14 +147,14 @@ static int stm32_sdmmc_access_read(struct disk_info *disk, u8_t *data_buf,
|
|||
}
|
||||
|
||||
static int stm32_sdmmc_access_write(struct disk_info *disk,
|
||||
const u8_t *data_buf,
|
||||
u32_t start_sector, u32_t num_sector)
|
||||
const uint8_t *data_buf,
|
||||
uint32_t start_sector, uint32_t num_sector)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct stm32_sdmmc_priv *priv = dev->driver_data;
|
||||
int err;
|
||||
|
||||
err = HAL_SD_WriteBlocks(&priv->hsd, (u8_t *)data_buf, start_sector,
|
||||
err = HAL_SD_WriteBlocks(&priv->hsd, (uint8_t *)data_buf, start_sector,
|
||||
num_sector, 30000);
|
||||
if (err != HAL_OK) {
|
||||
LOG_ERR("sd write block failed %d", err);
|
||||
|
|
@ -166,7 +166,7 @@ static int stm32_sdmmc_access_write(struct disk_info *disk,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_sdmmc_access_ioctl(struct disk_info *disk, u8_t cmd,
|
||||
static int stm32_sdmmc_access_ioctl(struct disk_info *disk, uint8_t cmd,
|
||||
void *buff)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
|
|
@ -180,17 +180,17 @@ static int stm32_sdmmc_access_ioctl(struct disk_info *disk, u8_t cmd,
|
|||
if (err != HAL_OK) {
|
||||
return -EIO;
|
||||
}
|
||||
*(u32_t *)buff = info.LogBlockNbr;
|
||||
*(uint32_t *)buff = info.LogBlockNbr;
|
||||
break;
|
||||
case DISK_IOCTL_GET_SECTOR_SIZE:
|
||||
err = HAL_SD_GetCardInfo(&priv->hsd, &info);
|
||||
if (err != HAL_OK) {
|
||||
return -EIO;
|
||||
}
|
||||
*(u32_t *)buff = info.LogBlockSize;
|
||||
*(uint32_t *)buff = info.LogBlockSize;
|
||||
break;
|
||||
case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
|
||||
*(u32_t *)buff = 1;
|
||||
*(uint32_t *)buff = 1;
|
||||
break;
|
||||
case DISK_IOCTL_CTRL_SYNC:
|
||||
/* we use a blocking API, so nothing to do for sync */
|
||||
|
|
@ -253,7 +253,7 @@ static void stm32_sdmmc_cd_handler(struct k_work *item)
|
|||
|
||||
static void stm32_sdmmc_cd_callback(struct device *gpiodev,
|
||||
struct gpio_callback *cb,
|
||||
u32_t pin)
|
||||
uint32_t pin)
|
||||
{
|
||||
struct stm32_sdmmc_priv *priv = CONTAINER_OF(cb,
|
||||
struct stm32_sdmmc_priv,
|
||||
|
|
|
|||
|
|
@ -273,13 +273,13 @@ enum usdhc_data_bus_width {
|
|||
USDHC_BLK_ATT_BLKCNT_SHIFT)
|
||||
|
||||
struct usdhc_cmd {
|
||||
u32_t index; /*cmd idx*/
|
||||
u32_t argument; /*cmd arg*/
|
||||
uint32_t index; /*cmd idx*/
|
||||
uint32_t argument; /*cmd arg*/
|
||||
enum usdhc_cmd_type cmd_type;
|
||||
enum sdhc_rsp_type rsp_type;
|
||||
u32_t response[4U];
|
||||
u32_t rsp_err_flags;
|
||||
u32_t flags;
|
||||
uint32_t response[4U];
|
||||
uint32_t rsp_err_flags;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
struct usdhc_data {
|
||||
|
|
@ -292,20 +292,20 @@ struct usdhc_data {
|
|||
* to read/write all the data
|
||||
*/
|
||||
bool data_enable;
|
||||
u8_t data_type;
|
||||
uint8_t data_type;
|
||||
/* this is used to distinguish
|
||||
* the normal/tuning/boot data
|
||||
*/
|
||||
u32_t block_size;
|
||||
uint32_t block_size;
|
||||
/* Block size
|
||||
*/
|
||||
u32_t block_count;
|
||||
uint32_t block_count;
|
||||
/* Block count
|
||||
*/
|
||||
u32_t *rx_data;
|
||||
uint32_t *rx_data;
|
||||
/* Buffer to save data read
|
||||
*/
|
||||
const u32_t *tx_data;
|
||||
const uint32_t *tx_data;
|
||||
/* Data buffer to write
|
||||
*/
|
||||
};
|
||||
|
|
@ -344,11 +344,11 @@ struct usdhc_adma_config {
|
|||
enum usdhc_burst_len burst_len;
|
||||
/* burst len config
|
||||
*/
|
||||
u32_t *adma_table;
|
||||
uint32_t *adma_table;
|
||||
/* ADMA table address,
|
||||
* can't be null if transfer way is ADMA1/ADMA2
|
||||
*/
|
||||
u32_t adma_table_words;
|
||||
uint32_t adma_table_words;
|
||||
/* ADMA table length united as words,
|
||||
* can't be 0 if transfer way is ADMA1/ADMA2
|
||||
*/
|
||||
|
|
@ -375,33 +375,33 @@ enum usdhc_endian_mode {
|
|||
|
||||
struct usdhc_config {
|
||||
USDHC_Type *base;
|
||||
u32_t data_timeout;
|
||||
uint32_t data_timeout;
|
||||
/* Data timeout value
|
||||
*/
|
||||
enum usdhc_endian_mode endian;
|
||||
/* Endian mode
|
||||
*/
|
||||
u8_t read_watermark;
|
||||
uint8_t read_watermark;
|
||||
/* Watermark level for DMA read operation.
|
||||
* Available range is 1 ~ 128.
|
||||
*/
|
||||
u8_t write_watermark;
|
||||
uint8_t write_watermark;
|
||||
/* Watermark level for DMA write operation.
|
||||
* Available range is 1 ~ 128.
|
||||
*/
|
||||
u8_t read_burst_len;
|
||||
uint8_t read_burst_len;
|
||||
/* Read burst len
|
||||
*/
|
||||
u8_t write_burst_len;
|
||||
uint8_t write_burst_len;
|
||||
/* Write burst len
|
||||
*/
|
||||
u32_t src_clk_hz;
|
||||
uint32_t src_clk_hz;
|
||||
};
|
||||
|
||||
struct usdhc_capability {
|
||||
u32_t max_blk_len;
|
||||
u32_t max_blk_cnt;
|
||||
u32_t host_flags;
|
||||
uint32_t max_blk_len;
|
||||
uint32_t max_blk_cnt;
|
||||
uint32_t host_flags;
|
||||
};
|
||||
|
||||
enum host_detect_type {
|
||||
|
|
@ -417,19 +417,19 @@ enum host_detect_type {
|
|||
};
|
||||
|
||||
struct usdhc_client_info {
|
||||
u32_t busclk_hz;
|
||||
u32_t relative_addr;
|
||||
u32_t version;
|
||||
u32_t card_flags;
|
||||
u32_t raw_cid[4U];
|
||||
u32_t raw_csd[4U];
|
||||
u32_t raw_scr[2U];
|
||||
u32_t raw_ocr;
|
||||
uint32_t busclk_hz;
|
||||
uint32_t relative_addr;
|
||||
uint32_t version;
|
||||
uint32_t card_flags;
|
||||
uint32_t raw_cid[4U];
|
||||
uint32_t raw_csd[4U];
|
||||
uint32_t raw_scr[2U];
|
||||
uint32_t raw_ocr;
|
||||
struct sd_cid cid;
|
||||
struct sd_csd csd;
|
||||
struct sd_scr scr;
|
||||
u32_t sd_block_count;
|
||||
u32_t sd_block_size;
|
||||
uint32_t sd_block_count;
|
||||
uint32_t sd_block_size;
|
||||
enum sd_timing_mode sd_timing;
|
||||
enum sd_driver_strength driver_strength;
|
||||
enum sd_max_current max_current;
|
||||
|
|
@ -438,19 +438,19 @@ struct usdhc_client_info {
|
|||
|
||||
struct usdhc_board_config {
|
||||
struct device *pwr_gpio;
|
||||
u32_t pwr_pin;
|
||||
uint32_t pwr_pin;
|
||||
gpio_dt_flags_t pwr_flags;
|
||||
|
||||
struct device *detect_gpio;
|
||||
u32_t detect_pin;
|
||||
uint32_t detect_pin;
|
||||
gpio_dt_flags_t detect_flags;
|
||||
struct gpio_callback detect_cb;
|
||||
};
|
||||
|
||||
struct usdhc_priv {
|
||||
bool host_ready;
|
||||
u8_t status;
|
||||
u8_t nusdhc;
|
||||
uint8_t status;
|
||||
uint8_t nusdhc;
|
||||
|
||||
struct usdhc_board_config board_cfg;
|
||||
|
||||
|
|
@ -557,9 +557,9 @@ enum usdhc_adma2_descriptor_flag {
|
|||
};
|
||||
|
||||
struct usdhc_adma2_descriptor {
|
||||
u32_t attribute;
|
||||
uint32_t attribute;
|
||||
/*!< The control and status field */
|
||||
const u32_t *address;
|
||||
const uint32_t *address;
|
||||
/*!< The address field */
|
||||
};
|
||||
|
||||
|
|
@ -721,28 +721,28 @@ static void usdhc_millsec_delay(unsigned int cycles_to_wait)
|
|||
;
|
||||
}
|
||||
|
||||
u32_t g_usdhc_boot_dummy __aligned(64);
|
||||
u32_t g_usdhc_rx_dummy[2048] __aligned(64);
|
||||
uint32_t g_usdhc_boot_dummy __aligned(64);
|
||||
uint32_t g_usdhc_rx_dummy[2048] __aligned(64);
|
||||
|
||||
static int usdhc_adma2_descriptor_cfg(
|
||||
u32_t *adma_table, u32_t adma_table_words,
|
||||
const u32_t *data_addr, u32_t data_size, u32_t flags)
|
||||
uint32_t *adma_table, uint32_t adma_table_words,
|
||||
const uint32_t *data_addr, uint32_t data_size, uint32_t flags)
|
||||
{
|
||||
u32_t min_entries, start_entry = 0U;
|
||||
u32_t max_entries = (adma_table_words * sizeof(u32_t)) /
|
||||
uint32_t min_entries, start_entry = 0U;
|
||||
uint32_t max_entries = (adma_table_words * sizeof(uint32_t)) /
|
||||
sizeof(struct usdhc_adma2_descriptor);
|
||||
struct usdhc_adma2_descriptor *adma2_addr =
|
||||
(struct usdhc_adma2_descriptor *)(adma_table);
|
||||
u32_t i, dma_buf_len = 0U;
|
||||
uint32_t i, dma_buf_len = 0U;
|
||||
|
||||
if ((u32_t)data_addr % USDHC_ADMA2_ADDRESS_ALIGN) {
|
||||
if ((uint32_t)data_addr % USDHC_ADMA2_ADDRESS_ALIGN) {
|
||||
return -EIO;
|
||||
}
|
||||
/* Add non aligned access support.
|
||||
*/
|
||||
if (data_size % sizeof(u32_t)) {
|
||||
if (data_size % sizeof(uint32_t)) {
|
||||
/* make the data length as word-aligned */
|
||||
data_size += sizeof(u32_t) - (data_size % sizeof(u32_t));
|
||||
data_size += sizeof(uint32_t) - (data_size % sizeof(uint32_t));
|
||||
}
|
||||
|
||||
/* Check if ADMA descriptor's number is enough. */
|
||||
|
|
@ -776,7 +776,7 @@ static int usdhc_adma2_descriptor_cfg(
|
|||
dma_buf_len =
|
||||
USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
|
||||
} else {
|
||||
dma_buf_len = (data_size == 0U ? sizeof(u32_t) :
|
||||
dma_buf_len = (data_size == 0U ? sizeof(uint32_t) :
|
||||
data_size);
|
||||
/* adma don't support 0 data length transfer
|
||||
* descriptor
|
||||
|
|
@ -791,7 +791,7 @@ static int usdhc_adma2_descriptor_cfg(
|
|||
adma2_addr[i].attribute |=
|
||||
(data_size == 0U) ? 0U :
|
||||
(USDHC_ADMA2_XFER_FLAG | USDHC_ADMA2_INT_FLAG);
|
||||
data_addr += (dma_buf_len / sizeof(u32_t));
|
||||
data_addr += (dma_buf_len / sizeof(uint32_t));
|
||||
|
||||
if (data_size != 0U)
|
||||
data_size -= dma_buf_len;
|
||||
|
|
@ -813,14 +813,14 @@ static int usdhc_adma2_descriptor_cfg(
|
|||
|
||||
static int usdhc_Internal_dma_cfg(struct usdhc_priv *priv,
|
||||
struct usdhc_adma_config *dma_cfg,
|
||||
const u32_t *data_addr)
|
||||
const uint32_t *data_addr)
|
||||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
bool cmd23 = priv->op_context.data.cmd23;
|
||||
|
||||
if (dma_cfg->dma_mode == USDHC_DMA_SIMPLE) {
|
||||
/* check DMA data buffer address align or not */
|
||||
if (((u32_t)data_addr % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) {
|
||||
if (((uint32_t)data_addr % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) {
|
||||
return -EIO;
|
||||
}
|
||||
/* in simple DMA mode if use auto CMD23,
|
||||
|
|
@ -828,13 +828,13 @@ static int usdhc_Internal_dma_cfg(struct usdhc_priv *priv,
|
|||
* and block count should load to DS_ADDR
|
||||
*/
|
||||
if (cmd23)
|
||||
base->ADMA_SYS_ADDR = (u32_t)data_addr;
|
||||
base->ADMA_SYS_ADDR = (uint32_t)data_addr;
|
||||
else
|
||||
base->DS_ADDR = (u32_t)data_addr;
|
||||
base->DS_ADDR = (uint32_t)data_addr;
|
||||
} else {
|
||||
/* When use ADMA, disable simple DMA */
|
||||
base->DS_ADDR = 0U;
|
||||
base->ADMA_SYS_ADDR = (u32_t)(dma_cfg->adma_table);
|
||||
base->ADMA_SYS_ADDR = (uint32_t)(dma_cfg->adma_table);
|
||||
}
|
||||
|
||||
/* select DMA mode and config the burst length */
|
||||
|
|
@ -849,16 +849,16 @@ static int usdhc_Internal_dma_cfg(struct usdhc_priv *priv,
|
|||
}
|
||||
|
||||
|
||||
static int usdhc_adma_table_cfg(struct usdhc_priv *priv, u32_t flags)
|
||||
static int usdhc_adma_table_cfg(struct usdhc_priv *priv, uint32_t flags)
|
||||
{
|
||||
int error = -EIO;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
struct usdhc_adma_config *dma_cfg = &priv->op_context.dma_cfg;
|
||||
u32_t boot_dummy_off = data->data_type == USDHC_XFER_BOOT_CONTINUOUS ?
|
||||
sizeof(u32_t) : 0U;
|
||||
const u32_t *data_addr = (const u32_t *)((u32_t)((!data->rx_data) ?
|
||||
uint32_t boot_dummy_off = data->data_type == USDHC_XFER_BOOT_CONTINUOUS ?
|
||||
sizeof(uint32_t) : 0U;
|
||||
const uint32_t *data_addr = (const uint32_t *)((uint32_t)((!data->rx_data) ?
|
||||
data->tx_data : data->rx_data) + boot_dummy_off);
|
||||
u32_t data_size = data->block_size * data->block_count - boot_dummy_off;
|
||||
uint32_t data_size = data->block_size * data->block_count - boot_dummy_off;
|
||||
|
||||
switch (dma_cfg->dma_mode) {
|
||||
case USDHC_DMA_SIMPLE:
|
||||
|
|
@ -892,9 +892,9 @@ static int usdhc_data_xfer_cfg(struct usdhc_priv *priv,
|
|||
bool en_dma)
|
||||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
u32_t mix_ctrl = base->MIX_CTRL;
|
||||
uint32_t mix_ctrl = base->MIX_CTRL;
|
||||
struct usdhc_data *data = NULL;
|
||||
u32_t *flag = &priv->op_context.cmd.flags;
|
||||
uint32_t *flag = &priv->op_context.cmd.flags;
|
||||
|
||||
if (!priv->op_context.cmd_only)
|
||||
data = &priv->op_context.data;
|
||||
|
|
@ -1004,8 +1004,8 @@ static int usdhc_data_xfer_cfg(struct usdhc_priv *priv,
|
|||
|
||||
static void usdhc_send_cmd(USDHC_Type *base, struct usdhc_cmd *command)
|
||||
{
|
||||
u32_t xfer_type = base->CMD_XFR_TYP;
|
||||
u32_t flags = command->flags;
|
||||
uint32_t xfer_type = base->CMD_XFR_TYP;
|
||||
uint32_t flags = command->flags;
|
||||
|
||||
if (!(base->PRES_STATE & USDHC_CMD_INHIBIT_FLAG)
|
||||
&& (command->cmd_type != USDHC_CMD_TYPE_EMPTY)) {
|
||||
|
|
@ -1076,7 +1076,7 @@ static void usdhc_send_cmd(USDHC_Type *base, struct usdhc_cmd *command)
|
|||
|
||||
static int usdhc_cmd_rsp(struct usdhc_priv *priv)
|
||||
{
|
||||
u32_t i;
|
||||
uint32_t i;
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
|
||||
|
|
@ -1121,7 +1121,7 @@ static int usdhc_wait_cmd_done(struct usdhc_priv *priv,
|
|||
bool poll_cmd)
|
||||
{
|
||||
int error = 0;
|
||||
u32_t int_status = 0U;
|
||||
uint32_t int_status = 0U;
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
|
||||
/* check if need polling command done or not */
|
||||
|
|
@ -1152,38 +1152,38 @@ static int usdhc_wait_cmd_done(struct usdhc_priv *priv,
|
|||
return error;
|
||||
}
|
||||
|
||||
static inline void usdhc_write_data(USDHC_Type *base, u32_t data)
|
||||
static inline void usdhc_write_data(USDHC_Type *base, uint32_t data)
|
||||
{
|
||||
base->DATA_BUFF_ACC_PORT = data;
|
||||
}
|
||||
|
||||
static inline u32_t usdhc_read_data(USDHC_Type *base)
|
||||
static inline uint32_t usdhc_read_data(USDHC_Type *base)
|
||||
{
|
||||
return base->DATA_BUFF_ACC_PORT;
|
||||
}
|
||||
|
||||
static u32_t usdhc_read_data_port(struct usdhc_priv *priv,
|
||||
u32_t xfered_words)
|
||||
static uint32_t usdhc_read_data_port(struct usdhc_priv *priv,
|
||||
uint32_t xfered_words)
|
||||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
u32_t i, total_words, remaing_words;
|
||||
uint32_t i, total_words, remaing_words;
|
||||
/* The words can be read at this time. */
|
||||
u32_t watermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >>
|
||||
uint32_t watermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >>
|
||||
USDHC_WTMK_LVL_RD_WML_SHIFT);
|
||||
|
||||
/* If DMA is enable, do not need to polling data port */
|
||||
if (!(base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK)) {
|
||||
/*Add non aligned access support.*/
|
||||
if (data->block_size % sizeof(u32_t)) {
|
||||
if (data->block_size % sizeof(uint32_t)) {
|
||||
data->block_size +=
|
||||
sizeof(u32_t) -
|
||||
(data->block_size % sizeof(u32_t));
|
||||
sizeof(uint32_t) -
|
||||
(data->block_size % sizeof(uint32_t));
|
||||
/* make the block size as word-aligned */
|
||||
}
|
||||
|
||||
total_words = ((data->block_count * data->block_size) /
|
||||
sizeof(u32_t));
|
||||
sizeof(uint32_t));
|
||||
|
||||
if (watermark >= total_words) {
|
||||
remaing_words = total_words;
|
||||
|
|
@ -1208,19 +1208,19 @@ static int usdhc_read_data_port_sync(struct usdhc_priv *priv)
|
|||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
u32_t total_words;
|
||||
u32_t xfered_words = 0U, int_status = 0U;
|
||||
uint32_t total_words;
|
||||
uint32_t xfered_words = 0U, int_status = 0U;
|
||||
int error = 0;
|
||||
|
||||
if (data->block_size % sizeof(u32_t)) {
|
||||
if (data->block_size % sizeof(uint32_t)) {
|
||||
data->block_size +=
|
||||
sizeof(u32_t) -
|
||||
(data->block_size % sizeof(u32_t));
|
||||
sizeof(uint32_t) -
|
||||
(data->block_size % sizeof(uint32_t));
|
||||
}
|
||||
|
||||
total_words =
|
||||
((data->block_count * data->block_size) /
|
||||
sizeof(u32_t));
|
||||
sizeof(uint32_t));
|
||||
|
||||
while ((!error) && (xfered_words < total_words)) {
|
||||
while (!(int_status & (USDHC_INT_BUF_READ_READY_FLAG |
|
||||
|
|
@ -1262,27 +1262,27 @@ static int usdhc_read_data_port_sync(struct usdhc_priv *priv)
|
|||
return error;
|
||||
}
|
||||
|
||||
static u32_t usdhc_write_data_port(struct usdhc_priv *priv,
|
||||
u32_t xfered_words)
|
||||
static uint32_t usdhc_write_data_port(struct usdhc_priv *priv,
|
||||
uint32_t xfered_words)
|
||||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
u32_t i, total_words, remaing_words;
|
||||
uint32_t i, total_words, remaing_words;
|
||||
/* Words can be wrote at this time. */
|
||||
u32_t watermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >>
|
||||
uint32_t watermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >>
|
||||
USDHC_WTMK_LVL_WR_WML_SHIFT);
|
||||
|
||||
/* If DMA is enable, do not need to polling data port */
|
||||
if (!(base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK)) {
|
||||
if (data->block_size % sizeof(u32_t)) {
|
||||
if (data->block_size % sizeof(uint32_t)) {
|
||||
data->block_size +=
|
||||
sizeof(u32_t) -
|
||||
(data->block_size % sizeof(u32_t));
|
||||
sizeof(uint32_t) -
|
||||
(data->block_size % sizeof(uint32_t));
|
||||
}
|
||||
|
||||
total_words =
|
||||
((data->block_count * data->block_size) /
|
||||
sizeof(u32_t));
|
||||
sizeof(uint32_t));
|
||||
|
||||
if (watermark >= total_words) {
|
||||
remaing_words = total_words;
|
||||
|
|
@ -1307,16 +1307,16 @@ static status_t usdhc_write_data_port_sync(struct usdhc_priv *priv)
|
|||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
u32_t total_words;
|
||||
u32_t xfered_words = 0U, int_status = 0U;
|
||||
uint32_t total_words;
|
||||
uint32_t xfered_words = 0U, int_status = 0U;
|
||||
int error = 0;
|
||||
|
||||
if (data->block_size % sizeof(u32_t)) {
|
||||
if (data->block_size % sizeof(uint32_t)) {
|
||||
data->block_size +=
|
||||
sizeof(u32_t) - (data->block_size % sizeof(u32_t));
|
||||
sizeof(uint32_t) - (data->block_size % sizeof(uint32_t));
|
||||
}
|
||||
|
||||
total_words = (data->block_count * data->block_size) / sizeof(u32_t);
|
||||
total_words = (data->block_count * data->block_size) / sizeof(uint32_t);
|
||||
|
||||
while ((!error) && (xfered_words < total_words)) {
|
||||
while (!(int_status & (USDHC_INT_BUF_WRITE_READY_FLAG |
|
||||
|
|
@ -1366,7 +1366,7 @@ static status_t usdhc_write_data_port_sync(struct usdhc_priv *priv)
|
|||
static int usdhc_data_sync_xfer(struct usdhc_priv *priv, bool en_dma)
|
||||
{
|
||||
int error = 0;
|
||||
u32_t int_status = 0U;
|
||||
uint32_t int_status = 0U;
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
|
||||
|
|
@ -1480,9 +1480,9 @@ static inline void usdhc_force_clk_on(USDHC_Type *base, bool on)
|
|||
base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK;
|
||||
}
|
||||
|
||||
static void usdhc_tuning(USDHC_Type *base, u32_t start, u32_t step, bool enable)
|
||||
static void usdhc_tuning(USDHC_Type *base, uint32_t start, uint32_t step, bool enable)
|
||||
{
|
||||
u32_t tuning_ctrl = 0U;
|
||||
uint32_t tuning_ctrl = 0U;
|
||||
|
||||
if (enable) {
|
||||
/* feedback clock */
|
||||
|
|
@ -1510,9 +1510,9 @@ static void usdhc_tuning(USDHC_Type *base, u32_t start, u32_t step, bool enable)
|
|||
}
|
||||
}
|
||||
|
||||
int usdhc_adjust_tuning_timing(USDHC_Type *base, u32_t delay)
|
||||
int usdhc_adjust_tuning_timing(USDHC_Type *base, uint32_t delay)
|
||||
{
|
||||
u32_t clk_tune_ctrl = 0U;
|
||||
uint32_t clk_tune_ctrl = 0U;
|
||||
|
||||
clk_tune_ctrl = base->CLK_TUNE_CTRL_STATUS;
|
||||
|
||||
|
|
@ -1531,7 +1531,7 @@ int usdhc_adjust_tuning_timing(USDHC_Type *base, u32_t delay)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline void usdhc_set_retuning_timer(USDHC_Type *base, u32_t counter)
|
||||
static inline void usdhc_set_retuning_timer(USDHC_Type *base, uint32_t counter)
|
||||
{
|
||||
base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK;
|
||||
base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter);
|
||||
|
|
@ -1638,7 +1638,7 @@ static int usdhc_vol_switch(struct usdhc_priv *priv)
|
|||
}
|
||||
|
||||
static inline void usdhc_op_ctx_init(struct usdhc_priv *priv,
|
||||
bool cmd_only, u8_t cmd_idx, u32_t arg, enum sdhc_rsp_type rsp_type)
|
||||
bool cmd_only, uint8_t cmd_idx, uint32_t arg, enum sdhc_rsp_type rsp_type)
|
||||
{
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
|
|
@ -1654,11 +1654,11 @@ static inline void usdhc_op_ctx_init(struct usdhc_priv *priv,
|
|||
}
|
||||
|
||||
static int usdhc_select_fun(struct usdhc_priv *priv,
|
||||
u32_t group, u32_t function)
|
||||
uint32_t group, uint32_t function)
|
||||
{
|
||||
u32_t *fun_status;
|
||||
u16_t fun_grp_info[6U] = {0};
|
||||
u32_t current_fun_status = 0U, arg;
|
||||
uint32_t *fun_status;
|
||||
uint16_t fun_grp_info[6U] = {0};
|
||||
uint32_t current_fun_status = 0U, arg;
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
int ret;
|
||||
|
|
@ -1671,7 +1671,7 @@ static int usdhc_select_fun(struct usdhc_priv *priv,
|
|||
|
||||
/* Check if card support high speed mode. */
|
||||
arg = (SD_SWITCH_CHECK << 31U | 0x00FFFFFFU);
|
||||
arg &= ~((u32_t)(0xFU) << (group * 4U));
|
||||
arg &= ~((uint32_t)(0xFU) << (group * 4U));
|
||||
arg |= (function << (group * 4U));
|
||||
usdhc_op_ctx_init(priv, 0, SDHC_SWITCH, arg, SDHC_RSP_TYPE_R1);
|
||||
|
||||
|
|
@ -1708,12 +1708,12 @@ static int usdhc_select_fun(struct usdhc_priv *priv,
|
|||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
fun_grp_info[5U] = (u16_t)fun_status[0U];
|
||||
fun_grp_info[4U] = (u16_t)(fun_status[1U] >> 16U);
|
||||
fun_grp_info[3U] = (u16_t)(fun_status[1U]);
|
||||
fun_grp_info[2U] = (u16_t)(fun_status[2U] >> 16U);
|
||||
fun_grp_info[1U] = (u16_t)(fun_status[2U]);
|
||||
fun_grp_info[0U] = (u16_t)(fun_status[3U] >> 16U);
|
||||
fun_grp_info[5U] = (uint16_t)fun_status[0U];
|
||||
fun_grp_info[4U] = (uint16_t)(fun_status[1U] >> 16U);
|
||||
fun_grp_info[3U] = (uint16_t)(fun_status[1U]);
|
||||
fun_grp_info[2U] = (uint16_t)(fun_status[2U] >> 16U);
|
||||
fun_grp_info[1U] = (uint16_t)(fun_status[2U]);
|
||||
fun_grp_info[0U] = (uint16_t)(fun_status[3U] >> 16U);
|
||||
current_fun_status = ((fun_status[3U] & 0xFFU) << 8U) |
|
||||
(fun_status[4U] >> 24U);
|
||||
|
||||
|
|
@ -1732,7 +1732,7 @@ static int usdhc_select_fun(struct usdhc_priv *priv,
|
|||
data->rx_data = &g_usdhc_rx_dummy[0];
|
||||
|
||||
cmd->argument = (SD_SWITCH_SET << 31U | 0x00FFFFFFU);
|
||||
cmd->argument &= ~((u32_t)(0xFU) << (group * 4U));
|
||||
cmd->argument &= ~((uint32_t)(0xFU) << (group * 4U));
|
||||
cmd->argument |= (function << (group * 4U));
|
||||
|
||||
ret = usdhc_xfer(priv);
|
||||
|
|
@ -1771,13 +1771,13 @@ static int usdhc_select_fun(struct usdhc_priv *priv,
|
|||
return 0;
|
||||
}
|
||||
|
||||
u32_t usdhc_set_sd_clk(USDHC_Type *base, u32_t src_clk_hz, u32_t sd_clk_hz)
|
||||
uint32_t usdhc_set_sd_clk(USDHC_Type *base, uint32_t src_clk_hz, uint32_t sd_clk_hz)
|
||||
{
|
||||
u32_t total_div = 0U;
|
||||
u32_t divisor = 0U;
|
||||
u32_t prescaler = 0U;
|
||||
u32_t sysctl = 0U;
|
||||
u32_t nearest_freq = 0U;
|
||||
uint32_t total_div = 0U;
|
||||
uint32_t divisor = 0U;
|
||||
uint32_t prescaler = 0U;
|
||||
uint32_t sysctl = 0U;
|
||||
uint32_t nearest_freq = 0U;
|
||||
|
||||
assert(src_clk_hz != 0U);
|
||||
assert((sd_clk_hz != 0U) && (sd_clk_hz <= src_clk_hz));
|
||||
|
|
@ -1870,9 +1870,9 @@ u32_t usdhc_set_sd_clk(USDHC_Type *base, u32_t src_clk_hz, u32_t sd_clk_hz)
|
|||
}
|
||||
|
||||
static void usdhc_enable_ddr_mode(USDHC_Type *base,
|
||||
bool enable, u32_t nibble_pos)
|
||||
bool enable, uint32_t nibble_pos)
|
||||
{
|
||||
u32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >>
|
||||
uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >>
|
||||
USDHC_SYS_CTRL_SDCLKFS_SHIFT;
|
||||
|
||||
if (enable) {
|
||||
|
|
@ -2044,8 +2044,8 @@ static int usdhc_select_bus_timing(struct usdhc_priv *priv)
|
|||
return error;
|
||||
}
|
||||
|
||||
static int usdhc_write_sector(void *bus_data, const u8_t *buf, u32_t sector,
|
||||
u32_t count)
|
||||
static int usdhc_write_sector(void *bus_data, const uint8_t *buf, uint32_t sector,
|
||||
uint32_t count)
|
||||
{
|
||||
struct usdhc_priv *priv = bus_data;
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
|
|
@ -2058,7 +2058,7 @@ static int usdhc_write_sector(void *bus_data, const u8_t *buf, u32_t sector,
|
|||
cmd->index = SDHC_WRITE_MULTIPLE_BLOCK;
|
||||
data->block_size = priv->card_info.sd_block_size;
|
||||
data->block_count = count;
|
||||
data->tx_data = (const u32_t *)buf;
|
||||
data->tx_data = (const uint32_t *)buf;
|
||||
data->cmd12 = true;
|
||||
if (data->block_count == 1U) {
|
||||
cmd->index = SDHC_WRITE_BLOCK;
|
||||
|
|
@ -2073,8 +2073,8 @@ static int usdhc_write_sector(void *bus_data, const u8_t *buf, u32_t sector,
|
|||
return usdhc_xfer(priv);
|
||||
}
|
||||
|
||||
static int usdhc_read_sector(void *bus_data, u8_t *buf, u32_t sector,
|
||||
u32_t count)
|
||||
static int usdhc_read_sector(void *bus_data, uint8_t *buf, uint32_t sector,
|
||||
uint32_t count)
|
||||
{
|
||||
struct usdhc_priv *priv = bus_data;
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
|
|
@ -2087,7 +2087,7 @@ static int usdhc_read_sector(void *bus_data, u8_t *buf, u32_t sector,
|
|||
cmd->index = SDHC_READ_MULTIPLE_BLOCK;
|
||||
data->block_size = priv->card_info.sd_block_size;
|
||||
data->block_count = count;
|
||||
data->rx_data = (u32_t *)buf;
|
||||
data->rx_data = (uint32_t *)buf;
|
||||
data->cmd12 = true;
|
||||
|
||||
if (data->block_count == 1U) {
|
||||
|
|
@ -2107,7 +2107,7 @@ static int usdhc_read_sector(void *bus_data, u8_t *buf, u32_t sector,
|
|||
|
||||
static bool usdhc_set_sd_active(USDHC_Type *base)
|
||||
{
|
||||
u32_t timeout = 0xffff;
|
||||
uint32_t timeout = 0xffff;
|
||||
|
||||
base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK;
|
||||
/* Delay some time to wait card become active state. */
|
||||
|
|
@ -2125,8 +2125,8 @@ static bool usdhc_set_sd_active(USDHC_Type *base)
|
|||
static void usdhc_get_host_capability(USDHC_Type *base,
|
||||
struct usdhc_capability *capability)
|
||||
{
|
||||
u32_t host_cap;
|
||||
u32_t max_blk_len;
|
||||
uint32_t host_cap;
|
||||
uint32_t max_blk_len;
|
||||
|
||||
host_cap = base->HOST_CTRL_CAP;
|
||||
|
||||
|
|
@ -2150,7 +2150,7 @@ static void usdhc_get_host_capability(USDHC_Type *base,
|
|||
USDHC_SUPPORT_8BIT_FLAG);
|
||||
}
|
||||
|
||||
static bool usdhc_hw_reset(USDHC_Type *base, u32_t mask, u32_t timeout)
|
||||
static bool usdhc_hw_reset(USDHC_Type *base, uint32_t mask, uint32_t timeout)
|
||||
{
|
||||
base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK |
|
||||
USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK));
|
||||
|
|
@ -2168,8 +2168,8 @@ static bool usdhc_hw_reset(USDHC_Type *base, u32_t mask, u32_t timeout)
|
|||
static void usdhc_host_hw_init(USDHC_Type *base,
|
||||
const struct usdhc_config *config)
|
||||
{
|
||||
u32_t proctl, sysctl, wml;
|
||||
u32_t int_mask;
|
||||
uint32_t proctl, sysctl, wml;
|
||||
uint32_t int_mask;
|
||||
|
||||
assert(config);
|
||||
assert((config->write_watermark >= 1U) &&
|
||||
|
|
@ -2220,7 +2220,7 @@ static void usdhc_host_hw_init(USDHC_Type *base,
|
|||
}
|
||||
|
||||
static void usdhc_cd_gpio_cb(struct device *dev,
|
||||
struct gpio_callback *cb, u32_t pins)
|
||||
struct gpio_callback *cb, uint32_t pins)
|
||||
{
|
||||
struct usdhc_board_config *board_cfg =
|
||||
CONTAINER_OF(cb, struct usdhc_board_config, detect_cb);
|
||||
|
|
@ -2230,7 +2230,7 @@ static void usdhc_cd_gpio_cb(struct device *dev,
|
|||
}
|
||||
|
||||
static int usdhc_cd_gpio_init(struct device *detect_gpio,
|
||||
u32_t pin, gpio_dt_flags_t flags,
|
||||
uint32_t pin, gpio_dt_flags_t flags,
|
||||
struct gpio_callback *callback)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -2259,7 +2259,7 @@ static void usdhc_host_reset(struct usdhc_priv *priv)
|
|||
}
|
||||
|
||||
static int usdhc_app_host_cmd(struct usdhc_priv *priv, int retry,
|
||||
u32_t arg, u8_t app_cmd, u32_t app_arg, enum sdhc_rsp_type rsp_type,
|
||||
uint32_t arg, uint8_t app_cmd, uint32_t app_arg, enum sdhc_rsp_type rsp_type,
|
||||
enum sdhc_rsp_type app_rsp_type, bool app_cmd_only)
|
||||
{
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
|
|
@ -2291,7 +2291,7 @@ APP_CMD_XFER_AGAIN:
|
|||
static int usdhc_sd_init(struct usdhc_priv *priv)
|
||||
{
|
||||
USDHC_Type *base = priv->host_config.base;
|
||||
u32_t app_cmd_41_arg = 0U;
|
||||
uint32_t app_cmd_41_arg = 0U;
|
||||
int ret, retry;
|
||||
struct usdhc_cmd *cmd = &priv->op_context.cmd;
|
||||
struct usdhc_data *data = &priv->op_context.data;
|
||||
|
|
@ -2567,7 +2567,7 @@ APP_SEND_OP_COND_AGAIN:
|
|||
retry = 10;
|
||||
ret = -EIO;
|
||||
while (ret && retry >= 0) {
|
||||
ret = usdhc_read_sector(priv, (u8_t *)g_usdhc_rx_dummy, 0, 1);
|
||||
ret = usdhc_read_sector(priv, (uint8_t *)g_usdhc_rx_dummy, 0, 1);
|
||||
if (!ret) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -2590,7 +2590,7 @@ static K_MUTEX_DEFINE(z_usdhc_init_lock);
|
|||
static int usdhc_board_access_init(struct usdhc_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
u32_t gpio_level;
|
||||
uint32_t gpio_level;
|
||||
|
||||
if (priv->nusdhc == 0) {
|
||||
#if DT_NODE_HAS_PROP(DT_INST(0, nxp_imx_usdhc), pwr_gpios)
|
||||
|
|
@ -2785,8 +2785,8 @@ static int disk_usdhc_access_status(struct disk_info *disk)
|
|||
return priv->status;
|
||||
}
|
||||
|
||||
static int disk_usdhc_access_read(struct disk_info *disk, u8_t *buf,
|
||||
u32_t sector, u32_t count)
|
||||
static int disk_usdhc_access_read(struct disk_info *disk, uint8_t *buf,
|
||||
uint32_t sector, uint32_t count)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct usdhc_priv *priv = dev->driver_data;
|
||||
|
|
@ -2796,8 +2796,8 @@ static int disk_usdhc_access_read(struct disk_info *disk, u8_t *buf,
|
|||
return usdhc_read_sector(priv, buf, sector, count);
|
||||
}
|
||||
|
||||
static int disk_usdhc_access_write(struct disk_info *disk, const u8_t *buf,
|
||||
u32_t sector, u32_t count)
|
||||
static int disk_usdhc_access_write(struct disk_info *disk, const uint8_t *buf,
|
||||
uint32_t sector, uint32_t count)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct usdhc_priv *priv = dev->driver_data;
|
||||
|
|
@ -2807,7 +2807,7 @@ static int disk_usdhc_access_write(struct disk_info *disk, const u8_t *buf,
|
|||
return usdhc_write_sector(priv, buf, sector, count);
|
||||
}
|
||||
|
||||
static int disk_usdhc_access_ioctl(struct disk_info *disk, u8_t cmd, void *buf)
|
||||
static int disk_usdhc_access_ioctl(struct disk_info *disk, uint8_t cmd, void *buf)
|
||||
{
|
||||
struct device *dev = disk->dev;
|
||||
struct usdhc_priv *priv = dev->driver_data;
|
||||
|
|
@ -2822,13 +2822,13 @@ static int disk_usdhc_access_ioctl(struct disk_info *disk, u8_t cmd, void *buf)
|
|||
case DISK_IOCTL_CTRL_SYNC:
|
||||
break;
|
||||
case DISK_IOCTL_GET_SECTOR_COUNT:
|
||||
*(u32_t *)buf = priv->card_info.sd_block_count;
|
||||
*(uint32_t *)buf = priv->card_info.sd_block_count;
|
||||
break;
|
||||
case DISK_IOCTL_GET_SECTOR_SIZE:
|
||||
*(u32_t *)buf = priv->card_info.sd_block_size;
|
||||
*(uint32_t *)buf = priv->card_info.sd_block_size;
|
||||
break;
|
||||
case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
|
||||
*(u32_t *)buf = priv->card_info.sd_block_size;
|
||||
*(uint32_t *)buf = priv->card_info.sd_block_size;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* fat table (1, 2), directory table (3) and file(readme) contents (4).
|
||||
*/
|
||||
|
||||
static u8_t ramdisk_buf[RAMDISK_VOLUME_SIZE] = {
|
||||
static uint8_t ramdisk_buf[RAMDISK_VOLUME_SIZE] = {
|
||||
0xEB, 0x3C, 0x90, 0x4D, 0x53, 0x44, 0x4F, 0x53,
|
||||
0x35, 0x2E, 0x30, 0x00, 0x02, 0x01, 0x01, 0x00,
|
||||
0x01, 0x10, 0x00, 0x20, 0x00, 0xF8, 0x02, 0x00,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue