zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
ee6fa31af6
commit
a1b77fd589
2364 changed files with 32505 additions and 32505 deletions
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@ -17,11 +17,11 @@
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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static u32_t ref_clk_freq;
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static uint32_t ref_clk_freq;
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#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
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void z_soc_irq_enable(u32_t irq)
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void z_soc_irq_enable(uint32_t irq)
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{
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struct device *dev_cavs, *dev_ictl;
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@ -80,7 +80,7 @@ void z_soc_irq_enable(u32_t irq)
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irq_enable_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq));
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}
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void z_soc_irq_disable(u32_t irq)
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void z_soc_irq_disable(uint32_t irq)
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{
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struct device *dev_cavs, *dev_ictl;
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@ -224,7 +224,7 @@ static inline void soc_set_resource_ownership(void)
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SOC_GENO_MNDIV_OWNER_DSP;
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}
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u32_t soc_get_ref_clk_freq(void)
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uint32_t soc_get_ref_clk_freq(void)
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{
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return ref_clk_freq;
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}
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@ -297,7 +297,7 @@ static inline void soc_read_bootstraps(void)
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{
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volatile struct soc_global_regs *regs =
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(volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE;
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u32_t bootstrap;
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uint32_t bootstrap;
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bootstrap = regs->straps;
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@ -92,9 +92,9 @@
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#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12)
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struct soc_mclk_control_regs {
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u32_t mdivctrl;
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u32_t reserved[31];
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u32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
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uint32_t mdivctrl;
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uint32_t reserved[31];
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uint32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
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};
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#define PDM_BASE 0x00010000
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@ -127,11 +127,11 @@ struct soc_mclk_control_regs {
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struct soc_resource_alloc_regs {
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union {
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u16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
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u16_t reserved[4];
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uint16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
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uint16_t reserved[4];
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};
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u32_t dspiopo;
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u32_t geno;
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uint32_t dspiopo;
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uint32_t geno;
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};
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/* L2 Local Memory Registers */
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@ -145,8 +145,8 @@ struct soc_resource_alloc_regs {
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#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
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struct soc_dmic_shim_regs {
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u32_t dmiclcap;
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u32_t dmiclctl;
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uint32_t dmiclcap;
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uint32_t dmiclctl;
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};
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/* SOC DSP SHIM Registers */
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@ -160,40 +160,40 @@ struct soc_dmic_shim_regs {
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#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1)
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struct soc_dsp_shim_regs {
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u32_t reserved[8];
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uint32_t reserved[8];
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union {
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struct {
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u32_t walclk32_lo;
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u32_t walclk32_hi;
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uint32_t walclk32_lo;
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uint32_t walclk32_hi;
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};
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u64_t walclk;
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uint64_t walclk;
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};
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u32_t dspwctcs;
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u32_t reserved1[1];
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uint32_t dspwctcs;
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uint32_t reserved1[1];
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union {
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struct {
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u32_t dspwct0c32_lo;
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u32_t dspwct0c32_hi;
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uint32_t dspwct0c32_lo;
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uint32_t dspwct0c32_hi;
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};
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u64_t dspwct0c;
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uint64_t dspwct0c;
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};
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union {
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struct {
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u32_t dspwct1c32_lo;
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u32_t dspwct1c32_hi;
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uint32_t dspwct1c32_lo;
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uint32_t dspwct1c32_hi;
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};
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u64_t dspwct1c;
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uint64_t dspwct1c;
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};
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u32_t reserved2[14];
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u32_t clkctl;
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u32_t clksts;
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u32_t reserved3[4];
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u16_t pwrctl;
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u16_t pwrsts;
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u32_t lpsctl;
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u32_t lpsdmas0;
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u32_t lpsdmas1;
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u32_t reserved4[22];
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uint32_t reserved2[14];
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uint32_t clkctl;
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uint32_t clksts;
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uint32_t reserved3[4];
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uint16_t pwrctl;
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uint16_t pwrsts;
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uint32_t lpsctl;
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uint32_t lpsdmas0;
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uint32_t lpsdmas1;
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uint32_t reserved4[22];
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};
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/* Global Control registers */
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@ -214,12 +214,12 @@ struct soc_dsp_shim_regs {
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#define SOC_S1000_STRAP_REF_CLK_24P576 (2 << 3)
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struct soc_global_regs {
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u32_t reserved1[5];
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u32_t cavs_dsp1power_control;
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u32_t reserved2[2];
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u32_t gna_power_control;
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u32_t reserved3[7];
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u32_t straps;
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uint32_t reserved1[5];
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uint32_t cavs_dsp1power_control;
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uint32_t reserved2[2];
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uint32_t gna_power_control;
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uint32_t reserved3[7];
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uint32_t straps;
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};
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/* macros for data cache operations */
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@ -228,10 +228,10 @@ struct soc_global_regs {
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#define SOC_DCACHE_INVALIDATE(addr, size) \
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xthal_dcache_region_invalidate((addr), (size))
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extern void z_soc_irq_enable(u32_t irq);
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extern void z_soc_irq_disable(u32_t irq);
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extern void z_soc_irq_enable(uint32_t irq);
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extern void z_soc_irq_disable(uint32_t irq);
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extern int z_soc_irq_is_enabled(unsigned int irq);
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extern u32_t soc_get_ref_clk_freq(void);
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extern uint32_t soc_get_ref_clk_freq(void);
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#endif /* __INC_SOC_H */
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@ -26,14 +26,14 @@ static struct device *idc;
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extern void __start(void);
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struct cpustart_rec {
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u32_t cpu;
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uint32_t cpu;
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arch_cpustart_t fn;
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char *stack_top;
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void *arg;
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u32_t vecbase;
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u32_t alive;
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uint32_t vecbase;
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uint32_t alive;
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/* padding to cache line */
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u8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
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uint8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
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};
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static __aligned(XCHAL_DCACHE_LINESIZE)
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@ -122,7 +122,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
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volatile struct soc_global_regs *soc_glb_regs =
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(volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE;
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u32_t vecbase;
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uint32_t vecbase;
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__ASSERT(cpu_num == 1, "Intel S1000 supports only two CPUs!");
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@ -150,7 +150,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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* and set the vector.
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*/
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sys_write32(0x0, SOC_L2RAM_LOCAL_MEM_REG_LSPGCTL);
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*((u32_t *)LPSRAM_BOOT_VECTOR_ADDR) = (u32_t)__start;
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*((uint32_t *)LPSRAM_BOOT_VECTOR_ADDR) = (uint32_t)__start;
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/* Disable power gating for DSP core #cpu_num */
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dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1;
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@ -40,14 +40,14 @@ void log_3(const char *str,
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void log_n(const char *str,
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log_arg_t *args,
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u32_t narg,
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uint32_t narg,
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struct log_msg_ids src_level)
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{
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}
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void log_hexdump(const char *str,
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const u8_t *data,
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u32_t length,
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const uint8_t *data,
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uint32_t length,
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struct log_msg_ids src_level)
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{
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}
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@ -57,7 +57,7 @@ void log_string_sync(struct log_msg_ids src_level, const char *fmt, ...)
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}
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void log_hexdump_sync(struct log_msg_ids src_level, const char *metadata,
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const u8_t *data, u32_t len)
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const uint8_t *data, uint32_t len)
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{
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}
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@ -79,12 +79,12 @@ void log_free(void *buf)
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{
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}
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u32_t log_get_strdup_pool_utilization(void)
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uint32_t log_get_strdup_pool_utilization(void)
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{
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return 0;
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}
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u32_t log_get_strdup_longest_string(void)
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uint32_t log_get_strdup_longest_string(void)
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{
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return 0;
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}
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@ -99,6 +99,6 @@ void __printf_like(2, 3) log_from_user(struct log_msg_ids src_level,
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}
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void log_hexdump_from_user(struct log_msg_ids src_level, const char *metadata,
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const u8_t *data, u32_t len)
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const uint8_t *data, uint32_t len)
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{
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}
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