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zephyr: replace zephyr integer types with C99 types

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git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-05-27 11:26:57 -05:00 • committed by Kumar Gala
commit a1b77fd589
2364 changed files with 32505 additions and 32505 deletions
Download patch file Download diff file Expand all files Collapse all files

2
soc/xtensa/esp32/esp32-mp.c
View file

@ -11,7 +11,7 @@
#include <spinlock.h>
#include <kernel_structs.h>
#define Z_REG(base, off) (*(volatile u32_t *)((base) + (off)))
#define Z_REG(base, off) (*(volatile uint32_t *)((base) + (off)))
#define RTC_CNTL_BASE 0x3ff48000
#define RTC_CNTL_OPTIONS0 Z_REG(RTC_CNTL_BASE, 0x0)

12
soc/xtensa/esp32/soc.c
View file

@ -25,12 +25,12 @@ extern void z_cstart(void);
*/
void __attribute__((section(".iram1"))) __start(void)
{
volatile u32_t *wdt_rtc_reg = (u32_t *)RTC_CNTL_WDTCONFIG0_REG;
volatile u32_t *wdt_timg_reg = (u32_t *)TIMG_WDTCONFIG0_REG(0);
volatile u32_t *app_cpu_config_reg = (u32_t *)DPORT_APPCPU_CTRL_B_REG;
extern u32_t _init_start;
extern u32_t _bss_start;
extern u32_t _bss_end;
volatile uint32_t *wdt_rtc_reg = (uint32_t *)RTC_CNTL_WDTCONFIG0_REG;
volatile uint32_t *wdt_timg_reg = (uint32_t *)TIMG_WDTCONFIG0_REG(0);
volatile uint32_t *app_cpu_config_reg = (uint32_t *)DPORT_APPCPU_CTRL_B_REG;
extern uint32_t _init_start;
extern uint32_t _bss_start;
extern uint32_t _bss_end;
/* Move the exception vector table to IRAM. */
__asm__ __volatile__ (

12
soc/xtensa/esp32/soc.h
View file

@ -25,12 +25,12 @@ struct esp32_peripheral {
int rst;
};
static inline void esp32_set_mask32(u32_t v, u32_t mem_addr)
static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
{
sys_write32(sys_read32(mem_addr) | v, mem_addr);
}
static inline void esp32_clear_mask32(u32_t v, u32_t mem_addr)
static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
{
sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
}
@ -45,15 +45,15 @@ extern int esp32_rom_intr_matrix_set(int cpu_no,
int interrupt_src,
int interrupt_line);
extern int esp32_rom_gpio_matrix_in(u32_t gpio, u32_t signal_index,
extern int esp32_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
bool inverted);
extern int esp32_rom_gpio_matrix_out(u32_t gpio, u32_t signal_index,
extern int esp32_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
bool out_inverted,
bool out_enabled_inverted);
extern void esp32_rom_uart_attach(void);
extern STATUS esp32_rom_uart_tx_one_char(u8_t chr);
extern STATUS esp32_rom_uart_rx_one_char(u8_t *chr);
extern STATUS esp32_rom_uart_tx_one_char(uint8_t chr);
extern STATUS esp32_rom_uart_rx_one_char(uint8_t *chr);
extern void esp32_rom_Cache_Flush(int cpu);
extern void esp32_rom_Cache_Read_Enable(int cpu);

6
soc/xtensa/intel_apl_adsp/soc.c
View file

@ -23,7 +23,7 @@ LOG_MODULE_REGISTER(soc);
#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
void z_soc_irq_enable(u32_t irq)
void z_soc_irq_enable(uint32_t irq)
{
struct device *dev_cavs;
@ -61,7 +61,7 @@ void z_soc_irq_enable(u32_t irq)
irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
}
void z_soc_irq_disable(u32_t irq)
void z_soc_irq_disable(uint32_t irq)
{
struct device *dev_cavs;
@ -141,7 +141,7 @@ out:
#ifdef CONFIG_DYNAMIC_INTERRUPTS
int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
void (*routine)(void *parameter),
void *parameter, u32_t flags)
void *parameter, uint32_t flags)
{
uint32_t table_idx;
uint32_t cavs_irq, cavs_idx;

66
soc/xtensa/intel_apl_adsp/soc.h
View file

@ -105,9 +105,9 @@
#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12)
struct soc_mclk_control_regs {
u32_t mdivctrl;
u32_t reserved[31];
u32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
uint32_t mdivctrl;
uint32_t reserved[31];
uint32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
};
#define PDM_BASE 0x00010000
@ -133,11 +133,11 @@ struct soc_mclk_control_regs {
struct soc_resource_alloc_regs {
union {
u16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
u16_t reserved[4];
uint16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
uint16_t reserved[4];
};
u32_t dspiopo;
u32_t geno;
uint32_t dspiopo;
uint32_t geno;
};
/* DMIC SHIM Registers */
@ -146,8 +146,8 @@ struct soc_resource_alloc_regs {
#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
struct soc_dmic_shim_regs {
u32_t dmiclcap;
u32_t dmiclctl;
uint32_t dmiclcap;
uint32_t dmiclctl;
};
/* SOC DSP SHIM Registers */
@ -208,40 +208,40 @@ struct soc_dmic_shim_regs {
#define DSP_WCT_CS_TT(x) BIT(4 + x)
struct soc_dsp_shim_regs {
u32_t reserved[8];
uint32_t reserved[8];
union {
struct {
u32_t walclk32_lo;
u32_t walclk32_hi;
uint32_t walclk32_lo;
uint32_t walclk32_hi;
};
u64_t walclk;
uint64_t walclk;
};
u32_t dspwctcs;
u32_t reserved1[1];
uint32_t dspwctcs;
uint32_t reserved1[1];
union {
struct {
u32_t dspwct0c32_lo;
u32_t dspwct0c32_hi;
uint32_t dspwct0c32_lo;
uint32_t dspwct0c32_hi;
};
u64_t dspwct0c;
uint64_t dspwct0c;
};
union {
struct {
u32_t dspwct1c32_lo;
u32_t dspwct1c32_hi;
uint32_t dspwct1c32_lo;
uint32_t dspwct1c32_hi;
};
u64_t dspwct1c;
uint64_t dspwct1c;
};
u32_t reserved2[14];
u32_t clkctl;
u32_t clksts;
u32_t reserved3[4];
u16_t pwrctl;
u16_t pwrsts;
u32_t lpsctl;
u32_t lpsdmas0;
u32_t lpsdmas1;
u32_t reserved4[22];
uint32_t reserved2[14];
uint32_t clkctl;
uint32_t clksts;
uint32_t reserved3[4];
uint16_t pwrctl;
uint16_t pwrsts;
uint32_t lpsctl;
uint32_t lpsdmas0;
uint32_t lpsdmas1;
uint32_t reserved4[22];
};
/* macros for data cache operations */
@ -250,8 +250,8 @@ struct soc_dsp_shim_regs {
#define SOC_DCACHE_INVALIDATE(addr, size) \
xthal_dcache_region_invalidate((addr), (size))
extern void z_soc_irq_enable(u32_t irq);
extern void z_soc_irq_disable(u32_t irq);
extern void z_soc_irq_enable(uint32_t irq);
extern void z_soc_irq_disable(uint32_t irq);
extern int z_soc_irq_is_enabled(unsigned int irq);
#endif /* __INC_SOC_H */

18
soc/xtensa/intel_apl_adsp/soc_mp.c
View file

@ -55,17 +55,17 @@ static struct device *idc;
extern void __start(void);
struct cpustart_rec {
u32_t cpu;
uint32_t cpu;
arch_cpustart_t fn;
char *stack_top;
void *arg;
u32_t vecbase;
uint32_t vecbase;
u32_t alive;
uint32_t alive;
/* padding to cache line */
u8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
uint8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
};
static __aligned(XCHAL_DCACHE_LINESIZE)
@ -76,7 +76,7 @@ static void *mp_top;
static void mp_entry2(void)
{
volatile int ps, ie;
u32_t idc_reg;
uint32_t idc_reg;
/* Copy over VECBASE from the main CPU for an initial value
* (will need to revisit this if we ever allow a user API to
@ -149,8 +149,8 @@ __asm__("\n"
*/
void z_mp_entry(void)
{
*(u32_t *)CONFIG_SRAM_BASE_ADDRESS = 0xDEADBEEF;
SOC_DCACHE_FLUSH((u32_t *)CONFIG_SRAM_BASE_ADDRESS, 64);
*(uint32_t *)CONFIG_SRAM_BASE_ADDRESS = 0xDEADBEEF;
SOC_DCACHE_FLUSH((uint32_t *)CONFIG_SRAM_BASE_ADDRESS, 64);
mp_stack_switch(mp_top, mp_entry2);
}
@ -158,8 +158,8 @@ void z_mp_entry(void)
void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
arch_cpustart_t fn, void *arg)
{
u32_t vecbase;
u32_t idc_reg;
uint32_t vecbase;
uint32_t idc_reg;
__ASSERT(cpu_num == 1, "Only supports only two CPUs!");

10
soc/xtensa/intel_s1000/soc.c
View file

@ -17,11 +17,11 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(soc);
static u32_t ref_clk_freq;
static uint32_t ref_clk_freq;
#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
void z_soc_irq_enable(u32_t irq)
void z_soc_irq_enable(uint32_t irq)
{
struct device *dev_cavs, *dev_ictl;
@ -80,7 +80,7 @@ void z_soc_irq_enable(u32_t irq)
irq_enable_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq));
}
void z_soc_irq_disable(u32_t irq)
void z_soc_irq_disable(uint32_t irq)
{
struct device *dev_cavs, *dev_ictl;
@ -224,7 +224,7 @@ static inline void soc_set_resource_ownership(void)
SOC_GENO_MNDIV_OWNER_DSP;
}
u32_t soc_get_ref_clk_freq(void)
uint32_t soc_get_ref_clk_freq(void)
{
return ref_clk_freq;
}
@ -297,7 +297,7 @@ static inline void soc_read_bootstraps(void)
{
volatile struct soc_global_regs *regs =
(volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE;
u32_t bootstrap;
uint32_t bootstrap;
bootstrap = regs->straps;

80
soc/xtensa/intel_s1000/soc.h
View file

@ -92,9 +92,9 @@
#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12)
struct soc_mclk_control_regs {
u32_t mdivctrl;
u32_t reserved[31];
u32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
uint32_t mdivctrl;
uint32_t reserved[31];
uint32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
};
#define PDM_BASE 0x00010000
@ -127,11 +127,11 @@ struct soc_mclk_control_regs {
struct soc_resource_alloc_regs {
union {
u16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
u16_t reserved[4];
uint16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
uint16_t reserved[4];
};
u32_t dspiopo;
u32_t geno;
uint32_t dspiopo;
uint32_t geno;
};
/* L2 Local Memory Registers */
@ -145,8 +145,8 @@ struct soc_resource_alloc_regs {
#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
struct soc_dmic_shim_regs {
u32_t dmiclcap;
u32_t dmiclctl;
uint32_t dmiclcap;
uint32_t dmiclctl;
};
/* SOC DSP SHIM Registers */
@ -160,40 +160,40 @@ struct soc_dmic_shim_regs {
#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1)
struct soc_dsp_shim_regs {
u32_t reserved[8];
uint32_t reserved[8];
union {
struct {
u32_t walclk32_lo;
u32_t walclk32_hi;
uint32_t walclk32_lo;
uint32_t walclk32_hi;
};
u64_t walclk;
uint64_t walclk;
};
u32_t dspwctcs;
u32_t reserved1[1];
uint32_t dspwctcs;
uint32_t reserved1[1];
union {
struct {
u32_t dspwct0c32_lo;
u32_t dspwct0c32_hi;
uint32_t dspwct0c32_lo;
uint32_t dspwct0c32_hi;
};
u64_t dspwct0c;
uint64_t dspwct0c;
};
union {
struct {
u32_t dspwct1c32_lo;
u32_t dspwct1c32_hi;
uint32_t dspwct1c32_lo;
uint32_t dspwct1c32_hi;
};
u64_t dspwct1c;
uint64_t dspwct1c;
};
u32_t reserved2[14];
u32_t clkctl;
u32_t clksts;
u32_t reserved3[4];
u16_t pwrctl;
u16_t pwrsts;
u32_t lpsctl;
u32_t lpsdmas0;
u32_t lpsdmas1;
u32_t reserved4[22];
uint32_t reserved2[14];
uint32_t clkctl;
uint32_t clksts;
uint32_t reserved3[4];
uint16_t pwrctl;
uint16_t pwrsts;
uint32_t lpsctl;
uint32_t lpsdmas0;
uint32_t lpsdmas1;
uint32_t reserved4[22];
};
/* Global Control registers */
@ -214,12 +214,12 @@ struct soc_dsp_shim_regs {
#define SOC_S1000_STRAP_REF_CLK_24P576 (2 << 3)
struct soc_global_regs {
u32_t reserved1[5];
u32_t cavs_dsp1power_control;
u32_t reserved2[2];
u32_t gna_power_control;
u32_t reserved3[7];
u32_t straps;
uint32_t reserved1[5];
uint32_t cavs_dsp1power_control;
uint32_t reserved2[2];
uint32_t gna_power_control;
uint32_t reserved3[7];
uint32_t straps;
};
/* macros for data cache operations */
@ -228,10 +228,10 @@ struct soc_global_regs {
#define SOC_DCACHE_INVALIDATE(addr, size) \
xthal_dcache_region_invalidate((addr), (size))
extern void z_soc_irq_enable(u32_t irq);
extern void z_soc_irq_disable(u32_t irq);
extern void z_soc_irq_enable(uint32_t irq);
extern void z_soc_irq_disable(uint32_t irq);
extern int z_soc_irq_is_enabled(unsigned int irq);
extern u32_t soc_get_ref_clk_freq(void);
extern uint32_t soc_get_ref_clk_freq(void);
#endif /* __INC_SOC_H */

12
soc/xtensa/intel_s1000/soc_mp.c
View file

@ -26,14 +26,14 @@ static struct device *idc;
extern void __start(void);
struct cpustart_rec {
u32_t cpu;
uint32_t cpu;
arch_cpustart_t fn;
char *stack_top;
void *arg;
u32_t vecbase;
u32_t alive;
uint32_t vecbase;
uint32_t alive;
/* padding to cache line */
u8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
uint8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
};
static __aligned(XCHAL_DCACHE_LINESIZE)
@ -122,7 +122,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
volatile struct soc_global_regs *soc_glb_regs =
(volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE;
u32_t vecbase;
uint32_t vecbase;
__ASSERT(cpu_num == 1, "Intel S1000 supports only two CPUs!");
@ -150,7 +150,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
* and set the vector.
*/
sys_write32(0x0, SOC_L2RAM_LOCAL_MEM_REG_LSPGCTL);
*((u32_t *)LPSRAM_BOOT_VECTOR_ADDR) = (u32_t)__start;
*((uint32_t *)LPSRAM_BOOT_VECTOR_ADDR) = (uint32_t)__start;
/* Disable power gating for DSP core #cpu_num */
dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1;

14
soc/xtensa/intel_s1000/xcc/log_minimal_fixes.c
View file

@ -40,14 +40,14 @@ void log_3(const char *str,
void log_n(const char *str,
log_arg_t *args,
u32_t narg,
uint32_t narg,
struct log_msg_ids src_level)
{
}
void log_hexdump(const char *str,
const u8_t *data,
u32_t length,
const uint8_t *data,
uint32_t length,
struct log_msg_ids src_level)
{
}
@ -57,7 +57,7 @@ void log_string_sync(struct log_msg_ids src_level, const char *fmt, ...)
}
void log_hexdump_sync(struct log_msg_ids src_level, const char *metadata,
const u8_t *data, u32_t len)
const uint8_t *data, uint32_t len)
{
}
@ -79,12 +79,12 @@ void log_free(void *buf)
{
}
u32_t log_get_strdup_pool_utilization(void)
uint32_t log_get_strdup_pool_utilization(void)
{
return 0;
}
u32_t log_get_strdup_longest_string(void)
uint32_t log_get_strdup_longest_string(void)
{
return 0;
}
@ -99,6 +99,6 @@ void __printf_like(2, 3) log_from_user(struct log_msg_ids src_level,
}
void log_hexdump_from_user(struct log_msg_ids src_level, const char *metadata,
const u8_t *data, u32_t len)
const uint8_t *data, uint32_t len)
{
}