zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
ee6fa31af6
commit
a1b77fd589
2364 changed files with 32505 additions and 32505 deletions
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@ -131,8 +131,8 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
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* out_queue and presented to application.
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*/
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struct stream {
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s32_t state;
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u32_t dma_channel;
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int32_t state;
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uint32_t dma_channel;
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struct dma_config dma_cfg;
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struct dma_block_config dma_block;
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struct k_msgq in_queue;
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@ -144,7 +144,7 @@ struct stream {
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struct i2s_cavs_config {
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struct i2s_cavs_ssp *regs;
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struct i2s_cavs_mn_div *mn_regs;
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u32_t irq_id;
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uint32_t irq_id;
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void (*irq_connect)(void);
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};
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@ -166,7 +166,7 @@ I2S_DEVICE_OBJECT_DECLARE(1);
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I2S_DEVICE_OBJECT_DECLARE(2);
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I2S_DEVICE_OBJECT_DECLARE(3);
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static void i2s_dma_tx_callback(void *, u32_t, int);
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static void i2s_dma_tx_callback(void *, uint32_t, int);
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static void i2s_tx_stream_disable(struct i2s_cavs_dev_data *,
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volatile struct i2s_cavs_ssp *const, struct device *);
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static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *,
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@ -186,7 +186,7 @@ static inline void i2s_purge_stream_buffers(struct stream *strm,
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}
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/* This function is executed in the interrupt context */
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static void i2s_dma_tx_callback(void *arg, u32_t channel,
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static void i2s_dma_tx_callback(void *arg, uint32_t channel,
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int status)
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{
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struct device *dev = (struct device *)arg;
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@ -215,7 +215,7 @@ static void i2s_dma_tx_callback(void *arg, u32_t channel,
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if (ret == 0) {
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/* reload the DMA */
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dma_reload(dev_data->dev_dma, strm->dma_channel,
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(u32_t)buffer, (u32_t)&ssp->ssd,
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(uint32_t)buffer, (uint32_t)&ssp->ssd,
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dev_data->cfg.block_size);
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dma_start(dev_data->dev_dma, strm->dma_channel);
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ssp->ssc1 |= SSCR1_TSRE;
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@ -242,7 +242,7 @@ static void i2s_dma_tx_callback(void *arg, u32_t channel,
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}
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}
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static void i2s_dma_rx_callback(void *arg, u32_t channel, int status)
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static void i2s_dma_rx_callback(void *arg, uint32_t channel, int status)
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{
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struct device *dev = (struct device *)arg;
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const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
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@ -287,7 +287,7 @@ static void i2s_dma_rx_callback(void *arg, u32_t channel, int status)
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/* reload the DMA */
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dma_reload(dev_data->dev_dma, strm->dma_channel,
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(u32_t)&ssp->ssd, (u32_t)buffer,
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(uint32_t)&ssp->ssd, (uint32_t)buffer,
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dev_data->cfg.block_size);
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dma_start(dev_data->dev_dma, strm->dma_channel);
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ssp->ssc1 |= SSCR1_RSRE;
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@ -308,26 +308,26 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
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volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
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volatile struct i2s_cavs_mn_div *const mn_div = dev_cfg->mn_regs;
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struct dma_block_config *dma_block;
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u8_t num_words = i2s_cfg->channels;
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u8_t word_size_bits = i2s_cfg->word_size;
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u8_t word_size_bytes;
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u32_t bit_clk_freq, mclk;
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uint8_t num_words = i2s_cfg->channels;
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uint8_t word_size_bits = i2s_cfg->word_size;
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uint8_t word_size_bytes;
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uint32_t bit_clk_freq, mclk;
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int ret;
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u32_t ssc0;
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u32_t ssc1;
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u32_t ssc2;
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u32_t ssc3;
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u32_t sspsp;
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u32_t sspsp2;
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u32_t sstsa;
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u32_t ssrsa;
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u32_t ssto;
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u32_t ssioc = 0U;
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u32_t mdiv;
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u32_t i2s_m = 0U;
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u32_t i2s_n = 0U;
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u32_t frame_len = 0U;
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uint32_t ssc0;
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uint32_t ssc1;
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uint32_t ssc2;
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uint32_t ssc3;
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uint32_t sspsp;
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uint32_t sspsp2;
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uint32_t sstsa;
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uint32_t ssrsa;
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uint32_t ssto;
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uint32_t ssioc = 0U;
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uint32_t mdiv;
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uint32_t i2s_m = 0U;
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uint32_t i2s_n = 0U;
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uint32_t frame_len = 0U;
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bool inverted_frame = false;
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if ((dev_data->tx.state != I2S_STATE_NOT_READY) &&
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@ -529,8 +529,8 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
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dma_block = dev_data->tx.dma_cfg.head_block;
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dma_block->block_size = i2s_cfg->block_size;
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dma_block->source_address = (u32_t)NULL;
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dma_block->dest_address = (u32_t)&ssp->ssd;
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dma_block->source_address = (uint32_t)NULL;
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dma_block->dest_address = (uint32_t)&ssp->ssd;
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ret = dma_config(dev_data->dev_dma, dev_data->tx.dma_channel,
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&dev_data->tx.dma_cfg);
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@ -541,8 +541,8 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
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dma_block = dev_data->rx.dma_cfg.head_block;
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dma_block->block_size = i2s_cfg->block_size;
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dma_block->source_address = (u32_t)&ssp->ssd;
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dma_block->dest_address = (u32_t)NULL;
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dma_block->source_address = (uint32_t)&ssp->ssd;
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dma_block->dest_address = (uint32_t)NULL;
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ret = dma_config(dev_data->dev_dma, dev_data->rx.dma_channel,
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&dev_data->rx.dma_cfg);
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@ -579,8 +579,8 @@ static int i2s_tx_stream_start(struct i2s_cavs_dev_data *dev_data,
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return ret;
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}
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ret = dma_reload(dev_dma, strm->dma_channel, (u32_t)buffer,
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(u32_t)&ssp->ssd, dev_data->cfg.block_size);
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ret = dma_reload(dev_dma, strm->dma_channel, (uint32_t)buffer,
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(uint32_t)&ssp->ssd, dev_data->cfg.block_size);
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if (ret != 0) {
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LOG_ERR("dma_reload failed (%d)", ret);
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return ret;
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@ -626,8 +626,8 @@ static int i2s_rx_stream_start(struct i2s_cavs_dev_data *dev_data,
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SOC_DCACHE_INVALIDATE(buffer, dev_data->cfg.block_size);
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ret = dma_reload(dev_dma, strm->dma_channel, (u32_t)&ssp->ssd,
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(u32_t)buffer, dev_data->cfg.block_size);
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ret = dma_reload(dev_dma, strm->dma_channel, (uint32_t)&ssp->ssd,
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(uint32_t)buffer, dev_data->cfg.block_size);
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if (ret != 0) {
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LOG_ERR("dma_reload failed (%d)", ret);
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return ret;
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@ -685,7 +685,7 @@ static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *dev_data,
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struct device *dev_dma)
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{
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struct stream *strm = &dev_data->rx;
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u32_t data;
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uint32_t data;
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/* Disable DMA service request handshake logic. Handshake is
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* not required now since DMA is not in operation.
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@ -821,7 +821,7 @@ static void i2s_cavs_isr(void *arg)
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const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
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volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
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struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
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u32_t status;
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uint32_t status;
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/* clear interrupts */
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status = ssp->sss;
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@ -20,22 +20,22 @@ extern "C" {
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#endif
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struct i2s_cavs_ssp {
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u32_t ssc0; /* 0x00 - Control0 */
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u32_t ssc1; /* 0x04 - Control1 */
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u32_t sss; /* 0x08 - Status */
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u32_t ssit; /* 0x0C - Interrupt Test */
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u32_t ssd; /* 0x10 - Data */
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u32_t reserved0[5];
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u32_t ssto; /* 0x28 - Time Out */
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u32_t sspsp; /* 0x2C - Programmable Serial Protocol */
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u32_t sstsa; /* 0x30 - TX Time Slot Active */
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u32_t ssrsa; /* 0x34 - RX Time Slot Active */
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u32_t sstss; /* 0x38 - Time Slot Status */
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u32_t reserved1;
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u32_t ssc2; /* 0x40 - Command / Status 2 */
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u32_t sspsp2; /* 0x44 - Programmable Serial Protocol 2 */
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u32_t ssc3; /* 0x48 - Command / Status 3 */
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u32_t ssioc; /* 0x4C - IO Control */
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uint32_t ssc0; /* 0x00 - Control0 */
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uint32_t ssc1; /* 0x04 - Control1 */
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uint32_t sss; /* 0x08 - Status */
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uint32_t ssit; /* 0x0C - Interrupt Test */
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uint32_t ssd; /* 0x10 - Data */
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uint32_t reserved0[5];
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uint32_t ssto; /* 0x28 - Time Out */
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uint32_t sspsp; /* 0x2C - Programmable Serial Protocol */
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uint32_t sstsa; /* 0x30 - TX Time Slot Active */
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uint32_t ssrsa; /* 0x34 - RX Time Slot Active */
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uint32_t sstss; /* 0x38 - Time Slot Status */
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uint32_t reserved1;
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uint32_t ssc2; /* 0x40 - Command / Status 2 */
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uint32_t sspsp2; /* 0x44 - Programmable Serial Protocol 2 */
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uint32_t ssc3; /* 0x48 - Command / Status 3 */
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uint32_t ssioc; /* 0x4C - IO Control */
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};
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/* SSCR0 bits */
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@ -132,8 +132,8 @@ struct i2s_cavs_ssp {
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#define SSIOC_SCOE (1 << 5)
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struct i2s_cavs_mn_div {
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u32_t mval; /* 0x00 - M value */
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u32_t nval; /* 0x04 - N value */
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uint32_t mval; /* 0x00 - M value */
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uint32_t nval; /* 0x04 - N value */
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};
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/* MVAL & NVAL bits */
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@ -24,9 +24,9 @@ LOG_MODULE_REGISTER(i2s_ll_stm32);
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*/
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#if 0
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#define DCACHE_INVALIDATE(addr, size) \
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SCB_InvalidateDCache_by_Addr((u32_t *)addr, size)
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SCB_InvalidateDCache_by_Addr((uint32_t *)addr, size)
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#define DCACHE_CLEAN(addr, size) \
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SCB_CleanDCache_by_Addr((u32_t *)addr, size)
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SCB_CleanDCache_by_Addr((uint32_t *)addr, size)
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#else
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#define DCACHE_INVALIDATE(addr, size) {; }
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#define DCACHE_CLEAN(addr, size) {; }
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@ -34,7 +34,7 @@ LOG_MODULE_REGISTER(i2s_ll_stm32);
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#define MODULO_INC(val, max) { val = (++val < max) ? val : 0; }
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static unsigned int div_round_closest(u32_t dividend, u32_t divisor)
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static unsigned int div_round_closest(uint32_t dividend, uint32_t divisor)
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{
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return (dividend + (divisor / 2U)) / divisor;
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}
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@ -68,7 +68,7 @@ static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
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*/
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static int queue_put(struct ring_buf *rb, void *mem_block, size_t size)
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{
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u16_t head_next;
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uint16_t head_next;
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unsigned int key;
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key = irq_lock();
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@ -111,18 +111,18 @@ static int i2s_stm32_enable_clock(struct device *dev)
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#ifdef CONFIG_I2S_STM32_USE_PLLI2S_ENABLE
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#define PLLI2S_MAX_MS_TIME 1 /* PLLI2S lock time is 300us max */
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static u16_t plli2s_ms_count;
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static uint16_t plli2s_ms_count;
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#define z_pllr(v) LL_RCC_PLLI2SR_DIV_ ## v
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#define pllr(v) z_pllr(v)
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#endif
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static int i2s_stm32_set_clock(struct device *dev, u32_t bit_clk_freq)
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static int i2s_stm32_set_clock(struct device *dev, uint32_t bit_clk_freq)
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{
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const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
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u32_t pll_src = LL_RCC_PLL_GetMainSource();
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uint32_t pll_src = LL_RCC_PLL_GetMainSource();
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int freq_in;
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u8_t i2s_div, i2s_odd;
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uint8_t i2s_div, i2s_odd;
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freq_in = (pll_src == LL_RCC_PLLSOURCE_HSI) ?
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HSI_VALUE : CONFIG_CLOCK_STM32_HSE_CLOCK;
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@ -183,7 +183,7 @@ static int i2s_stm32_configure(struct device *dev, enum i2s_dir dir,
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const struct i2s_stm32_cfg *const cfg = DEV_CFG(dev);
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struct i2s_stm32_data *const dev_data = DEV_DATA(dev);
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struct stream *stream;
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u32_t bit_clk_freq;
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uint32_t bit_clk_freq;
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int ret;
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if (dir == I2S_DIR_RX) {
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@ -433,13 +433,13 @@ static const struct i2s_driver_api i2s_stm32_driver_api = {
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static struct device *active_dma_rx_channel[STM32_DMA_NUM_CHANNELS];
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static struct device *active_dma_tx_channel[STM32_DMA_NUM_CHANNELS];
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static int reload_dma(struct device *dev_dma, u32_t channel,
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static int reload_dma(struct device *dev_dma, uint32_t channel,
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struct dma_config *dcfg, void *src, void *dst,
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u32_t blk_size)
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uint32_t blk_size)
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{
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int ret;
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ret = dma_reload(dev_dma, channel, (u32_t)src, (u32_t)dst, blk_size);
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ret = dma_reload(dev_dma, channel, (uint32_t)src, (uint32_t)dst, blk_size);
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if (ret < 0) {
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return ret;
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}
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@ -449,19 +449,19 @@ static int reload_dma(struct device *dev_dma, u32_t channel,
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return ret;
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}
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static int start_dma(struct device *dev_dma, u32_t channel,
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static int start_dma(struct device *dev_dma, uint32_t channel,
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struct dma_config *dcfg, void *src,
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bool src_addr_increment, void *dst,
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bool dst_addr_increment, u8_t fifo_threshold,
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u32_t blk_size)
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bool dst_addr_increment, uint8_t fifo_threshold,
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uint32_t blk_size)
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{
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struct dma_block_config blk_cfg;
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int ret;
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memset(&blk_cfg, 0, sizeof(blk_cfg));
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blk_cfg.block_size = blk_size;
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blk_cfg.source_address = (u32_t)src;
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blk_cfg.dest_address = (u32_t)dst;
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blk_cfg.source_address = (uint32_t)src;
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blk_cfg.dest_address = (uint32_t)dst;
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if (src_addr_increment) {
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blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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@ -486,13 +486,13 @@ static int start_dma(struct device *dev_dma, u32_t channel,
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return ret;
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}
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static struct device *get_dev_from_rx_dma_channel(u32_t dma_channel);
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static struct device *get_dev_from_tx_dma_channel(u32_t dma_channel);
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static struct device *get_dev_from_rx_dma_channel(uint32_t dma_channel);
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static struct device *get_dev_from_tx_dma_channel(uint32_t dma_channel);
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static void rx_stream_disable(struct stream *stream, struct device *dev);
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static void tx_stream_disable(struct stream *stream, struct device *dev);
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/* This function is executed in the interrupt context */
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static void dma_rx_callback(void *arg, u32_t channel, int status)
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static void dma_rx_callback(void *arg, uint32_t channel, int status)
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{
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struct device *dev = get_dev_from_rx_dma_channel(channel);
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const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
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@ -558,7 +558,7 @@ rx_disable:
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rx_stream_disable(stream, dev);
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}
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static void dma_tx_callback(void *arg, u32_t channel, int status)
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static void dma_tx_callback(void *arg, uint32_t channel, int status)
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{
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struct device *dev = get_dev_from_tx_dma_channel(channel);
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const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
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@ -623,8 +623,8 @@ tx_disable:
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tx_stream_disable(stream, dev);
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}
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static u32_t i2s_stm32_irq_count;
|
||||
static u32_t i2s_stm32_irq_ovr_count;
|
||||
static uint32_t i2s_stm32_irq_count;
|
||||
static uint32_t i2s_stm32_irq_ovr_count;
|
||||
|
||||
static void i2s_stm32_isr(void *arg)
|
||||
{
|
||||
|
|
@ -839,12 +839,12 @@ static void tx_queue_drop(struct stream *stream)
|
|||
}
|
||||
}
|
||||
|
||||
static struct device *get_dev_from_rx_dma_channel(u32_t dma_channel)
|
||||
static struct device *get_dev_from_rx_dma_channel(uint32_t dma_channel)
|
||||
{
|
||||
return active_dma_rx_channel[dma_channel];
|
||||
}
|
||||
|
||||
static struct device *get_dev_from_tx_dma_channel(u32_t dma_channel)
|
||||
static struct device *get_dev_from_tx_dma_channel(uint32_t dma_channel)
|
||||
{
|
||||
return active_dma_tx_channel[dma_channel];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -62,30 +62,30 @@ struct queue_item {
|
|||
/* Minimal ring buffer implementation */
|
||||
struct ring_buf {
|
||||
struct queue_item *buf;
|
||||
u16_t len;
|
||||
u16_t head;
|
||||
u16_t tail;
|
||||
uint16_t len;
|
||||
uint16_t head;
|
||||
uint16_t tail;
|
||||
};
|
||||
|
||||
/* Device constant configuration parameters */
|
||||
struct i2s_stm32_cfg {
|
||||
SPI_TypeDef *i2s;
|
||||
struct stm32_pclken pclken;
|
||||
u32_t i2s_clk_sel;
|
||||
uint32_t i2s_clk_sel;
|
||||
void (*irq_config)(struct device *dev);
|
||||
};
|
||||
|
||||
struct stream {
|
||||
s32_t state;
|
||||
int32_t state;
|
||||
struct k_sem sem;
|
||||
|
||||
const char *dma_name;
|
||||
u32_t dma_channel;
|
||||
uint32_t dma_channel;
|
||||
struct dma_config dma_cfg;
|
||||
u8_t priority;
|
||||
uint8_t priority;
|
||||
bool src_addr_increment;
|
||||
bool dst_addr_increment;
|
||||
u8_t fifo_threshold;
|
||||
uint8_t fifo_threshold;
|
||||
|
||||
struct i2s_config cfg;
|
||||
struct ring_buf mem_block_queue;
|
||||
|
|
|
|||
|
|
@ -36,9 +36,9 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
|
|||
|
||||
#if __DCACHE_PRESENT == 1
|
||||
#define DCACHE_INVALIDATE(addr, size) \
|
||||
SCB_InvalidateDCache_by_Addr((u32_t *)addr, size)
|
||||
SCB_InvalidateDCache_by_Addr((uint32_t *)addr, size)
|
||||
#define DCACHE_CLEAN(addr, size) \
|
||||
SCB_CleanDCache_by_Addr((u32_t *)addr, size)
|
||||
SCB_CleanDCache_by_Addr((uint32_t *)addr, size)
|
||||
#else
|
||||
#define DCACHE_INVALIDATE(addr, size) {; }
|
||||
#define DCACHE_CLEAN(addr, size) {; }
|
||||
|
|
@ -57,9 +57,9 @@ struct queue_item {
|
|||
/* Minimal ring buffer implementation */
|
||||
struct ring_buf {
|
||||
struct queue_item *buf;
|
||||
u16_t len;
|
||||
u16_t head;
|
||||
u16_t tail;
|
||||
uint16_t len;
|
||||
uint16_t head;
|
||||
uint16_t tail;
|
||||
};
|
||||
|
||||
/* Device constant configuration parameters */
|
||||
|
|
@ -67,15 +67,15 @@ struct i2s_sam_dev_cfg {
|
|||
Ssc *regs;
|
||||
void (*irq_config)(void);
|
||||
const struct soc_gpio_pin *pin_list;
|
||||
u8_t pin_list_size;
|
||||
u8_t periph_id;
|
||||
u8_t irq_id;
|
||||
uint8_t pin_list_size;
|
||||
uint8_t periph_id;
|
||||
uint8_t irq_id;
|
||||
};
|
||||
|
||||
struct stream {
|
||||
s32_t state;
|
||||
int32_t state;
|
||||
struct k_sem sem;
|
||||
u32_t dma_channel;
|
||||
uint32_t dma_channel;
|
||||
struct dma_config dma_cfg;
|
||||
struct i2s_config cfg;
|
||||
struct ring_buf mem_block_queue;
|
||||
|
|
@ -103,9 +103,9 @@ struct i2s_sam_dev_data {
|
|||
|
||||
#define MODULO_INC(val, max) { val = (++val < max) ? val : 0; }
|
||||
|
||||
static struct device *get_dev_from_dma_channel(u32_t dma_channel);
|
||||
static void dma_rx_callback(void *, u32_t, int);
|
||||
static void dma_tx_callback(void *, u32_t, int);
|
||||
static struct device *get_dev_from_dma_channel(uint32_t dma_channel);
|
||||
static void dma_rx_callback(void *, uint32_t, int);
|
||||
static void dma_tx_callback(void *, uint32_t, int);
|
||||
static void rx_stream_disable(struct stream *, Ssc *const, struct device *);
|
||||
static void tx_stream_disable(struct stream *, Ssc *const, struct device *);
|
||||
|
||||
|
|
@ -138,7 +138,7 @@ static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
|
|||
*/
|
||||
static int queue_put(struct ring_buf *rb, void *mem_block, size_t size)
|
||||
{
|
||||
u16_t head_next;
|
||||
uint16_t head_next;
|
||||
unsigned int key;
|
||||
|
||||
key = irq_lock();
|
||||
|
|
@ -161,17 +161,17 @@ static int queue_put(struct ring_buf *rb, void *mem_block, size_t size)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int start_dma(struct device *dev_dma, u32_t channel,
|
||||
static int start_dma(struct device *dev_dma, uint32_t channel,
|
||||
struct dma_config *cfg, void *src, void *dst,
|
||||
u32_t blk_size)
|
||||
uint32_t blk_size)
|
||||
{
|
||||
struct dma_block_config blk_cfg;
|
||||
int ret;
|
||||
|
||||
(void)memset(&blk_cfg, 0, sizeof(blk_cfg));
|
||||
blk_cfg.block_size = blk_size;
|
||||
blk_cfg.source_address = (u32_t)src;
|
||||
blk_cfg.dest_address = (u32_t)dst;
|
||||
blk_cfg.source_address = (uint32_t)src;
|
||||
blk_cfg.dest_address = (uint32_t)dst;
|
||||
|
||||
cfg->head_block = &blk_cfg;
|
||||
|
||||
|
|
@ -186,7 +186,7 @@ static int start_dma(struct device *dev_dma, u32_t channel,
|
|||
}
|
||||
|
||||
/* This function is executed in the interrupt context */
|
||||
static void dma_rx_callback(void *callback_arg, u32_t channel, int status)
|
||||
static void dma_rx_callback(void *callback_arg, uint32_t channel, int status)
|
||||
{
|
||||
struct device *dev = get_dev_from_dma_channel(channel);
|
||||
const struct i2s_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
|
||||
|
|
@ -245,7 +245,7 @@ rx_disable:
|
|||
}
|
||||
|
||||
/* This function is executed in the interrupt context */
|
||||
static void dma_tx_callback(void *callback_arg, u32_t channel, int status)
|
||||
static void dma_tx_callback(void *callback_arg, uint32_t channel, int status)
|
||||
{
|
||||
struct device *dev = get_dev_from_dma_channel(channel);
|
||||
const struct i2s_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
|
||||
|
|
@ -310,11 +310,11 @@ static int set_rx_data_format(const struct i2s_sam_dev_cfg *const dev_cfg,
|
|||
Ssc *const ssc = dev_cfg->regs;
|
||||
const bool pin_rk_en = IS_ENABLED(CONFIG_I2S_SAM_SSC_0_PIN_RK_EN);
|
||||
const bool pin_rf_en = IS_ENABLED(CONFIG_I2S_SAM_SSC_0_PIN_RF_EN);
|
||||
u8_t word_size_bits = i2s_cfg->word_size;
|
||||
u8_t num_words = i2s_cfg->channels;
|
||||
u8_t fslen = 0U;
|
||||
u32_t ssc_rcmr = 0U;
|
||||
u32_t ssc_rfmr = 0U;
|
||||
uint8_t word_size_bits = i2s_cfg->word_size;
|
||||
uint8_t num_words = i2s_cfg->channels;
|
||||
uint8_t fslen = 0U;
|
||||
uint32_t ssc_rcmr = 0U;
|
||||
uint32_t ssc_rfmr = 0U;
|
||||
bool frame_clk_master = !(i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE);
|
||||
|
||||
switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
|
||||
|
|
@ -401,11 +401,11 @@ static int set_tx_data_format(const struct i2s_sam_dev_cfg *const dev_cfg,
|
|||
struct i2s_config *i2s_cfg)
|
||||
{
|
||||
Ssc *const ssc = dev_cfg->regs;
|
||||
u8_t word_size_bits = i2s_cfg->word_size;
|
||||
u8_t num_words = i2s_cfg->channels;
|
||||
u8_t fslen = 0U;
|
||||
u32_t ssc_tcmr = 0U;
|
||||
u32_t ssc_tfmr = 0U;
|
||||
uint8_t word_size_bits = i2s_cfg->word_size;
|
||||
uint8_t num_words = i2s_cfg->channels;
|
||||
uint8_t fslen = 0U;
|
||||
uint32_t ssc_tcmr = 0U;
|
||||
uint32_t ssc_tfmr = 0U;
|
||||
|
||||
switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
|
||||
|
||||
|
|
@ -483,19 +483,19 @@ static int set_tx_data_format(const struct i2s_sam_dev_cfg *const dev_cfg,
|
|||
}
|
||||
|
||||
/* Calculate number of bytes required to store a word of bit_size length */
|
||||
static u8_t get_word_size_bytes(u8_t bit_size)
|
||||
static uint8_t get_word_size_bytes(uint8_t bit_size)
|
||||
{
|
||||
u8_t byte_size_min = (bit_size + 7) / 8U;
|
||||
u8_t byte_size;
|
||||
uint8_t byte_size_min = (bit_size + 7) / 8U;
|
||||
uint8_t byte_size;
|
||||
|
||||
byte_size = (byte_size_min == 3U) ? 4 : byte_size_min;
|
||||
|
||||
return byte_size;
|
||||
}
|
||||
|
||||
static int bit_clock_set(Ssc *const ssc, u32_t bit_clk_freq)
|
||||
static int bit_clock_set(Ssc *const ssc, uint32_t bit_clk_freq)
|
||||
{
|
||||
u32_t clk_div = SOC_ATMEL_SAM_MCK_FREQ_HZ / bit_clk_freq / 2U;
|
||||
uint32_t clk_div = SOC_ATMEL_SAM_MCK_FREQ_HZ / bit_clk_freq / 2U;
|
||||
|
||||
if (clk_div == 0U || clk_div >= (1 << 12)) {
|
||||
LOG_ERR("Invalid bit clock frequency");
|
||||
|
|
@ -534,10 +534,10 @@ static int i2s_sam_configure(struct device *dev, enum i2s_dir dir,
|
|||
const struct i2s_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
|
||||
struct i2s_sam_dev_data *const dev_data = DEV_DATA(dev);
|
||||
Ssc *const ssc = dev_cfg->regs;
|
||||
u8_t num_words = i2s_cfg->channels;
|
||||
u8_t word_size_bits = i2s_cfg->word_size;
|
||||
u8_t word_size_bytes;
|
||||
u32_t bit_clk_freq;
|
||||
uint8_t num_words = i2s_cfg->channels;
|
||||
uint8_t word_size_bits = i2s_cfg->word_size;
|
||||
uint8_t word_size_bytes;
|
||||
uint32_t bit_clk_freq;
|
||||
struct stream *stream;
|
||||
int ret;
|
||||
|
||||
|
|
@ -887,7 +887,7 @@ static void i2s_sam_isr(void *arg)
|
|||
const struct i2s_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
|
||||
struct i2s_sam_dev_data *const dev_data = DEV_DATA(dev);
|
||||
Ssc *const ssc = dev_cfg->regs;
|
||||
u32_t isr_status;
|
||||
uint32_t isr_status;
|
||||
|
||||
/* Retrieve interrupt status */
|
||||
isr_status = ssc->SSC_SR & ssc->SSC_IMR;
|
||||
|
|
@ -957,7 +957,7 @@ static const struct i2s_driver_api i2s_sam_driver_api = {
|
|||
|
||||
static struct device DEVICE_NAME_GET(i2s0_sam);
|
||||
|
||||
static struct device *get_dev_from_dma_channel(u32_t dma_channel)
|
||||
static struct device *get_dev_from_dma_channel(uint32_t dma_channel)
|
||||
{
|
||||
return &DEVICE_NAME_GET(i2s0_sam);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue