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zephyr: replace zephyr integer types with C99 types

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git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-05-27 11:26:57 -05:00 • committed by Kumar Gala
commit a1b77fd589
2364 changed files with 32505 additions and 32505 deletions
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66
drivers/dma/dma_sam_xdmac.h
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@ -18,7 +18,7 @@ extern "C" {
#endif
/** DMA transfer callback */
typedef void (*dma_callback)(void *arg, u32_t channel, int error_code);
typedef void (*dma_callback)(void *arg, uint32_t channel, int error_code);
/* XDMA_MBR_UBC */
#define XDMA_UBC_NDE (0x1u << 24)
@ -40,89 +40,89 @@ typedef void (*dma_callback)(void *arg, u32_t channel, int error_code);
/** DMA channel configuration parameters */
struct sam_xdmac_channel_config {
/** Configuration Register */
u32_t cfg;
uint32_t cfg;
/** Data Stride / Memory Set Pattern Register */
u32_t ds_msp;
uint32_t ds_msp;
/** Source Microblock Stride */
u32_t sus;
uint32_t sus;
/** Destination Microblock Stride */
u32_t dus;
uint32_t dus;
/** Channel Interrupt Enable */
u32_t cie;
uint32_t cie;
};
/** DMA transfer configuration parameters */
struct sam_xdmac_transfer_config {
/** Microblock length */
u32_t ublen;
uint32_t ublen;
/** Source Address */
u32_t sa;
uint32_t sa;
/** Destination Address */
u32_t da;
uint32_t da;
/** Block length (The length of the block is (blen+1) microblocks) */
u32_t blen;
uint32_t blen;
/** Next descriptor address */
u32_t nda;
uint32_t nda;
/** Next descriptor configuration */
u32_t ndc;
uint32_t ndc;
};
/** DMA Master transfer linked list view 0 structure */
struct sam_xdmac_linked_list_desc_view0 {
/** Next Descriptor Address */
u32_t mbr_nda;
uint32_t mbr_nda;
/** Microblock Control */
u32_t mbr_ubc;
uint32_t mbr_ubc;
/** Transfer Address */
u32_t mbr_ta;
uint32_t mbr_ta;
};
/** DMA Master transfer linked list view 1 structure */
struct sam_xdmac_linked_list_desc_view1 {
/** Next Descriptor Address */
u32_t mbr_nda;
uint32_t mbr_nda;
/** Microblock Control */
u32_t mbr_ubc;
uint32_t mbr_ubc;
/** Source Address */
u32_t mbr_sa;
uint32_t mbr_sa;
/** Destination Address */
u32_t mbr_da;
uint32_t mbr_da;
};
/** DMA Master transfer linked list view 2 structure */
struct sam_xdmac_linked_list_desc_view2 {
/** Next Descriptor Address */
u32_t mbr_nda;
uint32_t mbr_nda;
/** Microblock Control */
u32_t mbr_ubc;
uint32_t mbr_ubc;
/** Source Address */
u32_t mbr_sa;
uint32_t mbr_sa;
/** Destination Address */
u32_t mbr_da;
uint32_t mbr_da;
/** Configuration Register */
u32_t mbr_cfg;
uint32_t mbr_cfg;
};
/** DMA Master transfer linked list view 3 structure */
struct sam_xdmac_linked_list_desc_view3 {
/** Next Descriptor Address */
u32_t mbr_nda;
uint32_t mbr_nda;
/** Microblock Control */
u32_t mbr_ubc;
uint32_t mbr_ubc;
/** Source Address */
u32_t mbr_sa;
uint32_t mbr_sa;
/** Destination Address */
u32_t mbr_da;
uint32_t mbr_da;
/** Configuration Register */
u32_t mbr_cfg;
uint32_t mbr_cfg;
/** Block Control */
u32_t mbr_bc;
uint32_t mbr_bc;
/** Data Stride */
u32_t mbr_ds;
uint32_t mbr_ds;
/** Source Microblock Stride */
u32_t mbr_sus;
uint32_t mbr_sus;
/** Destination Microblock Stride */
u32_t mbr_dus;
uint32_t mbr_dus;
};
#ifdef __cplusplus