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zephyr: replace zephyr integer types with C99 types

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git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-05-27 11:26:57 -05:00 • committed by Kumar Gala
commit a1b77fd589
2364 changed files with 32505 additions and 32505 deletions
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58
drivers/adc/adc_sam0.c
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@ -28,16 +28,16 @@ struct adc_sam0_data {
struct adc_context ctx;
struct device *dev;
u16_t *buffer;
uint16_t *buffer;
/*
* Saved initial start, so we can reset the advances we've done
* if required
*/
u16_t *repeat_buffer;
uint16_t *repeat_buffer;
#ifdef ADC_SAM0_REFERENCE_GLITCH
u8_t reference_changed;
uint8_t reference_changed;
#endif
};
@ -45,15 +45,15 @@ struct adc_sam0_cfg {
Adc *regs;
#ifdef MCLK
u32_t mclk_mask;
u32_t gclk_mask;
u16_t gclk_id;
uint32_t mclk_mask;
uint32_t gclk_mask;
uint16_t gclk_id;
#else
u32_t gclk;
uint32_t gclk;
#endif
u32_t freq;
u16_t prescaler;
uint32_t freq;
uint16_t prescaler;
void (*config_func)(struct device *dev);
};
@ -75,10 +75,10 @@ static void wait_synchronization(Adc *const adc)
}
static int adc_sam0_acquisition_to_clocks(struct device *dev,
u16_t acquisition_time)
uint16_t acquisition_time)
{
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
u64_t scaled_acq;
uint64_t scaled_acq;
switch (ADC_ACQ_TIME_UNIT(acquisition_time)) {
case ADC_ACQ_TIME_TICKS:
@ -88,11 +88,11 @@ static int adc_sam0_acquisition_to_clocks(struct device *dev,
return (int)ADC_ACQ_TIME_VALUE(acquisition_time) - 1;
case ADC_ACQ_TIME_MICROSECONDS:
scaled_acq = (u64_t)ADC_ACQ_TIME_VALUE(acquisition_time) *
scaled_acq = (uint64_t)ADC_ACQ_TIME_VALUE(acquisition_time) *
1000000U;
break;
case ADC_ACQ_TIME_NANOSECONDS:
scaled_acq = (u64_t)ADC_ACQ_TIME_VALUE(acquisition_time) *
scaled_acq = (uint64_t)ADC_ACQ_TIME_VALUE(acquisition_time) *
1000U;
break;
default:
@ -125,7 +125,7 @@ static int adc_sam0_channel_setup(struct device *dev,
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
Adc *const adc = cfg->regs;
int retval;
u8_t SAMPCTRL = 0;
uint8_t SAMPCTRL = 0;
if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
retval = adc_sam0_acquisition_to_clocks(dev,
@ -142,7 +142,7 @@ static int adc_sam0_channel_setup(struct device *dev,
wait_synchronization(adc);
u8_t REFCTRL;
uint8_t REFCTRL;
switch (channel_cfg->reference) {
case ADC_REF_INTERNAL:
@ -189,7 +189,7 @@ static int adc_sam0_channel_setup(struct device *dev,
}
u32_t INPUTCTRL = 0;
uint32_t INPUTCTRL = 0;
switch (channel_cfg->gain) {
case ADC_GAIN_1:
@ -316,11 +316,11 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx,
}
static int check_buffer_size(const struct adc_sequence *sequence,
u8_t active_channels)
uint8_t active_channels)
{
size_t needed_buffer_size;
needed_buffer_size = active_channels * sizeof(u16_t);
needed_buffer_size = active_channels * sizeof(uint16_t);
if (sequence->options) {
needed_buffer_size *= (1U + sequence->options->extra_samplings);
}
@ -434,11 +434,11 @@ static void adc_sam0_isr(void *arg)
struct adc_sam0_data *data = DEV_DATA(dev);
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev);
Adc *const adc = cfg->regs;
u16_t result;
uint16_t result;
adc->INTFLAG.reg = ADC_INTFLAG_MASK;
result = (u16_t)(adc->RESULT.reg);
result = (uint16_t)(adc->RESULT.reg);
#ifdef ADC_SAM0_REFERENCE_GLITCH
if (data->reference_changed) {
@ -535,25 +535,25 @@ static const struct adc_driver_api adc_sam0_api = {
#define ADC_SAM0_BIASCOMP_SHIFT(n) \
(ADC0_FUSES_BIASCOMP_Pos + DT_INST_PROP(n, calib_offset))
#define ADC_SAM0_BIASCOMP(n) \
(((*(u32_t *)NVMCTRL_SW0) >> ADC_SAM0_BIASCOMP_SHIFT(n)) & 0x7)
(((*(uint32_t *)NVMCTRL_SW0) >> ADC_SAM0_BIASCOMP_SHIFT(n)) & 0x7)
#define ADC_SAM0_BIASR2R_SHIFT(n) \
(ADC0_FUSES_BIASR2R_Pos + DT_INST_PROP(n, calib_offset))
#define ADC_SAM0_BIASR2R(n) \
(((*(u32_t *)NVMCTRL_SW0) >> ADC_SAM0_BIASR2R_SHIFT(n)) & 0x7)
(((*(uint32_t *)NVMCTRL_SW0) >> ADC_SAM0_BIASR2R_SHIFT(n)) & 0x7)
#define ADC_SAM0_BIASREFBUF_SHIFT(n) \
(ADC0_FUSES_BIASREFBUF_Pos + DT_INST_PROP(n, calib_offset))
#define ADC_SAM0_BIASREFBUF(n) \
(((*(u32_t *)NVMCTRL_SW0) >> ADC_SAM0_BIASREFBUF_SHIFT(n)) & 0x7)
(((*(uint32_t *)NVMCTRL_SW0) >> ADC_SAM0_BIASREFBUF_SHIFT(n)) & 0x7)
#define ADC_SAM0_CONFIGURE(n) \
do { \
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev); \
Adc * const adc = cfg->regs; \
u32_t comp = ADC_SAM0_BIASCOMP(n); \
u32_t r2r = ADC_SAM0_BIASR2R(n); \
u32_t rbuf = ADC_SAM0_BIASREFBUF(n); \
uint32_t comp = ADC_SAM0_BIASCOMP(n); \
uint32_t r2r = ADC_SAM0_BIASR2R(n); \
uint32_t rbuf = ADC_SAM0_BIASREFBUF(n); \
adc->CALIB.reg = ADC_CALIB_BIASCOMP(comp) | \
ADC_CALIB_BIASR2R(r2r) | \
ADC_CALIB_BIASREFBUF(rbuf); \
@ -572,13 +572,13 @@ do { \
const struct adc_sam0_cfg *const cfg = DEV_CFG(dev); \
Adc * const adc = cfg->regs; \
/* Linearity is split across two words */ \
u32_t lin = ((*(u32_t *)ADC_FUSES_LINEARITY_0_ADDR) & \
uint32_t lin = ((*(uint32_t *)ADC_FUSES_LINEARITY_0_ADDR) & \
ADC_FUSES_LINEARITY_0_Msk) >> \
ADC_FUSES_LINEARITY_0_Pos; \
lin |= (((*(u32_t *)ADC_FUSES_LINEARITY_1_ADDR) & \
lin |= (((*(uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) & \
ADC_FUSES_LINEARITY_1_Msk) >> \
ADC_FUSES_LINEARITY_1_Pos) << 4; \
u32_t bias = ((*(u32_t *)ADC_FUSES_BIASCAL_ADDR) & \
uint32_t bias = ((*(uint32_t *)ADC_FUSES_BIASCAL_ADDR) & \
ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos; \
adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | \
ADC_CALIB_LINEARITY_CAL(lin); \