driver: ssp: remove use of out-of-tree CONFIG_INTEL_MN
The SSP driver has odd dependency to outside definition of CONFIG_INTEL_NM. This is in practise tied to SSP hardware version and always enabled for SSP block version 1.0. Use the new SSP_IP_VER define to replace the CONFIG_INTEL_MN preprocssor checks. Also modify the board test case to remove the obsolete config setting. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
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5b29fff725
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a14ae39e74
4 changed files with 9 additions and 17 deletions
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@ -122,7 +122,7 @@ static void dai_ssp_update_bits(struct dai_intel_ssp *dp, uint32_t reg, uint32_t
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sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest);
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}
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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static int dai_ssp_gcd(int a, int b)
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{
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int aux;
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@ -411,7 +411,7 @@ static void dai_ssp_mn_release_mclk(struct dai_intel_ssp *dp, uint32_t mclk_id)
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k_spin_unlock(&mp->lock, key);
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}
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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/**
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* \brief Finds valid M/(N * SCR) values for given frequencies.
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* \param[in] freq SSP clock frequency.
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@ -1156,7 +1156,7 @@ static void dai_ssp_mclk_disable_unprepare(struct dai_intel_ssp *dp)
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static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
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{
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#if !(CONFIG_INTEL_MN)
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#if SSP_IP_VER != SSP_IP_VER_1_0
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struct dai_intel_ssp_freq_table *ft = dai_get_ftable(dp);
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#endif
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struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
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@ -1170,7 +1170,7 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
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sscr0 = sys_read32(dai_base(dp) + SSCR0);
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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bool need_ecs = false;
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/* BCLK config */
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ret = dai_ssp_mn_set_bclk(dp, dp->dai_index, ssp_plat_data->params.bclk_rate,
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@ -1191,12 +1191,10 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
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mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate;
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#endif
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#if SSP_IP_VER < CONFIG_SOC_INTEL_ACE30
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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if (need_ecs) {
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sscr0 |= SSCR0_ECS;
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}
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#endif
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#endif
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/* clock divisor is SCR + 1 */
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@ -1231,7 +1229,7 @@ static void dai_ssp_bclk_disable_unprepare(struct dai_intel_ssp *dp)
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if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE)) {
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return;
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}
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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dai_ssp_mn_release_bclk(dp, ssp_plat_data->ssp_index);
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#endif
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ssp_plat_data->clk_active &= ~SSP_CLK_BCLK_ACTIVE;
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@ -2611,7 +2609,7 @@ static int dai_ssp_probe(struct dai_intel_ssp *dp)
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dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_READY;
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dp->state[DAI_DIR_CAPTURE] = DAI_STATE_READY;
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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/* Reset M/N, power-gating functions need it */
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dai_ssp_mn_reset_bclk_divider(dp, ssp_plat_data->ssp_index);
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#endif
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@ -76,7 +76,7 @@
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#error "Missing ssp definitions"
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#endif
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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/** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly.
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* Even in the case of M/N, the actual clock source can be XTAL,
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* Audio cardinal clock (24.576) or 96 MHz PLL.
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@ -104,7 +104,7 @@ struct dai_intel_ssp_mn {
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int mclk_rate[DAI_INTEL_SSP_NUM_MCLK];
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int mclk_source_clock;
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#if CONFIG_INTEL_MN
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#if SSP_IP_VER == SSP_IP_VER_1_0
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enum bclk_source bclk_sources[(CONFIG_DAI_INTEL_SSP_NUM_BASE +
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CONFIG_DAI_INTEL_SSP_NUM_EXT)];
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int bclk_source_mn_clock;
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@ -7,8 +7,3 @@
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mainmenu "Dai SSP Test"
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source "Kconfig.zephyr"
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config INTEL_MN
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bool "Use mn divider"
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help
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Use MN divider.
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@ -1,6 +1,5 @@
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CONFIG_ZTEST=y
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CONFIG_DAI=y
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CONFIG_INTEL_MN=y
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CONFIG_DMA_DW_HOST_MASK=1
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CONFIG_HEAP_MEM_POOL_SIZE=512
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CONFIG_PM=y
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