drivers/pinmux: stm32 fix ports_enable array definition
ports_enable array holds port clock information. It is populated for all SoCs, but ports availability depends on SoCs. The way it is defined today, location of the port in the array depends on previous ports definition in SoC CMSIS files. Though, port index is always the same irrespective of previous ports availability in the SoC. This will result in incoherency between port index and clock information. Fix this by setting a bogus value if port is not defined. Return an error if bogus value is read. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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2 changed files with 17 additions and 0 deletions
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@ -16,6 +16,9 @@
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#include <gpio.h>
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/* GPIO buses definitions */
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#define STM32_PORT_NOT_AVAILABLE 0xFFFFFFFF
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#ifdef CONFIG_SOC_SERIES_STM32F0X
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#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
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@ -29,18 +29,28 @@ static const u32_t ports_enable[STM32_PORTS_MAX] = {
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STM32_PERIPH_GPIOC,
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#ifdef GPIOD_BASE
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STM32_PERIPH_GPIOD,
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#else
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STM32_PORT_NOT_AVAILABLE,
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#endif
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#ifdef GPIOE_BASE
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STM32_PERIPH_GPIOE,
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#else
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STM32_PORT_NOT_AVAILABLE,
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#endif
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#ifdef GPIOF_BASE
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STM32_PERIPH_GPIOF,
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#else
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STM32_PORT_NOT_AVAILABLE,
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#endif
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#ifdef GPIOG_BASE
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STM32_PERIPH_GPIOG,
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#else
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STM32_PORT_NOT_AVAILABLE,
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#endif
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#ifdef GPIOH_BASE
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STM32_PERIPH_GPIOH,
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#else
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STM32_PORT_NOT_AVAILABLE,
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#endif
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};
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@ -64,6 +74,10 @@ static int enable_port(u32_t port, struct device *clk)
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pclken.bus = STM32_CLOCK_BUS_GPIO;
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pclken.enr = ports_enable[port];
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if (pclken.enr == STM32_PORT_NOT_AVAILABLE) {
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return -EIO;
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}
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return clock_control_on(clk, (clock_control_subsys_t *) &pclken);
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}
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