i2c: SAM Add RTIO support for I2C
Support i2c with a seperate driver for sam twihs that implements RTIO. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This commit is contained in:
Tom Burdick
Carles Cufí
parent
a560d47078
commit
a106a5e606
4 changed files with 499 additions and 8 deletions
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@ -3,6 +3,11 @@
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zephyr_library()
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zephyr_library()
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zephyr_library_sources(i2c_common.c)
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zephyr_library_sources(i2c_common.c)
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if(CONFIG_I2C_RTIO)
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zephyr_library_sources(i2c_rtio.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIHS i2c_sam_twihs_rtio.c)
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else()
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zephyr_library_sources_ifdef(CONFIG_I2C_SHELL i2c_shell.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SHELL i2c_shell.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_BITBANG i2c_bitbang.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_BITBANG i2c_bitbang.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_TELINK_B91 i2c_b91.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_TELINK_B91 i2c_b91.c)
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@ -52,10 +57,10 @@ zephyr_library_sources_ifdef(CONFIG_I2C_STM32_V2
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i2c_ll_stm32_v2.c
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i2c_ll_stm32_v2.c
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i2c_ll_stm32.c
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i2c_ll_stm32.c
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)
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)
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endif()
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zephyr_library_sources_ifdef(CONFIG_I2C_TEST i2c_test.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_TEST i2c_test.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_RTIO i2c_rtio.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE i2c_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE i2c_handlers.c)
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add_subdirectory_ifdef(CONFIG_I2C_TARGET target)
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add_subdirectory_ifdef(CONFIG_I2C_TARGET target)
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@ -40,6 +40,11 @@ config I2C_CALLBACK
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help
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help
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API and implementations of i2c_transfer_cb.
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API and implementations of i2c_transfer_cb.
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config I2C_RTIO
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bool "I2C RTIO API"
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help
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API and implementations of I2C for RTIO
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# Include these first so that any properties (e.g. defaults) below can be
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# Include these first so that any properties (e.g. defaults) below can be
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# overridden (by defining symbols in multiple locations)
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# overridden (by defining symbols in multiple locations)
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source "drivers/i2c/Kconfig.b91"
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source "drivers/i2c/Kconfig.b91"
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@ -56,6 +61,7 @@ source "drivers/i2c/Kconfig.sbcon"
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source "drivers/i2c/Kconfig.sifive"
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source "drivers/i2c/Kconfig.sifive"
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source "drivers/i2c/Kconfig.stm32"
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source "drivers/i2c/Kconfig.stm32"
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source "drivers/i2c/Kconfig.sam0"
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source "drivers/i2c/Kconfig.sam0"
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source "drivers/i2c/Kconfig.sam_twihs"
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source "drivers/i2c/Kconfig.litex"
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source "drivers/i2c/Kconfig.litex"
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source "drivers/i2c/Kconfig.lpc11u6x"
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source "drivers/i2c/Kconfig.lpc11u6x"
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source "drivers/i2c/Kconfig.npcx"
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source "drivers/i2c/Kconfig.npcx"
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@ -88,13 +94,6 @@ config I2C_GECKO
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help
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help
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Enable the SiLabs Gecko I2C bus driver.
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Enable the SiLabs Gecko I2C bus driver.
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config I2C_SAM_TWIHS
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bool "Atmel SAM (TWIHS) I2C driver"
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default y
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depends on DT_HAS_ATMEL_SAM_I2C_TWIHS_ENABLED
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help
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Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.
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config I2C_SAM_TWIM
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config I2C_SAM_TWIM
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bool "Atmel SAM (TWIM) I2C driver"
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bool "Atmel SAM (TWIM) I2C driver"
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default y
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default y
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37
drivers/i2c/Kconfig.sam_twihs
Normal file
37
drivers/i2c/Kconfig.sam_twihs
Normal file
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@ -0,0 +1,37 @@
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# sam twihs I2C support
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# Copyright (c) 2023 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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menuconfig I2C_SAM_TWIHS
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bool "Atmel SAM (TWIHS) I2C driver"
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default y
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depends on DT_HAS_ATMEL_SAM_I2C_TWIHS_ENABLED
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help
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Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.
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if I2C_SAM_TWIHS
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if I2C_RTIO
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config I2C_SAM_TWIHS_SQ_SIZE
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int "Submission queue size for blocking calls"
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default 4
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help
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Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver
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submission queue. The queue depth determines the number of possible i2c_msg
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structs that may be in the array given to i2c_transfer. A sensible default
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is going to be 4 given the device address, register address, and a value
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to be read or written.
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config I2C_SAM_TWIHS_CQ_SIZE
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int "Completion queue size for blocking calls"
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default 4
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help
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Blocking i2c calls when I2C_RTIO is enabled are copied into a per driver
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submission queue. The queue depth determines the number of possible i2c_msg
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structs that may be in the array given to i2c_transfer. A sensible default
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is going to be 4 given the device address, register address, and a value
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to be read or written.
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endif # I2C_RTIO
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endif # I2C_SAM_TWIHS
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450
drivers/i2c/i2c_sam_twihs_rtio.c
Normal file
450
drivers/i2c/i2c_sam_twihs_rtio.c
Normal file
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@ -0,0 +1,450 @@
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/*
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* Copyright (c) 2017 Piotr Mienkowski
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* Copyright (c) 2023 Gerson Fernando Budke
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "zephyr/spinlock.h"
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#define DT_DRV_COMPAT atmel_sam_i2c_twihs
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/** @file
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* @brief I2C bus (TWIHS) driver for Atmel SAM MCU family.
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*
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* Only I2C Controller Mode with 7 bit addressing is currently supported.
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*/
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#include <errno.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
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#include <zephyr/rtio/rtio.h>
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#include <zephyr/rtio/rtio_executor_simple.h>
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(i2c_sam_twihs_rtio);
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#include "i2c-priv.h"
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/** I2C bus speed [Hz] in Standard Mode */
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#define BUS_SPEED_STANDARD_HZ 100000U
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/** I2C bus speed [Hz] in Fast Mode */
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#define BUS_SPEED_FAST_HZ 400000U
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/** I2C bus speed [Hz] in High Speed Mode */
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#define BUS_SPEED_HIGH_HZ 3400000U
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/* Maximum value of Clock Divider (CKDIV) */
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#define CKDIV_MAX 7
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/* Device constant configuration parameters */
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struct i2c_sam_twihs_dev_cfg {
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Twihs *regs;
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void (*irq_config)(void);
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uint32_t bitrate;
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const struct atmel_sam_pmc_config clock_cfg;
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const struct pinctrl_dev_config *pcfg;
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uint8_t irq_id;
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};
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/* Device run time data */
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struct i2c_sam_twihs_dev_data {
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struct k_spinlock lock;
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struct k_sem block_lock;
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struct i2c_dt_spec dt_spec;
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struct rtio_iodev iodev;
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struct rtio *r;
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struct rtio_mpsc io_q;
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struct rtio_iodev_sqe *iodev_sqe;
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const struct rtio_sqe *sqe;
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uint32_t buf_idx;
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};
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static int i2c_clk_set(Twihs *const twihs, uint32_t speed)
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{
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uint32_t ck_div = 0U;
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uint32_t cl_div;
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bool div_completed = false;
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/* From the datasheet "TWIHS Clock Waveform Generator Register"
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* T_low = ( ( CLDIV × 2^CKDIV ) + 3 ) × T_MCK
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*/
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while (!div_completed) {
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cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (speed * 2U)) - 3)
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/ (1 << ck_div);
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if (cl_div <= 255U) {
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div_completed = true;
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} else {
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ck_div++;
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}
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}
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if (ck_div > CKDIV_MAX) {
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LOG_ERR("Failed to configure I2C clock");
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return -EIO;
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}
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/* Set I2C bus clock duty cycle to 50% */
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twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div)
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return 0;
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}
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static int i2c_sam_twihs_configure(const struct device *dev, uint32_t config)
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{
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
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Twihs *const twihs = dev_cfg->regs;
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uint32_t bitrate;
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int ret;
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if (!(config & I2C_MODE_CONTROLLER)) {
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LOG_ERR("Master Mode is not enabled");
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return -EIO;
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}
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if (config & I2C_ADDR_10_BITS) {
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LOG_ERR("I2C 10-bit addressing is currently not supported");
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LOG_ERR("Please submit a patch");
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return -EIO;
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}
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/* Configure clock */
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switch (I2C_SPEED_GET(config)) {
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case I2C_SPEED_STANDARD:
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bitrate = BUS_SPEED_STANDARD_HZ;
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break;
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case I2C_SPEED_FAST:
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bitrate = BUS_SPEED_FAST_HZ;
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break;
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default:
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LOG_ERR("Unsupported I2C speed value");
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return -EIO;
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}
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/* Setup clock waveform */
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ret = i2c_clk_set(twihs, bitrate);
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if (ret < 0) {
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return ret;
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}
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/* Disable Target Mode */
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twihs->TWIHS_CR = TWIHS_CR_SVDIS;
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/* Enable Controller Mode */
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twihs->TWIHS_CR = TWIHS_CR_MSEN;
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return 0;
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}
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static void write_msg_start(Twihs *const twihs, const uint8_t *buf, const uint32_t idx,
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const uint8_t daddr)
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{
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/* Set target address. */
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twihs->TWIHS_MMR = TWIHS_MMR_DADR(daddr);
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/* Write first data byte on I2C bus */
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twihs->TWIHS_THR = buf[idx];
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/* Enable Transmit Ready and Transmission Completed interrupts */
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twihs->TWIHS_IER = TWIHS_IER_TXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
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}
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static void read_msg_start(Twihs *const twihs, const uint32_t len, const uint8_t daddr)
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{
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uint32_t twihs_cr_stop;
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/* Set target address and number of internal address bytes */
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twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(daddr);
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/* In single data byte read the START and STOP must both be set */
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twihs_cr_stop = (len == 1U) ? TWIHS_CR_STOP : 0;
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/* Enable Receive Ready and Transmission Completed interrupts */
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twihs->TWIHS_IER = TWIHS_IER_RXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
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/* Start the transfer by sending START condition */
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twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
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}
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static void i2c_sam_twihs_complete(const struct device *dev, int status);
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static void i2c_sam_twihs_start(const struct device *dev)
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{
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struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
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Twihs *const twihs = dev_cfg->regs;
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const struct rtio_sqe *const sqe = dev_data->sqe;
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struct i2c_dt_spec *dt_spec = sqe->iodev->data;
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/* Clear pending interrupts, such as NACK. */
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(void)twihs->TWIHS_SR;
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/* Set number of internal address bytes to 0, not used. */
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twihs->TWIHS_IADR = 0;
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/* Set the current index to 0 */
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dev_data->buf_idx = 0;
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switch (sqe->op) {
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case RTIO_OP_RX:
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read_msg_start(twihs, sqe->buf_len, dt_spec->addr);
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break;
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case RTIO_OP_TX:
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dev_data->buf_idx = 1;
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write_msg_start(twihs, sqe->buf, 0, dt_spec->addr);
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break;
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default:
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LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
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i2c_sam_twihs_complete(dev, -EINVAL);
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}
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}
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static void i2c_sam_twihs_next(const struct device *dev, bool completion)
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{
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struct i2c_sam_twihs_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if (!completion && data->iodev_sqe != NULL) {
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k_spin_unlock(&data->lock, key);
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return;
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}
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struct rtio_mpsc_node *next = rtio_mpsc_pop(&data->io_q);
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if (next == NULL) {
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data->iodev_sqe = NULL;
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data->sqe = NULL;
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k_spin_unlock(&data->lock, key);
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return;
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}
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data->iodev_sqe = CONTAINER_OF(next, struct rtio_iodev_sqe, q);
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data->sqe = data->iodev_sqe->sqe;
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k_spin_unlock(&data->lock, key);
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|
|
||||||
|
i2c_sam_twihs_start(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void i2c_sam_twihs_complete(const struct device *dev, int status)
|
||||||
|
{
|
||||||
|
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
|
||||||
|
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
|
||||||
|
Twihs *const twihs = dev_cfg->regs;
|
||||||
|
struct rtio_iodev_sqe *iodev_sqe = dev_data->iodev_sqe;
|
||||||
|
|
||||||
|
/* Disable all enabled interrupts */
|
||||||
|
twihs->TWIHS_IDR = twihs->TWIHS_IMR;
|
||||||
|
|
||||||
|
if (status < 0) {
|
||||||
|
rtio_iodev_sqe_err(iodev_sqe, status);
|
||||||
|
i2c_sam_twihs_next(dev, true);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dev_data->sqe->flags & RTIO_SQE_TRANSACTION) {
|
||||||
|
dev_data->sqe = rtio_spsc_next(iodev_sqe->r->sq, dev_data->sqe);
|
||||||
|
i2c_sam_twihs_start(dev);
|
||||||
|
} else {
|
||||||
|
rtio_iodev_sqe_ok(iodev_sqe, status);
|
||||||
|
i2c_sam_twihs_next(dev, true);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void i2c_sam_twihs_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
|
||||||
|
{
|
||||||
|
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
|
||||||
|
|
||||||
|
rtio_mpsc_push(&dev_data->io_q, &iodev_sqe->q);
|
||||||
|
i2c_sam_twihs_next(dev, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void i2c_sam_twihs_isr(const struct device *dev)
|
||||||
|
{
|
||||||
|
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
|
||||||
|
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
|
||||||
|
Twihs *const twihs = dev_cfg->regs;
|
||||||
|
const struct rtio_sqe *const sqe = dev_data->sqe;
|
||||||
|
uint32_t isr_status;
|
||||||
|
|
||||||
|
/* Retrieve interrupt status */
|
||||||
|
isr_status = twihs->TWIHS_SR & twihs->TWIHS_IMR;
|
||||||
|
|
||||||
|
/* Not Acknowledged */
|
||||||
|
if (isr_status & TWIHS_SR_NACK) {
|
||||||
|
i2c_sam_twihs_complete(dev, -EIO);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Byte received */
|
||||||
|
if (isr_status & TWIHS_SR_RXRDY) {
|
||||||
|
sqe->buf[dev_data->buf_idx] = twihs->TWIHS_RHR;
|
||||||
|
dev_data->buf_idx += 1;
|
||||||
|
|
||||||
|
if (dev_data->buf_idx == sqe->buf_len - 1U) {
|
||||||
|
/* Send STOP condition */
|
||||||
|
twihs->TWIHS_CR = TWIHS_CR_STOP;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Byte sent */
|
||||||
|
if (isr_status & TWIHS_SR_TXRDY) {
|
||||||
|
if (dev_data->buf_idx == sqe->buf_len) {
|
||||||
|
if (sqe->iodev_flags & RTIO_IODEV_I2C_STOP) {
|
||||||
|
/* Send STOP condition */
|
||||||
|
twihs->TWIHS_CR = TWIHS_CR_STOP;
|
||||||
|
/* Disable Transmit Ready interrupt */
|
||||||
|
twihs->TWIHS_IDR = TWIHS_IDR_TXRDY;
|
||||||
|
} else {
|
||||||
|
/* Transmission completed */
|
||||||
|
i2c_sam_twihs_complete(dev, 0);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
twihs->TWIHS_THR = sqe->buf[dev_data->buf_idx++];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Transmission completed */
|
||||||
|
if (isr_status & TWIHS_SR_TXCOMP) {
|
||||||
|
i2c_sam_twihs_complete(dev, 0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int i2c_sam_twihs_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
|
||||||
|
uint16_t addr)
|
||||||
|
{
|
||||||
|
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
|
||||||
|
struct rtio_iodev *iodev = &dev_data->iodev;
|
||||||
|
struct rtio *const r = dev_data->r;
|
||||||
|
struct rtio_sqe *sqe = NULL;
|
||||||
|
struct rtio_cqe *cqe = NULL;
|
||||||
|
int res = 0;
|
||||||
|
|
||||||
|
k_sem_take(&dev_data->block_lock, K_FOREVER);
|
||||||
|
|
||||||
|
dev_data->dt_spec.addr = addr;
|
||||||
|
|
||||||
|
sqe = i2c_rtio_copy(r, iodev, msgs, num_msgs);
|
||||||
|
if (sqe == NULL) {
|
||||||
|
LOG_ERR("Not enough submission queue entries");
|
||||||
|
res = -ENOMEM;
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
sqe->flags &= ~RTIO_SQE_TRANSACTION;
|
||||||
|
|
||||||
|
rtio_submit(r, 1);
|
||||||
|
|
||||||
|
cqe = rtio_cqe_consume(r);
|
||||||
|
__ASSERT(cqe != NULL, "Expected valid completion");
|
||||||
|
while (cqe != NULL) {
|
||||||
|
res = cqe->result;
|
||||||
|
cqe = rtio_cqe_consume(r);
|
||||||
|
}
|
||||||
|
rtio_cqe_release_all(r);
|
||||||
|
|
||||||
|
out:
|
||||||
|
k_sem_give(&dev_data->block_lock);
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int i2c_sam_twihs_initialize(const struct device *dev)
|
||||||
|
{
|
||||||
|
const struct i2c_sam_twihs_dev_cfg *const dev_cfg = dev->config;
|
||||||
|
struct i2c_sam_twihs_dev_data *const dev_data = dev->data;
|
||||||
|
Twihs *const twihs = dev_cfg->regs;
|
||||||
|
uint32_t bitrate_cfg;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* Configure interrupts */
|
||||||
|
dev_cfg->irq_config();
|
||||||
|
|
||||||
|
/* Connect pins to the peripheral */
|
||||||
|
ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable TWIHS clock in PMC */
|
||||||
|
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
|
||||||
|
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
|
||||||
|
|
||||||
|
/* Reset the module */
|
||||||
|
twihs->TWIHS_CR = TWIHS_CR_SWRST;
|
||||||
|
|
||||||
|
bitrate_cfg = i2c_map_dt_bitrate(dev_cfg->bitrate);
|
||||||
|
|
||||||
|
ret = i2c_sam_twihs_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
|
||||||
|
if (ret < 0) {
|
||||||
|
LOG_ERR("Failed to initialize %s device", dev->name);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
k_sem_init(&dev_data->block_lock, 1, 1);
|
||||||
|
dev_data->dt_spec.bus = dev;
|
||||||
|
dev_data->iodev.api = &i2c_iodev_api;
|
||||||
|
dev_data->iodev.data = &dev_data->dt_spec;
|
||||||
|
rtio_mpsc_init(&dev_data->io_q);
|
||||||
|
|
||||||
|
/* Enable module's IRQ */
|
||||||
|
irq_enable(dev_cfg->irq_id);
|
||||||
|
|
||||||
|
LOG_INF("Device %s initialized", dev->name);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct i2c_driver_api i2c_sam_twihs_driver_api = {
|
||||||
|
.configure = i2c_sam_twihs_configure,
|
||||||
|
.transfer = i2c_sam_twihs_transfer,
|
||||||
|
.iodev_submit = i2c_sam_twihs_submit,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define I2C_TWIHS_SAM_INIT(n) \
|
||||||
|
PINCTRL_DT_INST_DEFINE(n); \
|
||||||
|
static void i2c##n##_sam_irq_config(void) \
|
||||||
|
{ \
|
||||||
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
|
||||||
|
i2c_sam_twihs_isr, \
|
||||||
|
DEVICE_DT_INST_GET(n), 0); \
|
||||||
|
} \
|
||||||
|
\
|
||||||
|
RTIO_EXECUTOR_SIMPLE_DEFINE(_i2c##n##_sam_rtio_exec); \
|
||||||
|
RTIO_DEFINE(_i2c##n##_sam_rtio, \
|
||||||
|
(struct rtio_executor *)&_i2c##n##_sam_rtio_exec, \
|
||||||
|
CONFIG_I2C_SAM_TWIHS_SQ_SIZE, \
|
||||||
|
CONFIG_I2C_SAM_TWIHS_CQ_SIZE); \
|
||||||
|
\
|
||||||
|
static const struct i2c_sam_twihs_dev_cfg i2c##n##_sam_config = { \
|
||||||
|
.regs = (Twihs *)DT_INST_REG_ADDR(n), \
|
||||||
|
.irq_config = i2c##n##_sam_irq_config, \
|
||||||
|
.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
|
||||||
|
.irq_id = DT_INST_IRQN(n), \
|
||||||
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||||
|
.bitrate = DT_INST_PROP(n, clock_frequency), \
|
||||||
|
}; \
|
||||||
|
\
|
||||||
|
static struct i2c_sam_twihs_dev_data i2c##n##_sam_data = { \
|
||||||
|
.r = &_i2c##n##_sam_rtio, \
|
||||||
|
}; \
|
||||||
|
\
|
||||||
|
I2C_DEVICE_DT_INST_DEFINE(n, i2c_sam_twihs_initialize, \
|
||||||
|
NULL, \
|
||||||
|
&i2c##n##_sam_data, &i2c##n##_sam_config, \
|
||||||
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
|
||||||
|
&i2c_sam_twihs_driver_api);
|
||||||
|
|
||||||
|
DT_INST_FOREACH_STATUS_OKAY(I2C_TWIHS_SAM_INIT)
|
||||||
Loading…
Add table
Add a link
Reference in a new issue