soc/intel_adsp: Fix timing/clock register ownership on cAVS 1.8+

The wall clock timer is not (per documentation) part of the
"timestamping" register set on the DSP.  And its counter and
comparator registers work fine always.  But if the DSP isn't set as
the "owner" of the timestamp hardware, wall clock interrupts never
arrive.

Also grab the PLL ownership too, because SOF already does anyway.
While we don't have a dynamic clock driver yet, we will surely want
one soon and will needt this.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>

soc/xtensa/intel_adsp/common/soc.c

@@ -227,6 +227,19 @@ static inline void soc_set_power_and_clock(void)
 
 static int soc_init(const struct device *dev)
 {
+#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
+	/* On cAVS 1.8+, we must demand ownership of the timestamping
+	 * and clock generator registers.  Lacking the former will
+	 * prevent wall clock timer interrupts from arriving, even
+	 * though the device itself is operational.
+	 */
+	sys_write32(GENO_MDIVOSEL | GENO_DIOPTOSEL, DSP_INIT_GENO);
+	sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG,
+		    DSP_INIT_LPGPDMA(0));
+	sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG,
+		    DSP_INIT_LPGPDMA(1));
+#endif
+
 	soc_set_power_and_clock();
 	return 0;
 }