From a0851c47aa876b98190b33106d6ca28fb384523c Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Wed, 6 Mar 2019 14:33:58 +0100 Subject: [PATCH] arch: arm: introduce barriers when disabling interrupts The ARM Cortex-M 321 application note is stressing that if we disable interrupts by executing CPSID i(f), or by MSR instructions (on PRIMASK, FAULTMASK registers), there is no requirement to add barrier instructions after disabling interupts. However, in ARMv7-M (and ARMv8-M Mainline) we use BASEPRI, instead. Therefore, if we need the effect of disabling interrupts to be recongnized immediately we should add barrier instructions. This commit adds DSB and ISB barriers when disabling interrupt using BASEPRI in the generic arm _irq_lock() function as well as in the PendSV handler, where we need to access kernel globals right after the interrups are disabled. Signed-off-by: Ioannis Glaropoulos --- arch/arm/core/swap_helper.S | 1 + include/arch/arm/cortex_m/asm_inline_gcc.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/core/swap_helper.S b/arch/arm/core/swap_helper.S index a40e7720f08..7705352bfc6 100644 --- a/arch/arm/core/swap_helper.S +++ b/arch/arm/core/swap_helper.S @@ -61,6 +61,7 @@ SECTION_FUNC(TEXT, __pendsv) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 + isb /* Make the effect of disabling interrupts be realized immediately */ #else #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ diff --git a/include/arch/arm/cortex_m/asm_inline_gcc.h b/include/arch/arm/cortex_m/asm_inline_gcc.h index 3a719bd1f17..a4a79bb3fef 100644 --- a/include/arch/arm/cortex_m/asm_inline_gcc.h +++ b/include/arch/arm/cortex_m/asm_inline_gcc.h @@ -132,7 +132,8 @@ static ALWAYS_INLINE unsigned int z_arch_irq_lock(void) __asm__ volatile( "mov %1, %2;" "mrs %0, BASEPRI;" - "msr BASEPRI, %1" + "msr BASEPRI, %1;" + "isb;" : "=r"(key), "=r"(tmp) : "i"(_EXC_IRQ_DEFAULT_PRIO) : "memory");