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tests: drivers: clock_control of the stm32h5 core

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Adapt the clock scheme for testing the clock on the stm32h573i_dk.
By default the HSI is 32MHz (div-by-2).
Only scheme for pll sourced by HSI is useful at max freq of 240MHz.
Configure the usart1-console clock to be csi  to always get
a valid clock source in any usecase.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2023-05-10 16:38:58 +02:00 • committed by Carles Cufí
commit a0725f039c
5 changed files with 12 additions and 72 deletions
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14
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay
View file

@ -10,6 +10,16 @@
* be found in stm32h5.dtsi
*/
/* Keep csi on to be the usart1-console clock */
&clk_csi {
status = "okay";
};
&usart1 {
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>,
<&rcc STM32_SRC_CSI USART1_SEL(4)>;
};
&clk_hse {
status = "disabled";
/delete-property/ clock-frequency;
@ -25,10 +35,6 @@
status = "disabled";
};
&clk_csi {
status = "disabled";
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;

25
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hsi_32.overlay
View file

@ -1,25 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <2>; /* HSI RC: 64MHz, hsi_clk = 32MHz */
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(32)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hsi_100.overlay
View file

@ -1,35 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <50>;
div-p = <4>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

4
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hsi_240.overlay
View file

@ -16,8 +16,8 @@
};
&pll {
div-m = <8>;
mul-n = <120>;
div-m = <4>;
mul-n = <30>;
div-p = <2>;
div-q = <2>;
div-r = <2>;

6
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/testcase.yaml
View file

@ -9,9 +9,6 @@ tests:
drivers.stm32_clock_configuration.h5.sysclksrc_pll_csi_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hsi_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hsi_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_240.overlay"
platform_allow: stm32h573i_dk
@ -24,9 +21,6 @@ tests:
drivers.stm32_clock_configuration.h5.sysclksrc_csi4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/csi4.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_hsi_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_32.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_hse_25:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse25.overlay"
platform_allow: stm32h573i_dk