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x86: rebase priority levels

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Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.

Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.

It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.

In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
  generate_interrupt_vector_bitmap() also ensures that there are
  sufficient free vectors within a priority level.

Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2016-02-01 16:09:32 -08:00 • committed by Anas Nashif
commit 9fc3afc339
4 changed files with 28 additions and 76 deletions
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2
drivers/interrupt_controller/system_apic.c
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@ -109,7 +109,7 @@ int _SysIntVecAlloc(
{
int vector;
__ASSERT(priority < 16, "invalid priority");
__ASSERT(priority < 14, "invalid priority");
__ASSERT(irq >= 0 && irq <= HARDWARE_IRQ_LIMIT, "invalid irq line");
vector = __LocalIntVecAlloc(irq, priority);