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drivers: udc_dwc2: Add isochronous register bit defines

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Add all register bit defines necessary for isochronous transfers. Clean
up the endpoint transfer size register defines clearly separating IN and
OUT registers because they do use different bit fields. Add alternate
bit names for bits that do have different meaning based on configured
endpoint transfer type.

Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This commit is contained in:
Tomasz Moń 2024-07-31 10:38:11 +02:00 • committed by Carles Cufí
commit 9f98ee854c
2 changed files with 68 additions and 32 deletions
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86
drivers/usb/common/usb_dwc2_hw.h
View file

@ -242,6 +242,7 @@ USB_DWC2_SET_FIELD_DEFINE(grstctl_txfnum, GRSTCTL_TXFNUM)
#define USB_DWC2_GINTSTS_FETSUSP BIT(USB_DWC2_GINTSTS_FETSUSP_POS) #define USB_DWC2_GINTSTS_FETSUSP BIT(USB_DWC2_GINTSTS_FETSUSP_POS)
#define USB_DWC2_GINTSTS_INCOMPIP_POS 21UL #define USB_DWC2_GINTSTS_INCOMPIP_POS 21UL
#define USB_DWC2_GINTSTS_INCOMPIP BIT(USB_DWC2_GINTSTS_INCOMPIP_POS) #define USB_DWC2_GINTSTS_INCOMPIP BIT(USB_DWC2_GINTSTS_INCOMPIP_POS)
#define USB_DWC2_GINTSTS_INCOMPISOOUT USB_DWC2_GINTSTS_INCOMPIP
#define USB_DWC2_GINTSTS_INCOMPISOIN_POS 20UL #define USB_DWC2_GINTSTS_INCOMPISOIN_POS 20UL
#define USB_DWC2_GINTSTS_INCOMPISOIN BIT(USB_DWC2_GINTSTS_INCOMPISOIN_POS) #define USB_DWC2_GINTSTS_INCOMPISOIN BIT(USB_DWC2_GINTSTS_INCOMPISOIN_POS)
#define USB_DWC2_GINTSTS_OEPINT_POS 19UL #define USB_DWC2_GINTSTS_OEPINT_POS 19UL
@ -565,13 +566,23 @@ USB_DWC2_SET_FIELD_DEFINE(dctl_tstctl, DCTL_TSTCTL)
/* Device status register */ /* Device status register */
#define USB_DWC2_DSTS 0x0808UL #define USB_DWC2_DSTS 0x0808UL
#define USB_DWC2_DSTS_DEVLNSTS_POS 22UL
#define USB_DWC2_DSTS_DEVLNSTS_MASK (0x3UL << USB_DWC2_DSTS_DEVLNSTS_POS)
#define USB_DWC2_DSTS_SOFFN_POS 8UL
#define USB_DWC2_DSTS_SOFFN_MASK (0x3FFFUL << USB_DWC2_DSTS_SOFFN_POS)
#define USB_DWC2_DSTS_ERRTICERR_POS 3UL
#define USB_DWC2_DSTS_ERRTICERR BIT(USB_DWC2_DSTS_ERRTICERR_POS)
#define USB_DWC2_DSTS_ENUMSPD_POS 1UL #define USB_DWC2_DSTS_ENUMSPD_POS 1UL
#define USB_DWC2_DSTS_ENUMSPD_MASK (0x3UL << USB_DWC2_DSTS_ENUMSPD_POS) #define USB_DWC2_DSTS_ENUMSPD_MASK (0x3UL << USB_DWC2_DSTS_ENUMSPD_POS)
#define USB_DWC2_DSTS_ENUMSPD_HS3060 0 #define USB_DWC2_DSTS_ENUMSPD_HS3060 0
#define USB_DWC2_DSTS_ENUMSPD_FS3060 1 #define USB_DWC2_DSTS_ENUMSPD_FS3060 1
#define USB_DWC2_DSTS_ENUMSPD_LS6 2 #define USB_DWC2_DSTS_ENUMSPD_LS6 2
#define USB_DWC2_DSTS_ENUMSPD_FS48 3 #define USB_DWC2_DSTS_ENUMSPD_FS48 3
#define USB_DWC2_DSTS_SUSPSTS_POS 0UL
#define USB_DWC2_DSTS_SUSPSTS BIT(USB_DWC2_DSTS_SUSPSTS_POS)
USB_DWC2_GET_FIELD_DEFINE(dsts_devlnsts, DSTS_DEVLNSTS)
USB_DWC2_GET_FIELD_DEFINE(dsts_soffn, DSTS_SOFFN)
USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD) USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD)
/* Device all endpoints interrupt registers */ /* Device all endpoints interrupt registers */
@ -622,8 +633,10 @@ USB_DWC2_SET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN)
#define USB_DWC2_DEPCTL_EPDIS BIT(USB_DWC2_DEPCTL_EPDIS_POS) #define USB_DWC2_DEPCTL_EPDIS BIT(USB_DWC2_DEPCTL_EPDIS_POS)
#define USB_DWC2_DEPCTL_SETD1PID_POS 29UL #define USB_DWC2_DEPCTL_SETD1PID_POS 29UL
#define USB_DWC2_DEPCTL_SETD1PID BIT(USB_DWC2_DEPCTL_SETD1PID_POS) #define USB_DWC2_DEPCTL_SETD1PID BIT(USB_DWC2_DEPCTL_SETD1PID_POS)
#define USB_DWC2_DEPCTL_SETODDFR USB_DWC2_DEPCTL_SETD1PID
#define USB_DWC2_DEPCTL_SETD0PID_POS 28UL #define USB_DWC2_DEPCTL_SETD0PID_POS 28UL
#define USB_DWC2_DEPCTL_SETD0PID BIT(USB_DWC2_DEPCTL_SETD0PID_POS) #define USB_DWC2_DEPCTL_SETD0PID BIT(USB_DWC2_DEPCTL_SETD0PID_POS)
#define USB_DWC2_DEPCTL_SETEVENFR USB_DWC2_DEPCTL_SETD0PID
#define USB_DWC2_DEPCTL_SNAK_POS 27UL #define USB_DWC2_DEPCTL_SNAK_POS 27UL
#define USB_DWC2_DEPCTL_SNAK BIT(USB_DWC2_DEPCTL_SNAK_POS) #define USB_DWC2_DEPCTL_SNAK BIT(USB_DWC2_DEPCTL_SNAK_POS)
#define USB_DWC2_DEPCTL_CNAK_POS 26UL #define USB_DWC2_DEPCTL_CNAK_POS 26UL
@ -730,44 +743,67 @@ USB_DWC2_SET_FIELD_DEFINE(depctl_mps, DEPCTL_MPS)
#define USB_DWC2_DOEPINT_XFERCOMPL_POS 0UL #define USB_DWC2_DOEPINT_XFERCOMPL_POS 0UL
#define USB_DWC2_DOEPINT_XFERCOMPL BIT(USB_DWC2_DOEPINT_XFERCOMPL_POS) #define USB_DWC2_DOEPINT_XFERCOMPL BIT(USB_DWC2_DOEPINT_XFERCOMPL_POS)
/* /* Device IN control endpoint transfer size register */
* Device IN/OUT control endpoint transfer size register
*/
#define USB_DWC2_DIEPTSIZ0 0x0910UL #define USB_DWC2_DIEPTSIZ0 0x0910UL
#define USB_DWC2_DIEPTSIZ0_PKTCNT_POS 19UL
#define USB_DWC2_DIEPTSIZ0_PKTCNT_MASK (0x3UL << USB_DWC2_DIEPTSIZ0_PKTCNT_POS)
#define USB_DWC2_DIEPTSIZ0_XFERSIZE_POS 0UL
#define USB_DWC2_DIEPTSIZ0_XFERSIZE_MASK 0x7FUL
USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_pktcnt, DIEPTSIZ0_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DIEPTSIZ0_XFERSIZE)
/* Device OUT control endpoint transfer size register */
#define USB_DWC2_DOEPTSIZ0 0x0B10UL #define USB_DWC2_DOEPTSIZ0 0x0B10UL
#define USB_DWC2_DOEPTSIZ0_SUPCNT_POS 29UL #define USB_DWC2_DOEPTSIZ0_SUPCNT_POS 29UL
#define USB_DWC2_DOEPTSIZ0_SUPCNT_MASK (0x3UL << USB_DWC2_DOEPTSIZ0_SUPCNT_POS) #define USB_DWC2_DOEPTSIZ0_SUPCNT_MASK (0x3UL << USB_DWC2_DOEPTSIZ0_SUPCNT_POS)
#define USB_DWC2_DOEPTSIZ0_PKTCNT_POS 19UL #define USB_DWC2_DOEPTSIZ0_PKTCNT_POS 19UL
#define USB_DWC2_DOEPTSIZ0_PKTCNT_MASK (0x1UL << USB_DWC2_DOEPTSIZ0_PKTCNT_POS) #define USB_DWC2_DOEPTSIZ0_PKTCNT_MASK (0x1UL << USB_DWC2_DOEPTSIZ0_PKTCNT_POS)
#define USB_DWC2_DIEPTSIZ0_PKTCNT_POS 19UL #define USB_DWC2_DOEPTSIZ0_XFERSIZE_POS 0UL
#define USB_DWC2_DIEPTSIZ0_PKTCNT_MASK (0x3UL << USB_DWC2_DIEPTSIZ0_PKTCNT_POS) #define USB_DWC2_DOEPTSIZ0_XFERSIZE_MASK 0x7FUL
#define USB_DWC2_DEPTSIZ0_XFERSIZE_POS 0UL
#define USB_DWC2_DEPTSIZ0_XFERSIZE_MASK 0x7FUL
USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_supcnt, DOEPTSIZ0_SUPCNT) USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_supcnt, DOEPTSIZ0_SUPCNT)
USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_pktcnt, DOEPTSIZ0_PKTCNT) USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_pktcnt, DOEPTSIZ0_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_xfersize, DEPTSIZ0_XFERSIZE) USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_xfersize, DOEPTSIZ0_XFERSIZE)
USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_pktcnt, DIEPTSIZ0_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DEPTSIZ0_XFERSIZE)
/* /*
* Device IN/OUT endpoint transfer size register * Device IN endpoint transfer size register
* IN at offsets 0x0910 + (0x20 * n), n = 1 .. x, * at offsets 0x0910 + (0x20 * n), n = 1 .. x
* OUT at offsets 0x0B10 + (0x20 * n), n = 1 .. x
*/ */
#define USB_DWC2_DEPTSIZN_MC_POS 29UL #define USB_DWC2_DIEPTSIZN_MC_POS 29UL
#define USB_DWC2_DEPTSIZN_MC_MASK (0x3UL << USB_DWC2_DEPTSIZN_MC_POS) #define USB_DWC2_DIEPTSIZN_MC_MASK (0x3UL << USB_DWC2_DIEPTSIZN_MC_POS)
#define USB_DWC2_DEPTSIZN_PKTCNT_POS 19UL #define USB_DWC2_DIEPTSIZN_PKTCNT_POS 19UL
#define USB_DWC2_DEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DEPTSIZN_PKTCNT_POS) #define USB_DWC2_DIEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DIEPTSIZN_PKTCNT_POS)
#define USB_DWC2_DEPTSIZN_XFERSIZE_POS 0UL #define USB_DWC2_DIEPTSIZN_XFERSIZE_POS 0UL
#define USB_DWC2_DEPTSIZN_XFERSIZE_MASK 0x7FFFFUL #define USB_DWC2_DIEPTSIZN_XFERSIZE_MASK 0x7FFFFUL
USB_DWC2_GET_FIELD_DEFINE(deptsizn_mc, DEPTSIZN_MC) USB_DWC2_GET_FIELD_DEFINE(dieptsizn_mc, DIEPTSIZN_MC)
USB_DWC2_GET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT) USB_DWC2_GET_FIELD_DEFINE(dieptsizn_pktcnt, DIEPTSIZN_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE) USB_DWC2_GET_FIELD_DEFINE(dieptsizn_xfersize, DIEPTSIZN_XFERSIZE)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_mc, DEPTSIZN_MC) USB_DWC2_SET_FIELD_DEFINE(dieptsizn_mc, DIEPTSIZN_MC)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT) USB_DWC2_SET_FIELD_DEFINE(dieptsizn_pktcnt, DIEPTSIZN_PKTCNT)
USB_DWC2_SET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE) USB_DWC2_SET_FIELD_DEFINE(dieptsizn_xfersize, DIEPTSIZN_XFERSIZE)
/*
* Device OUT endpoint transfer size register
* at offsets 0x0B10 + (0x20 * n), n = 1 .. x
*/
#define USB_DWC2_DOEPTSIZN_RXDPID_POS 29UL
#define USB_DWC2_DOEPTSIZN_RXDPID_MASK (0x3UL << USB_DWC2_DOEPTSIZN_RXDPID_POS)
#define USB_DWC2_DOEPTSIZN_RXDPID_MDATA 3
#define USB_DWC2_DOEPTSIZN_RXDPID_DATA1 2
#define USB_DWC2_DOEPTSIZN_RXDPID_DATA2 1
#define USB_DWC2_DOEPTSIZN_RXDPID_DATA0 0
#define USB_DWC2_DOEPTSIZN_PKTCNT_POS 19UL
#define USB_DWC2_DOEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DOEPTSIZN_PKTCNT_POS)
#define USB_DWC2_DOEPTSIZN_XFERSIZE_POS 0UL
#define USB_DWC2_DOEPTSIZN_XFERSIZE_MASK 0x7FFFFUL
USB_DWC2_GET_FIELD_DEFINE(doeptsizn_rxdpid, DOEPTSIZN_RXDPID)
USB_DWC2_GET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
USB_DWC2_SET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT)
USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
/* /*
* Device IN/OUT endpoint transfer size register * Device IN/OUT endpoint transfer size register

14
drivers/usb/udc/udc_dwc2.c
View file

@ -373,9 +373,9 @@ static int dwc2_tx_fifo_write(const struct device *dev,
key = irq_lock(); key = irq_lock();
/* Set number of packets and transfer size */ /* Set number of packets and transfer size */
sys_write32((is_periodic ? usb_dwc2_set_deptsizn_mc(1 + addnl) : 0) | sys_write32((is_periodic ? usb_dwc2_set_dieptsizn_mc(1 + addnl) : 0) |
usb_dwc2_set_deptsizn_pktcnt(pktcnt) | usb_dwc2_set_dieptsizn_pktcnt(pktcnt) |
usb_dwc2_set_deptsizn_xfersize(len), dieptsiz_reg); usb_dwc2_set_dieptsizn_xfersize(len), dieptsiz_reg);
if (priv->bufferdma) { if (priv->bufferdma) {
if (!dwc2_dma_buffer_ok_to_use(dev, buf->data, len, cfg->mps)) { if (!dwc2_dma_buffer_ok_to_use(dev, buf->data, len, cfg->mps)) {
@ -505,8 +505,8 @@ static void dwc2_prep_rx(const struct device *dev, struct net_buf *buf,
xfersize = dwc2_rx_xfer_size(priv, cfg, buf); xfersize = dwc2_rx_xfer_size(priv, cfg, buf);
pktcnt = DIV_ROUND_UP(xfersize, udc_mps_ep_size(cfg)); pktcnt = DIV_ROUND_UP(xfersize, udc_mps_ep_size(cfg));
doeptsiz = usb_dwc2_set_deptsizn_pktcnt(pktcnt) | doeptsiz = usb_dwc2_set_doeptsizn_pktcnt(pktcnt) |
usb_dwc2_set_deptsizn_xfersize(xfersize); usb_dwc2_set_doeptsizn_xfersize(xfersize);
if (cfg->addr == USB_CONTROL_EP_OUT) { if (cfg->addr == USB_CONTROL_EP_OUT) {
/* Use 1 to allow 8 byte long buffers for SETUP data */ /* Use 1 to allow 8 byte long buffers for SETUP data */
doeptsiz |= (1 << USB_DWC2_DOEPTSIZ0_SUPCNT_POS); doeptsiz |= (1 << USB_DWC2_DOEPTSIZ0_SUPCNT_POS);
@ -892,7 +892,7 @@ static inline void dwc2_handle_rxflvl(const struct device *dev)
/* Prepare next read only when transfer finished */ /* Prepare next read only when transfer finished */
doeptsiz = sys_read32((mem_addr_t)&base->out_ep[evt.ep].doeptsiz); doeptsiz = sys_read32((mem_addr_t)&base->out_ep[evt.ep].doeptsiz);
if (usb_dwc2_get_deptsizn_xfersize(doeptsiz) == 0) { if (usb_dwc2_get_doeptsizn_xfersize(doeptsiz) == 0) {
dwc2_prep_rx(dev, buf, ep_cfg, 0); dwc2_prep_rx(dev, buf, ep_cfg, 0);
} }
} else { } else {
@ -1001,7 +1001,7 @@ static inline void dwc2_handle_out_xfercompl(const struct device *dev,
* every byte stored. * every byte stored.
*/ */
evt.bcnt = dwc2_rx_xfer_size(priv, ep_cfg, buf) - evt.bcnt = dwc2_rx_xfer_size(priv, ep_cfg, buf) -
usb_dwc2_get_deptsizn_xfersize(doeptsiz); usb_dwc2_get_doeptsizn_xfersize(doeptsiz);
if (priv->bufferdma) { if (priv->bufferdma) {
sys_cache_data_invd_range(buf->data, evt.bcnt); sys_cache_data_invd_range(buf->data, evt.bcnt);