diff --git a/drivers/spi/spi_litespi.c b/drivers/spi/spi_litespi.c
index 8ae3abed6dd..f224a2754cb 100644
--- a/drivers/spi/spi_litespi.c
+++ b/drivers/spi/spi_litespi.c
@@ -68,14 +68,14 @@ static int spi_config(const struct spi_config *config, uint16_t *control)
 
 	/* Set Loopback */
 	if (config->operation & SPI_MODE_LOOP) {
-		litex_write8(SPI_ENABLE, SPI_LOOPBACK_REG);
+		litex_write8(SPI_ENABLE, SPI_LOOPBACK_ADDR);
 	}
 	/* Set word size */
 	*control = (uint16_t) (SPI_WORD_SIZE_GET(config->operation)
 			<< POSITION_WORD_SIZE);
 	/* Write configurations */
-	litex_write8(cs, SPI_CS_REG);
-	litex_write16(*control, SPI_CONTROL_REG);
+	litex_write8(cs, SPI_CS_ADDR);
+	litex_write16(*control, SPI_CONTROL_ADDR);
 
 	return 0;
 }
@@ -84,18 +84,18 @@ static void spi_litespi_send(const struct device *dev, uint8_t frame,
 		             uint16_t control)
 {
 	/* Write frame to register */
-	litex_write8(frame, SPI_MOSI_DATA_REG);
+	litex_write8(frame, SPI_MOSI_DATA_ADDR);
 	/* Start the transfer */
-	litex_write16(control | SPI_ENABLE, SPI_CONTROL_REG);
+	litex_write16(control | SPI_ENABLE, SPI_CONTROL_ADDR);
 	/* Wait until the transfer ends */
-	while (!(litex_read8(SPI_STATUS_REG)))
+	while (!(litex_read8(SPI_STATUS_ADDR)))
 		;
 }
 
 static uint8_t spi_litespi_recv(void)
 {
     /* Return data inside MISO register */
-	return litex_read8(SPI_MISO_DATA_REG);
+	return litex_read8(SPI_MISO_DATA_ADDR);
 }
 
 static void spi_litespi_xfer(const struct device *dev,
@@ -158,7 +158,7 @@ static int spi_litespi_transceive_async(const struct device *dev,
 static int spi_litespi_release(const struct device *dev,
 			       const struct spi_config *config)
 {
-	if (!(litex_read8(SPI_STATUS_REG))) {
+	if (!(litex_read8(SPI_STATUS_ADDR))) {
 		return -EBUSY;
 	}
 	return 0;
diff --git a/drivers/spi/spi_litespi.h b/drivers/spi/spi_litespi.h
index 4e423986ee2..9f6bb230c46 100644
--- a/drivers/spi/spi_litespi.h
+++ b/drivers/spi/spi_litespi.h
@@ -13,13 +13,13 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/spi.h>
 
-#define SPI_BASE_ADDR DT_INST_REG_ADDR(0)
-#define SPI_CONTROL_REG SPI_BASE_ADDR
-#define SPI_STATUS_REG (SPI_BASE_ADDR + 0x08)
-#define SPI_MOSI_DATA_REG (SPI_BASE_ADDR + 0x0c)
-#define SPI_MISO_DATA_REG (SPI_BASE_ADDR + 0x10)
-#define SPI_CS_REG (SPI_BASE_ADDR + 0x14)
-#define SPI_LOOPBACK_REG (SPI_BASE_ADDR + 0x18)
+#define SPI_BASE_ADDR		DT_INST_REG_ADDR(0)
+#define SPI_CONTROL_ADDR	DT_INST_REG_ADDR_BY_NAME(0, control)
+#define SPI_STATUS_ADDR		DT_INST_REG_ADDR_BY_NAME(0, status)
+#define SPI_MOSI_DATA_ADDR	DT_INST_REG_ADDR_BY_NAME(0, mosi)
+#define SPI_MISO_DATA_ADDR	DT_INST_REG_ADDR_BY_NAME(0, miso)
+#define SPI_CS_ADDR		DT_INST_REG_ADDR_BY_NAME(0, cs)
+#define SPI_LOOPBACK_ADDR	DT_INST_REG_ADDR_BY_NAME(0, loopback)
 
 #define POSITION_WORD_SIZE 8
 #define SPI_MAX_CS_SIZE 0x100
diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi
index aa7ee448fef..2114b1b30ce 100644
--- a/dts/riscv/riscv32-litex-vexriscv.dtsi
+++ b/dts/riscv/riscv32-litex-vexriscv.dtsi
@@ -67,10 +67,18 @@
 		};
 		spi0: spi@e0002000 {
 			compatible = "litex,spi";
-			interrupt-parent = <&intc0>;
-			interrupts = <5 0>;
-			reg = <0xe0002000 0x34>;
-			reg-names = "control";
+			reg = <0xe0002000 0x4
+				0xe0002004 0x4
+				0xe0002008 0x4
+				0xe000200c 0x4
+				0xe0002010 0x4
+				0xe0002014 0x4>;
+			reg-names = "control",
+				"status",
+				"mosi",
+				"miso",
+				"cs",
+				"loopback";
 			label = "spi0";
 			status = "disabled";
 			#address-cells = <1>;