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boards: nrf54h20: define FLPR memory layout within RAM21 region

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Define the FLPR memory layout:

- 46K for code data
- 1K/1K for IPC between cpuapp/cpuflpr

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-06-27 17:03:08 +02:00 • committed by Carles Cufí
commit 9e7b055f63
1 changed files with 16 additions and 0 deletions
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16
boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi
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@ -93,6 +93,10 @@
};
};
/*
* NOTE: perm-execute is not required as FLPR has a direct
* bridge with RAM21, bypassing MPC.
*/
ram21_region: memory@2f890000 {
compatible = "nordic,owned-memory";
status = "disabled";
@ -104,6 +108,18 @@
#size-cells = <1>;
ranges = <0x0 0x2f890000 0x10000>;
cpuflpr_code_data: memory@0 {
reg = <0x0 DT_SIZE_K(46)>;
};
cpuapp_cpuflpr_ipc_shm: memory@b800 {
reg = <0xb800 DT_SIZE_K(1)>;
};
cpuflpr_cpuapp_ipc_shm: memory@bc00 {
reg = <0xbc00 DT_SIZE_K(1)>;
};
dma_fast_region: memory@c000 {
compatible = "zephyr,memory-region";
reg = <0xc000 DT_SIZE_K(16)>;