diff --git a/soc/arm/atmel_sam/samv71/CMakeLists.txt b/soc/arm/atmel_sam/samv71/CMakeLists.txt new file mode 100644 index 00000000000..0ad494174dd --- /dev/null +++ b/soc/arm/atmel_sam/samv71/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + soc_config.c + ) diff --git a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series new file mode 100644 index 00000000000..e9cda38c0da --- /dev/null +++ b/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series @@ -0,0 +1,98 @@ +# Atmel SAM V71 MCU series configuration options + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMV71 + +config SOC_SERIES + default "samv71" + +config SOC_PART_NUMBER + default "samv71q21" if SOC_PART_NUMBER_SAMV71Q21 + default "samv71q20" if SOC_PART_NUMBER_SAMV71Q20 + default "samv71q19" if SOC_PART_NUMBER_SAMV71Q19 + default "samv71n21" if SOC_PART_NUMBER_SAMV71N21 + default "samv71n20" if SOC_PART_NUMBER_SAMV71N20 + default "samv71n19" if SOC_PART_NUMBER_SAMV71N19 + default "samv71j21" if SOC_PART_NUMBER_SAMV71J21 + default "samv71j20" if SOC_PART_NUMBER_SAMV71J20 + default "samv71j19" if SOC_PART_NUMBER_SAMV71J19 + default "samv71q21b" if SOC_PART_NUMBER_SAMV71Q21B + default "samv71q20b" if SOC_PART_NUMBER_SAMV71Q20B + default "samv71q19b" if SOC_PART_NUMBER_SAMV71Q19B + default "samv71n21b" if SOC_PART_NUMBER_SAMV71N21B + default "samv71n20b" if SOC_PART_NUMBER_SAMV71N20B + default "samv71n19b" if SOC_PART_NUMBER_SAMV71N19B + default "samv71j21b" if SOC_PART_NUMBER_SAMV71J21B + default "samv71j20b" if SOC_PART_NUMBER_SAMV71J20B + default "samv71j19b" if SOC_PART_NUMBER_SAMV71J19B + +# +# SAM V71 family has in total 71 peripherals capable of generating interrupts +# for the revision A and 74 for the revision B (not all Peripheral Identifiers +# are used). +# +config NUM_IRQS + default 74 if SOC_ATMEL_SAMV71_REVB + default 71 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 300000000 + +# Configure default device drivers. If a feature is supported by more than one +# device driver the default configuration will be placed in the board defconfig +# file. + +if DMA +config DMA_SAM_XDMAC + default y +endif # DMA + +if GPIO +config GPIO_SAM + default y +endif # GPIO + +if ADC +config ADC_SAM_AFEC + default y +endif # ADC + +if I2C +config I2C_SAM_TWIHS + default y +endif # I2C + +if I2S +config I2S_SAM_SSC + default y +endif # I2S + +if SPI +config SPI_SAM + default y +endif # SPI + +if USB +config USB_DC_SAM + default y +endif # USB + +if ENTROPY_GENERATOR +config ENTROPY_SAM_RNG + default y +endif # ENTROPY_GENERATOR + +if FLASH +config SOC_FLASH_SAM + default y +endif # FLASH + +if PWM +config PWM_SAM + default y +endif # PWM + +endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/Kconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.series new file mode 100644 index 00000000000..e34ca533f6d --- /dev/null +++ b/soc/arm/atmel_sam/samv71/Kconfig.series @@ -0,0 +1,23 @@ +# Atmel SAM V71 MCU series + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMV71 + bool "Atmel SAMV71 MCU" + select CPU_CORTEX_M7 + select SOC_FAMILY_SAM + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_CORTEX_M_HAS_DWT + select ASF + select XIP + select CPU_HAS_ARM_MPU + select ARM_MPU + select HAS_SWO + help + Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. + Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, + SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, + SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, + SAMV71Q20B, SAMV71Q21B diff --git a/soc/arm/atmel_sam/samv71/Kconfig.soc b/soc/arm/atmel_sam/samv71/Kconfig.soc new file mode 100644 index 00000000000..c8e7d60438c --- /dev/null +++ b/soc/arm/atmel_sam/samv71/Kconfig.soc @@ -0,0 +1,168 @@ +# Atmel SAM V71 MCU series + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAMV71 MCU Selection" + depends on SOC_SERIES_SAMV71 + + config SOC_PART_NUMBER_SAMV71Q21 + bool "SAMV71Q21" + + config SOC_PART_NUMBER_SAMV71Q20 + bool "SAMV71Q20" + + config SOC_PART_NUMBER_SAMV71Q19 + bool "SAMV71Q19" + + config SOC_PART_NUMBER_SAMV71N21 + bool "SAMV71N21" + + config SOC_PART_NUMBER_SAMV71N20 + bool "SAMV71N20" + + config SOC_PART_NUMBER_SAMV71N19 + bool "SAMV71N19" + + config SOC_PART_NUMBER_SAMV71J21 + bool "SAMV71J21" + + config SOC_PART_NUMBER_SAMV71J20 + bool "SAMV71J20" + + config SOC_PART_NUMBER_SAMV71J19 + bool "SAMV71J19" + + config SOC_PART_NUMBER_SAMV71Q21B + bool "SAMV71Q21B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71Q20B + bool "SAMV71Q20B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71Q19B + bool "SAMV71Q19B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71N21B + bool "SAMV71N21B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71N20B + bool "SAMV71N20B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71N19B + bool "SAMV71N19B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71J21B + bool "SAMV71J21B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71J20B + bool "SAMV71J20B" + select SOC_ATMEL_SAMV71_REVB + + config SOC_PART_NUMBER_SAMV71J19B + bool "SAMV71J19B" + select SOC_ATMEL_SAMV71_REVB +endchoice + +if SOC_SERIES_SAMV71 + +config SOC_ATMEL_SAMV71_REVB + bool + +config SOC_ATMEL_SAMV71_EXT_SLCK + bool "Use external crystal oscillator for slow clock" + help + Say y if you want to use external 32 kHz crystal + oscillator to drive the slow clock. Note that this + adds a few seconds to boot time, as the crystal + needs to stabilize after power-up. + + Says n if you do not need accurate and precise timers. + The slow clock will be driven by the internal fast + RC oscillator running at 32 kHz. + +config SOC_ATMEL_SAMV71_EXT_MAINCK + bool "Use external crystal oscillator for main clock" + help + The main clock is being used to drive the PLL, and + thus driving the processor clock. + + Say y if you want to use external crystal oscillator + to drive the main clock. Note that this adds about + a second to boot time, as the crystal needs to + stabilize after power-up. + + The crystal used here can be from 3 to 20 MHz. + + Says n here will use the internal fast RC oscillator + running at 12 MHz. + +config SOC_ATMEL_SAMV71_MDIV + int "MDIV" + default 2 + range 1 4 + help + This divisor defines a ratio between processor clock (HCLK) + and master clock (MCK): + MCK = HCLK / MDIV + +config SOC_ATMEL_SAMV71_PLLA_MULA + int "PLL MULA" + default 24 + range 1 62 + help + This is the multiplier MULA used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + Setting MULA=0 would disable PLL at boot, this is currently + not supported. + + With default of MULA == 24, and DIVA == 1, + PLL is running at 25 times the main clock frequency. + +config SOC_ATMEL_SAMV71_PLLA_DIVA + int "PLL DIVA" + default 1 + range 1 255 + help + This is the divider DIVA used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + Setting DIVA=0 would disable PLL at boot, this is currently + not supported. + + With default of MULA == 24, and DIVA == 1, + PLL is running at 25 times the main clock frequency. + +config SOC_ATMEL_SAMV71_WAIT_MODE + bool "Go to Wait mode instead of Sleep mode" + depends on SOC_ATMEL_SAMV71_EXT_MAINCK + default y if DEBUG + help + For JTAG debugging CPU clock (HCLK) should not stop. In order + to achieve this, make CPU go to Wait mode instead of Sleep + mode while using external crystal oscillator for main clock. + +config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN + bool "Disable ERASE pin" + help + At reset ERASE pin is configured in System IO mode. Asserting the ERASE + pin at '1' will completely erase Flash memory. Setting this option will + switch the pin to general IO mode giving control of the pin to the GPIO + module. + +endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/dts_fixup.h b/soc/arm/atmel_sam/samv71/dts_fixup.h new file mode 100644 index 00000000000..2d00452b709 --- /dev/null +++ b/soc/arm/atmel_sam/samv71/dts_fixup.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is a temporary workaround for mapping of the generated information + * to the current driver definitions. This will be removed when the drivers + * are modified to handle the generated information, or the mapping of + * generated data matches the driver definitions. + */ + +/* SoC level DTS fixup file */ + +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY + +#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS + +#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL +#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS +#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0 +#define DT_GPIO_SAM_PORTA_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTA_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTB_LABEL DT_ATMEL_SAM_GPIO_400E1000_LABEL +#define DT_GPIO_SAM_PORTB_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS +#define DT_GPIO_SAM_PORTB_IRQ DT_ATMEL_SAM_GPIO_400E1000_IRQ_0 +#define DT_GPIO_SAM_PORTB_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTB_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTC_LABEL DT_ATMEL_SAM_GPIO_400E1200_LABEL +#define DT_GPIO_SAM_PORTC_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS +#define DT_GPIO_SAM_PORTC_IRQ DT_ATMEL_SAM_GPIO_400E1200_IRQ_0 +#define DT_GPIO_SAM_PORTC_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTC_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTD_LABEL DT_ATMEL_SAM_GPIO_400E1400_LABEL +#define DT_GPIO_SAM_PORTD_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1400_BASE_ADDRESS +#define DT_GPIO_SAM_PORTD_IRQ DT_ATMEL_SAM_GPIO_400E1400_IRQ_0 +#define DT_GPIO_SAM_PORTD_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1400_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTD_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1400_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTE_LABEL DT_ATMEL_SAM_GPIO_400E1600_LABEL +#define DT_GPIO_SAM_PORTE_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1600_BASE_ADDRESS +#define DT_GPIO_SAM_PORTE_IRQ DT_ATMEL_SAM_GPIO_400E1600_IRQ_0 +#define DT_GPIO_SAM_PORTE_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1600_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTE_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1600_PERIPHERAL_ID + +#define DT_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_40018000_BASE_ADDRESS +#define DT_I2C_0_NAME DT_ATMEL_SAM_I2C_TWIHS_40018000_LABEL +#define DT_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWIHS_40018000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWIHS_40018000_IRQ_0 +#define DT_I2C_0_IRQ_PRI DT_ATMEL_SAM_I2C_TWIHS_40018000_IRQ_0_PRIORITY +#define DT_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40018000_PERIPHERAL_ID + +#define DT_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_4001C000_BASE_ADDRESS +#define DT_I2C_1_NAME DT_ATMEL_SAM_I2C_TWIHS_4001C000_LABEL +#define DT_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWIHS_4001C000_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWIHS_4001C000_IRQ_0 +#define DT_I2C_1_IRQ_PRI DT_ATMEL_SAM_I2C_TWIHS_4001C000_IRQ_0_PRIORITY +#define DT_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_4001C000_PERIPHERAL_ID + +#define DT_I2C_2_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_40060000_BASE_ADDRESS +#define DT_I2C_2_NAME DT_ATMEL_SAM_I2C_TWIHS_40060000_LABEL +#define DT_I2C_2_BITRATE DT_ATMEL_SAM_I2C_TWIHS_40060000_CLOCK_FREQUENCY +#define DT_I2C_2_IRQ DT_ATMEL_SAM_I2C_TWIHS_40060000_IRQ_0 +#define DT_I2C_2_IRQ_PRI DT_ATMEL_SAM_I2C_TWIHS_40060000_IRQ_0_PRIORITY +#define DT_I2C_2_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40060000_PERIPHERAL_ID + +#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS +#define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL +#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0 +#define DT_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY +#define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID + +#define DT_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS +#define DT_SPI_1_NAME DT_ATMEL_SAM_SPI_40058000_LABEL +#define DT_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0 +#define DT_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY +#define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID + +#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL +#define DT_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED +#define DT_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 +#define DT_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_1_NAME DT_ATMEL_SAM_UART_400E0A00_LABEL +#define DT_UART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_UART_400E0A00_CURRENT_SPEED +#define DT_UART_SAM_PORT_1_IRQ DT_ATMEL_SAM_UART_400E0A00_IRQ_0 +#define DT_UART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_UART_400E0A00_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_2_NAME DT_ATMEL_SAM_UART_400E1A00_LABEL +#define DT_UART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_UART_400E1A00_CURRENT_SPEED +#define DT_UART_SAM_PORT_2_IRQ DT_ATMEL_SAM_UART_400E1A00_IRQ_0 +#define DT_UART_SAM_PORT_2_IRQ_PRIO DT_ATMEL_SAM_UART_400E1A00_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_3_NAME DT_ATMEL_SAM_UART_400E1C00_LABEL +#define DT_UART_SAM_PORT_3_BAUD_RATE DT_ATMEL_SAM_UART_400E1C00_CURRENT_SPEED +#define DT_UART_SAM_PORT_3_IRQ DT_ATMEL_SAM_UART_400E1C00_IRQ_0 +#define DT_UART_SAM_PORT_3_IRQ_PRIO DT_ATMEL_SAM_UART_400E1C00_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_4_NAME DT_ATMEL_SAM_UART_400E1E00_LABEL +#define DT_UART_SAM_PORT_4_BAUD_RATE DT_ATMEL_SAM_UART_400E1E00_CURRENT_SPEED +#define DT_UART_SAM_PORT_4_IRQ DT_ATMEL_SAM_UART_400E1E00_IRQ_0 +#define DT_UART_SAM_PORT_4_IRQ_PRIO DT_ATMEL_SAM_UART_400E1E00_IRQ_0_PRIORITY + +#define DT_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40024000_LABEL +#define DT_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40024000_CURRENT_SPEED +#define DT_USART_SAM_PORT_0_IRQ DT_ATMEL_SAM_USART_40024000_IRQ_0 +#define DT_USART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_USART_40024000_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_0_PERIPHERAL_ID DT_ATMEL_SAM_USART_40024000_PERIPHERAL_ID +#define DT_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_40028000_LABEL +#define DT_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_40028000_CURRENT_SPEED +#define DT_USART_SAM_PORT_1_IRQ DT_ATMEL_SAM_USART_40028000_IRQ_0 +#define DT_USART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_USART_40028000_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_1_PERIPHERAL_ID DT_ATMEL_SAM_USART_40028000_PERIPHERAL_ID +#define DT_USART_SAM_PORT_2_NAME DT_ATMEL_SAM_USART_4002C000_LABEL +#define DT_USART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_USART_4002C000_CURRENT_SPEED +#define DT_USART_SAM_PORT_2_IRQ DT_ATMEL_SAM_USART_4002C000_IRQ_0 +#define DT_USART_SAM_PORT_2_IRQ_PRIO DT_ATMEL_SAM_USART_4002C000_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_2_PERIPHERAL_ID DT_ATMEL_SAM_USART_4002C000_PERIPHERAL_ID + +#define DT_ADC_0_BASE_ADDRESS DT_ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS +#define DT_ADC_0_IRQ DT_ATMEL_SAM_AFEC_4003C000_IRQ_0 +#define DT_ADC_0_IRQ_PRI DT_ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY +#define DT_ADC_0_NAME DT_ATMEL_SAM_AFEC_4003C000_LABEL +#define DT_ADC_0_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_4003C000_PERIPHERAL_ID + +#define DT_ADC_1_BASE_ADDRESS DT_ATMEL_SAM_AFEC_40064000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ATMEL_SAM_AFEC_40064000_IRQ_0 +#define DT_ADC_1_IRQ_PRI DT_ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY +#define DT_ADC_1_NAME DT_ATMEL_SAM_AFEC_40064000_LABEL +#define DT_ADC_1_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_40064000_PERIPHERAL_ID + +#define DT_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0 +#define DT_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0_PRIORITY +#define DT_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1850_LABEL +#define DT_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1850_BASE_ADDRESS + +#define DT_USBHS_IRQ DT_ATMEL_SAM_USBHS_40038000_IRQ_0 +#define DT_USBHS_IRQ_PRI DT_ATMEL_SAM_USBHS_40038000_IRQ_0_PRIORITY +#define DT_USBHS_MAXIMUM_SPEED DT_ATMEL_SAM_USBHS_40038000_MAXIMUM_SPEED +#define DT_USBHS_NUM_BIDIR_EP DT_ATMEL_SAM_USBHS_40038000_NUM_BIDIR_ENDPOINTS +#define DT_USBHS_PERIPHERAL_ID DT_ATMEL_SAM_USBHS_40038000_PERIPHERAL_ID +#define DT_USBHS_RAM_BASE_ADDRESS DT_ATMEL_SAM_USBHS_40038000_RAM_0 + +#define DT_ENTROPY_SAM_TRNG_BASE_ADDRESS DT_ATMEL_SAM_TRNG_40070000_BASE_ADDRESS +#define DT_ENTROPY_SAM_TRNG_IRQ DT_ATMEL_SAM_TRNG_40070000_IRQ_0 +#define DT_ENTROPY_SAM_TRNG_IRQ_PRI DT_ATMEL_SAM_TRNG_40070000_IRQ_0_PRIORITY +#define DT_ENTROPY_SAM_TRNG_PERIPHERAL_ID DT_ATMEL_SAM_TRNG_40070000_PERIPHERAL_ID +#define DT_ENTROPY_SAM_TRNG_NAME DT_ATMEL_SAM_TRNG_40070000_LABEL +#define CONFIG_ENTROPY_NAME DT_ATMEL_SAM_TRNG_40070000_LABEL + +#define DT_FLASH_DEV_BASE_ADDRESS DT_ATMEL_SAM_FLASH_CONTROLLER_400E0C00_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_ATMEL_SAM_FLASH_CONTROLLER_400E0C00_LABEL + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/atmel_sam/samv71/linker.ld b/soc/arm/atmel_sam/samv71/linker.ld new file mode 100644 index 00000000000..d6c9c438a3f --- /dev/null +++ b/soc/arm/atmel_sam/samv71/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c new file mode 100644 index 00000000000..b9ebc55f8b9 --- /dev/null +++ b/soc/arm/atmel_sam/samv71/soc.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM V71 MCU initialization code + * + * This file provides routines to initialize and support board-level hardware + * for the Atmel SAM V71 MCU. + */ + +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/* Power Manager Controller */ + +/* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 24, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (24 + 1) / 1 = 300 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK)=300 MHz. + */ +#define PMC_CKGR_PLLAR_MULA \ + (CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA)) +#define PMC_CKGR_PLLAR_DIVA \ + (CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA)) + +#if CONFIG_SOC_ATMEL_SAMV71_MDIV == 1 +#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_EQ_PCK +#elif CONFIG_SOC_ATMEL_SAMV71_MDIV == 2 +#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_PCK_DIV2 +#elif CONFIG_SOC_ATMEL_SAMV71_MDIV == 3 +#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_PCK_DIV3 +#elif CONFIG_SOC_ATMEL_SAMV71_MDIV == 4 +#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_PCK_DIV4 +#else +#error "Invalid CONFIG_SOC_ATMEL_SAMV71_MDIV define value" +#endif + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + u32_t reg_val; + +#ifdef CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK + /* Switch slow clock to the external 32 kHz crystal oscillator */ + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; + + /* Wait for oscillator to be stabilized */ + while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { + ; + } +#endif /* CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK */ + +#ifdef CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK + /* + * Setup main external crystal oscillator if not already done + * by a previous program i.e. bootloader + */ + + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL_Msk)) { + /* Start the external crystal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + | CKGR_MOR_MOSCXTST(0xFFu) + /* RC OSC must stay on */ + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTEN; + + /* Wait for oscillator to be stabilized */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { + ; + } + + /* Select the external crystal oscillator as main clock */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCSEL + | CKGR_MOR_MOSCXTST(0xFFu) + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTEN; + + /* Wait for external oscillator to be selected */ + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { + ; + } + } + + /* Turn off RC OSC, not used any longer, to save power */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCSEL + | CKGR_MOR_MOSCXTST(0xFFu) + | CKGR_MOR_MOSCXTEN; + + /* Wait for RC OSC to be turned off */ + while (PMC->PMC_SR & PMC_SR_MOSCRCS) { + ; + } + +#ifdef CONFIG_SOC_ATMEL_SAMV71_WAIT_MODE + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG + */ + PMC->PMC_FSMR |= PMC_FSMR_LPM; +#endif +#else + /* Attempt to change main fast RC oscillator frequency */ + + /* + * NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR + * register, should normally be the case here + */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { + ; + } + + /* Set main fast RC oscillator to 12 MHz */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCRCF_12_MHz + | CKGR_MOR_MOSCRCEN; + + /* Wait for oscillator to be stabilized */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { + ; + } +#endif /* CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK */ + + /* + * Setup PLLA + */ + + /* Switch MCK (Master Clock) to the main clock first */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; + + /* Wait for clock selection to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Setup PLLA */ + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE + | PMC_CKGR_PLLAR_MULA + | CKGR_PLLAR_PLLACOUNT(0x3Fu) + | PMC_CKGR_PLLAR_DIVA; + + /* + * NOTE: Both MULA and DIVA must be set to a value greater than 0 or + * otherwise PLL will be disabled. In this case we would get stuck in + * the following loop. + */ + + /* Wait for PLL lock */ + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { + ; + } + + /* + * Final setup of the Master Clock + */ + + /* + * NOTE: PMC_MCKR must not be programmed in a single write operation. + * If CSS, MDIV or PRES are modified we must wait for MCKRDY bit to be + * set again. + */ + + /* Setup prescaler - PLLA Clock / Processor Clock (HCLK) */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk; + PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAMV71_MDIV; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Finally select PLL as Master Clock source */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run at the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_samv71_init(struct device *arg) +{ + u32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + SCB_EnableICache(); + + if (!(SCB->CCR & SCB_CCR_DC_Msk)) { + SCB_EnableDCache(); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDIO value + * rather than maximum supported 150 MHz at standard VDDIO=2.7V + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; + + /* Setup system clocks */ + clock_init(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Check that the CHIP CIDR matches the HAL one */ + if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { + LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", + (u32_t)CHIPID->CHIPID_CIDR, (u32_t)CHIP_CIDR); + } + + return 0; +} + +SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam/samv71/soc.h b/soc/arm/atmel_sam/samv71/soc.h new file mode 100644 index 00000000000..bf7e4242b9a --- /dev/null +++ b/soc/arm/atmel_sam/samv71/soc.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM V71 MCU. + * + * This file provides register access macros for the Atmel SAM V71 MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _ATMEL_SAMV71_SOC_H_ +#define _ATMEL_SAMV71_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined CONFIG_SOC_PART_NUMBER_SAMV71J19 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21 +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J19B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20B +#include +#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21B +#include +#else + #error Library does not support the specified device. +#endif + +#include "soc_pinmap.h" + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" + +/* Add include for DTS generated information */ +#include + +#endif /* _ASMLANGUAGE */ + +/** Peripheral Hardware Request Line Identifier */ +#define DMA_PERID_HSMCI_TX_RX 0 +#define DMA_PERID_SPI0_TX 1 +#define DMA_PERID_SPI0_RX 2 +#define DMA_PERID_SPI1_TX 3 +#define DMA_PERID_SPI1_RX 4 +#define DMA_PERID_QSPI_TX 5 +#define DMA_PERID_QSPI_RX 6 +#define DMA_PERID_USART0_TX 7 +#define DMA_PERID_USART0_RX 8 +#define DMA_PERID_USART1_TX 9 +#define DMA_PERID_USART1_RX 10 +#define DMA_PERID_USART2_TX 11 +#define DMA_PERID_USART2_RX 12 +#define DMA_PERID_PWM0_TX 13 +#define DMA_PERID_TWIHS0_TX 14 +#define DMA_PERID_TWIHS0_RX 15 +#define DMA_PERID_TWIHS1_TX 16 +#define DMA_PERID_TWIHS1_RX 17 +#define DMA_PERID_TWIHS2_TX 18 +#define DMA_PERID_TWIHS2_RX 19 +#define DMA_PERID_UART0_TX 20 +#define DMA_PERID_UART0_RX 21 +#define DMA_PERID_UART1_TX 22 +#define DMA_PERID_UART1_RX 23 +#define DMA_PERID_UART2_TX 24 +#define DMA_PERID_UART2_RX 25 +#define DMA_PERID_UART3_TX 26 +#define DMA_PERID_UART3_RX 27 +#define DMA_PERID_UART4_TX 28 +#define DMA_PERID_UART4_RX 29 +#define DMA_PERID_DACC0_TX 30 +#define DMA_PERID_DACC1_TX 31 +#define DMA_PERID_SSC_TX 32 +#define DMA_PERID_SSC_RX 33 +#define DMA_PERID_PIOA_RX 34 +#define DMA_PERID_AFEC0_RX 35 +#define DMA_PERID_AFEC1_RX 36 +#define DMA_PERID_AES_TX 37 +#define DMA_PERID_AES_RX 38 +#define DMA_PERID_PWM1_TX 39 +#define DMA_PERID_TC0_RX 40 +#define DMA_PERID_TC3_RX 41 +#define DMA_PERID_TC6_RX 42 +#define DMA_PERID_TC9_RX 43 +#define DMA_PERID_I2SC0_TX_L 44 +#define DMA_PERID_I2SC0_RX_L 45 +#define DMA_PERID_I2SC1_TX_L 46 +#define DMA_PERID_I2SC1_RX_L 47 +#define DMA_PERID_I2SC0_TX_R 48 +#define DMA_PERID_I2SC0_RX_R 49 +#define DMA_PERID_I2SC1_TX_R 50 +#define DMA_PERID_I2SC1_RX_R 51 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ DT_ARM_CORTEX_M7_0_CLOCK_FREQUENCY +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ + (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAMV71_MDIV) + +#endif /* _ATMEL_SAMV71_SOC_H_ */ diff --git a/soc/arm/atmel_sam/samv71/soc_config.c b/soc/arm/atmel_sam/samv71/soc_config.c new file mode 100644 index 00000000000..b308540aa0b --- /dev/null +++ b/soc/arm/atmel_sam/samv71/soc_config.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief System module to support early Atmel SAM V71 MCU configuration + */ + +#include +#include +#include +#include + +/** + * @brief Perform SoC configuration at boot. + * + * This should be run early during the boot process but after basic hardware + * initialization is done. + * + * @return 0 + */ +static int atmel_samv71_config(struct device *dev) +{ +#ifdef CONFIG_SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN + /* Disable ERASE function on PB12 pin, this is controlled by Bus + * Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; +#endif + + /* In Cortex-M based SoCs JTAG interface can be used to perform + * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug + * interface therefore there is no harm done by disabling the JTAG TDI + * pin by default. + */ + /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + +#ifdef CONFIG_LOG_BACKEND_SWO + /* Disable PCK3 clock used by ETM module */ + PMC->PMC_SCDR = PMC_SCDR_PCK3; + while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { + ; + } + /* Select PLLA clock as PCK3 clock */ + PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; + /* Enable PCK3 clock */ + PMC->PMC_SCER = PMC_SCER_PCK3; + /* Wait for PCK3 setup to complete */ + while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { + ; + } +#endif + + return 0; +} + +SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1); diff --git a/soc/arm/atmel_sam/samv71/soc_pinmap.h b/soc/arm/atmel_sam/samv71/soc_pinmap.h new file mode 100644 index 00000000000..a1d81e31ab1 --- /dev/null +++ b/soc/arm/atmel_sam/samv71/soc_pinmap.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * Copyright (c) 2016-2017 Piotr Mienkowski + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM V71 MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _ATMEL_SAM_SOC_PINMAP_H_ +#define _ATMEL_SAM_SOC_PINMAP_H_ + +#include + +/* Analog to Digital Converter (AFEC) */ + +#define PIN_AFE0_ADTRG {PIO_PA8B_AFEC0_ADTRG, PIOA, ID_PIOA, SOC_GPIO_FUNC_B} +#define PIN_AFE1_ADTRG {PIO_PD9C_AFEC1_ADTRG, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} + +/* Ethernet MAC (GMAC) */ + +#define PINS_GMAC_MASK (PIO_PD0A_GMAC_GTXCK | PIO_PD1A_GMAC_GTXEN \ + | PIO_PD2A_GMAC_GTX0 | PIO_PD3A_GMAC_GTX1 | PIO_PD4A_GMAC_GRXDV \ + | PIO_PD5A_GMAC_GRX0 | PIO_PD6A_GMAC_GRX1 | PIO_PD7A_GMAC_GRXER \ + | PIO_PD8A_GMAC_GMDC | PIO_PD9A_GMAC_GMDIO) +#define PIN_GMAC_SET1 {PINS_GMAC_MASK, PIOD, ID_PIOD, SOC_GPIO_FUNC_A} + +#define PINS_GMAC0 {PIN_GMAC_SET1} + +/* Universal Asynchronous Receiver Transmitter (UART) */ + +#define PIN_UART0_RXD {PIO_PA9A_UART0_URXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#define PIN_UART0_TXD {PIO_PA10A_UART0_UTXD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} + +#define PINS_UART0 {PIN_UART0_RXD, PIN_UART0_TXD} + +#define PIN_UART1_RXD {PIO_PA5C_UART1_URXD1, PIOA, ID_PIOA, SOC_GPIO_FUNC_C} +#ifdef CONFIG_UART_SAM_PORT_1_PIN_TX_PA4 +#define PIN_UART1_TXD {PIO_PA4C_UART1_UTXD1, PIOA, ID_PIOA, SOC_GPIO_FUNC_C} +#elif CONFIG_UART_SAM_PORT_1_PIN_TX_PA6 +#define PIN_UART1_TXD {PIO_PA6C_UART1_UTXD1, PIOA, ID_PIOA, SOC_GPIO_FUNC_C} +#elif CONFIG_UART_SAM_PORT_1_PIN_TX_PD26 +#define PIN_UART1_TXD {PIO_PD26D_UART1_UTXD1, PIOD, ID_PIOD, SOC_GPIO_FUNC_D} +#endif + +#define PINS_UART1 {PIN_UART1_RXD, PIN_UART1_TXD} + +#define PIN_UART2_RXD {PIO_PD25C_UART2_URXD2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#define PIN_UART2_TXD {PIO_PD26C_UART2_UTXD2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} + +#define PINS_UART2 {PIN_UART2_RXD, PIN_UART2_TXD} + +#define PIN_UART3_RXD {PIO_PD28A_UART3_URXD3, PIOD, ID_PIOD, SOC_GPIO_FUNC_A} +#ifdef CONFIG_UART_SAM_PORT_3_PIN_TX_PD30 +#define PIN_UART3_TXD {PIO_PD30A_UART3_UTXD3, PIOD, ID_PIOD, SOC_GPIO_FUNC_A} +#elif CONFIG_UART_SAM_PORT_3_PIN_TX_PD31 +#define PIN_UART3_TXD {PIO_PD31B_UART3_UTXD3, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#endif + +#define PINS_UART3 {PIN_UART3_RXD, PIN_UART3_TXD} + +#define PIN_UART4_RXD {PIO_PD18C_UART4_URXD4, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#ifdef CONFIG_UART_SAM_PORT_4_PIN_TX_PD3 +#define PIN_UART4_TXD {PIO_PD3C_UART4_UTXD4, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#elif CONFIG_UART_SAM_PORT_4_PIN_TX_PD19 +#define PIN_UART4_TXD {PIO_PD19C_UART4_UTXD4, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#endif + +#define PINS_UART4 {PIN_UART4_RXD, PIN_UART4_TXD} + +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ + +#define PIN_USART0_RXD {PIO_PB0C_USART0_RXD0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C} +#define PIN_USART0_TXD {PIO_PB1C_USART0_TXD0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C} +#define PIN_USART0_CTS {PIO_PB2C_USART0_CTS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C} +#define PIN_USART0_RTS {PIO_PB3C_USART0_RTS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C} +#define PIN_USART0_SCK {PIO_PB13C_USART0_SCK0, PIOB, ID_PIOB, SOC_GPIO_FUNC_C} + +#define PINS_USART0 {PIN_USART0_RXD, PIN_USART0_TXD, PIN_USART0_CTS, \ + PIN_USART0_RTS, PIN_USART0_SCK} + +#define PIN_USART1_RXD {PIO_PA21A_USART1_RXD1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#define PIN_USART1_TXD {PIO_PB4D_USART1_TXD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_D} +#define PIN_USART1_CTS {PIO_PA25A_USART1_CTS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#define PIN_USART1_RTS {PIO_PA24A_USART1_RTS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#define PIN_USART1_SCK {PIO_PA23A_USART1_SCK1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} + +#define PINS_USART1 {PIN_USART1_RXD, PIN_USART1_TXD, PIN_USART1_CTS, \ + PIN_USART1_RTS, PIN_USART1_SCK} + +#define PIN_USART2_RXD {PIO_PD15B_USART2_RXD2, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#define PIN_USART2_TXD {PIO_PD16B_USART2_TXD2, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#define PIN_USART2_CTS {PIO_PD19B_USART2_CTS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#define PIN_USART2_RTS {PIO_PD18B_USART2_RTS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#define PIN_USART2_SCK {PIO_PD17B_USART2_SCK2, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} + +#define PINS_USART2 {PIN_USART2_RXD, PIN_USART2_TXD, PIN_USART2_CTS, \ + PIN_USART2_RTS, PIN_USART2_SCK} + +/* Synchronous Serial Controller (SSC) */ + +#define PIN_SSC0_RD {PIO_PA10C_SSC_RD, PIOA, ID_PIOA, SOC_GPIO_FUNC_C} +#define PIN_SSC0_RF {PIO_PD24B_SSC_RF, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#define PIN_SSC0_RK {PIO_PA22A_SSC_RK, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#ifdef CONFIG_I2S_SAM_SSC_0_PIN_TD_PB5 +#define PIN_SSC0_TD {PIO_PB5D_SSC_TD, PIOB, ID_PIOB, SOC_GPIO_FUNC_D} +#elif CONFIG_I2S_SAM_SSC_0_PIN_TD_PD10 +#define PIN_SSC0_TD {PIO_PD10C_SSC_TD, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#elif CONFIG_I2S_SAM_SSC_0_PIN_TD_PD26 +#define PIN_SSC0_TD {PIO_PD26B_SSC_TD, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#endif +#define PIN_SSC0_TF {PIO_PB0D_SSC_TF, PIOB, ID_PIOB, SOC_GPIO_FUNC_D} +#define PIN_SSC0_TK {PIO_PB1D_SSC_TK, PIOB, ID_PIOB, SOC_GPIO_FUNC_D} + +#define PINS_SSC0 {PIN_SSC0_RD, PIN_SSC0_RF, PIN_SSC0_RK, PIN_SSC0_TD, \ + PIN_SSC0_TF, PIN_SSC0_TK} + +/* Two-wire Interface (TWIHS) */ + +#define PIN_TWIHS0_TWCK {PIO_PA4A_TWIHS0_TWCK0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#define PIN_TWIHS0_TWD {PIO_PA3A_TWIHS0_TWD0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} + +#define PINS_TWIHS0 {PIN_TWIHS0_TWCK, PIN_TWIHS0_TWD} + +#define PIN_TWIHS1_TWCK {PIO_PB5A_TWIHS1_TWCK1, PIOB, ID_PIOB, SOC_GPIO_FUNC_A} +#define PIN_TWIHS1_TWD {PIO_PB4A_TWIHS1_TWD1, PIOB, ID_PIOB, SOC_GPIO_FUNC_A} + +#define PINS_TWIHS1 {PIN_TWIHS1_TWCK, PIN_TWIHS1_TWD} + +#define PIN_TWIHS2_TWCK {PIO_PD28C_TWIHS2_TWCK2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#define PIN_TWIHS2_TWD {PIO_PD27C_TWIHS2_TWD2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} + +#define PINS_TWIHS2 {PIN_TWIHS2_TWCK, PIN_TWIHS2_TWD} + +#endif /* _ATMEL_SAM_SOC_PINMAP_H_ */