From 9e49bbf179e8f6e676d08cc9bb35e16f33c3e378 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Mon, 10 Feb 2025 14:54:18 +0100 Subject: [PATCH] soc: espressif: esp32s3: Add files to support AMP Update to support APP_CPU flash access. - fix the map_rom_segment so it can be used in other context - add IROM and DROM region size in Kconfig - update the memory.h by using dts records - fix the appcpu ld file to support flash Signed-off-by: Marek Matej --- soc/espressif/common/Kconfig.amp | 12 + soc/espressif/common/include/hw_init.h | 11 + soc/espressif/common/loader.c | 137 +++--- soc/espressif/esp32s3/CMakeLists.txt | 2 +- soc/espressif/esp32s3/default.ld | 32 +- soc/espressif/esp32s3/default_appcpu.ld | 603 ++++++++++++++++++------ soc/espressif/esp32s3/esp32s3-mp.c | 60 ++- soc/espressif/esp32s3/memory.h | 24 +- 8 files changed, 634 insertions(+), 247 deletions(-) diff --git a/soc/espressif/common/Kconfig.amp b/soc/espressif/common/Kconfig.amp index 236f48c3ad6..cce7c866928 100644 --- a/soc/espressif/common/Kconfig.amp +++ b/soc/espressif/common/Kconfig.amp @@ -23,4 +23,16 @@ config ESP_APPCPU_DRAM_SIZE help Defines APPCPU DRAM area size in bytes. +config ESP_APPCPU_IROM_SIZE + hex "ESP32* APPCPU IROM size" + default 0x100000 + help + Defines APPCPU IROM area size in bytes. + +config ESP_APPCPU_DROM_SIZE + hex "ESP32* APPCPU DRAM size" + default 0x100000 + help + Defines APPCPU DROM area size in bytes. + endmenu # AMP config diff --git a/soc/espressif/common/include/hw_init.h b/soc/espressif/common/include/hw_init.h index 1c318fdb826..3c7cf807b6d 100644 --- a/soc/espressif/common/include/hw_init.h +++ b/soc/espressif/common/include/hw_init.h @@ -7,6 +7,17 @@ #ifndef _SOC_ESPRESSIF_COMMON_HW_INIT_H_ #define _SOC_ESPRESSIF_COMMON_HW_INIT_H_ +struct rom_segments { + unsigned int irom_map_addr; /* Mapped address (VMA) for IROM region */ + unsigned int irom_flash_offset; /* Flash offset (LMA) for IROM region */ + unsigned int irom_size; /* Size of IROM region */ + unsigned int drom_map_addr; /* Mapped address (VMA) for DROM region */ + unsigned int drom_flash_offset; /* Flash offset (LMA) for DROM region */ + unsigned int drom_size; /* Size of DROM region */ +}; + +void map_rom_segments(int core, struct rom_segments *map); + int hardware_init(void); #endif /* _SOC_ESPRESSIF_COMMON_HW_INIT_H_ */ diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c index ea9089da4f9..89f6e5d98e0 100644 --- a/soc/espressif/common/loader.c +++ b/soc/espressif/common/loader.c @@ -48,14 +48,18 @@ #include "soc_init.h" #include "soc_random.h" +#if defined(CONFIG_SOC_ESP32S3_APPCPU) || defined(CONFIG_SOC_ESP32_APPCPU) +#error "APPCPU does not need this file!" +#endif + #define TAG "boot" #define CHECKSUM_ALIGN 16 -#define IS_PADD(addr) (addr == 0) -#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) -#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) -#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) -#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) +#define IS_PADD(addr) (addr == 0) +#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) +#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) +#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) +#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) #ifdef SOC_RTC_MEM_SUPPORTED #define IS_RTC(addr) (addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH) #else @@ -68,28 +72,32 @@ #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) +#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU) +#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_partition) +#else +#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_appcpu_partition) +#endif + void __start(void); static HDR_ATTR void (*_entry_point)(void) = &__start; esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr; extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; -extern uint32_t _libc_heap_size; #ifndef CONFIG_MCUBOOT -static uint32_t _app_irom_start = - (FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_irom_start); -static uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - -static uint32_t _app_drom_start = - (FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_drom_start); -static uint32_t _app_drom_size = (uint32_t)&_image_drom_size; +extern uint32_t _libc_heap_size; static uint32_t libc_heap_size = (uint32_t)&_libc_heap_size; -#endif -static uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr); -static uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr); +static struct rom_segments map = { + .irom_map_addr = (uint32_t)&_image_irom_vaddr, + .irom_flash_offset = PART_OFFSET + (uint32_t)&_image_irom_start, + .irom_size = (uint32_t)&_image_irom_size, + .drom_map_addr = ((uint32_t)&_image_drom_vaddr), + .drom_flash_offset = PART_OFFSET + (uint32_t)&_image_drom_start, + .drom_size = (uint32_t)&_image_drom_size, +}; #ifndef CONFIG_BOOTLOADER_MCUBOOT static int spi_flash_read(uint32_t address, void *buffer, size_t length) @@ -98,15 +106,15 @@ static int spi_flash_read(uint32_t address, void *buffer, size_t length) } #endif /* CONFIG_BOOTLOADER_MCUBOOT */ -void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t app_drom_size, - uint32_t app_irom_start, uint32_t app_irom_vaddr, uint32_t app_irom_size) +void map_rom_segments(int core, struct rom_segments *map) { - uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; - uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_align = map->irom_map_addr & MMU_FLASH_MASK; + uint32_t app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK; - uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; - uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_align = map->drom_map_addr & MMU_FLASH_MASK; + uint32_t app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK; + /* Traverse segments to fix flash offset changes due to post-build processing */ #ifndef CONFIG_BOOTLOADER_MCUBOOT esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; size_t offset = FIXED_PARTITION_OFFSET(boot_partition); @@ -141,13 +149,13 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t /* Fix drom and irom produced be the linker, as it could * be invalidated by the elf2image and flash load offset */ - if (segment_hdr.load_addr == _app_drom_vaddr) { - app_drom_start = offset + sizeof(esp_image_segment_header_t); - app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + if (segment_hdr.load_addr == map->drom_map_addr) { + map->drom_flash_offset = offset + sizeof(esp_image_segment_header_t); + app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK; } - if (segment_hdr.load_addr == _app_irom_vaddr) { - app_irom_start = offset + sizeof(esp_image_segment_header_t); - app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + if (segment_hdr.load_addr == map->irom_map_addr) { + map->irom_flash_offset = offset + sizeof(esp_image_segment_header_t); + app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK; } if (IS_SRAM(segment_hdr.load_addr) || IS_RTC(segment_hdr.load_addr)) { ram_segments++; @@ -169,8 +177,8 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t #endif /* !CONFIG_BOOTLOADER_MCUBOOT */ #if CONFIG_SOC_SERIES_ESP32 - Cache_Read_Disable(0); - Cache_Flush(0); + Cache_Read_Disable(core); + Cache_Flush(core); #else cache_hal_disable(CACHE_TYPE_ALL); #endif /* CONFIG_SOC_SERIES_ESP32 */ @@ -178,56 +186,56 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t /* Clear the MMU entries that are already set up, * so the new app only has the mappings it creates. */ - mmu_hal_unmap_all(); + if (core == 0) { + mmu_hal_unmap_all(); + } #if CONFIG_SOC_SERIES_ESP32 int rc = 0; uint32_t drom_page_count = - (app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + (map->drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; - rc |= cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned, app_drom_start_aligned, 64, - drom_page_count); - rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned, app_drom_start_aligned, 64, + rc |= cache_flash_mmu_set(core, 0, app_drom_vaddr_align, app_drom_start_align, 64, drom_page_count); uint32_t irom_page_count = - (app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + (map->irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; - rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned, app_irom_start_aligned, 64, - irom_page_count); - rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned, app_irom_start_aligned, 64, + rc |= cache_flash_mmu_set(core, 0, app_irom_vaddr_align, app_irom_start_align, 64, irom_page_count); if (rc != 0) { - ESP_EARLY_LOGE(TAG, "Failed to setup XIP, aborting"); + ESP_EARLY_LOGE(TAG, "Failed to setup flash cache (e=0x%X). Aborting!", rc); abort(); } #else uint32_t actual_mapped_len = 0; - mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned, - app_drom_size, &actual_mapped_len); + mmu_hal_map_region(core, MMU_TARGET_FLASH0, app_drom_vaddr_align, app_drom_start_align, + map->drom_size, &actual_mapped_len); - mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned, - app_irom_size, &actual_mapped_len); + mmu_hal_map_region(core, MMU_TARGET_FLASH0, app_irom_vaddr_align, app_irom_start_align, + map->irom_size, &actual_mapped_len); #endif /* CONFIG_SOC_SERIES_ESP32 */ /* ----------------------Enable corresponding buses---------------- */ - cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size); + cache_bus_mask_t bus_mask; + + bus_mask = cache_ll_l1_get_bus(core, app_drom_vaddr_align, map->drom_size); + cache_ll_l1_enable_bus(core, bus_mask); + bus_mask = cache_ll_l1_get_bus(core, app_irom_vaddr_align, map->irom_size); + cache_ll_l1_enable_bus(core, bus_mask); - cache_ll_l1_enable_bus(0, bus_mask); - bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); - cache_ll_l1_enable_bus(0, bus_mask); #if CONFIG_MP_MAX_NUM_CPUS > 1 - bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_align, map->drom_size); cache_ll_l1_enable_bus(1, bus_mask); - bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_align, map->irom_size); cache_ll_l1_enable_bus(1, bus_mask); #endif /* ----------------------Enable Cache---------------- */ #if CONFIG_SOC_SERIES_ESP32 /* Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) */ - Cache_Read_Enable(0); + Cache_Read_Enable(core); #else cache_hal_enable(CACHE_TYPE_ALL); #endif /* CONFIG_SOC_SERIES_ESP32 */ @@ -235,21 +243,14 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t #if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32S2) /* Configure the Cache MMU size for instruction and rodata in flash. */ uint32_t cache_mmu_irom_size = - ((app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * + ((map->irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * sizeof(uint32_t); /* Split the cache usage by the segment sizes */ Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); #endif - /* Show map segments continue using same log format as during MCUboot phase */ - ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "DROM", - app_drom_start_aligned, app_drom_vaddr_aligned, app_drom_size, - app_drom_size); - ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "IROM", - app_irom_start_aligned, app_irom_vaddr_aligned, app_irom_size, - app_irom_size); - esp_rom_uart_tx_wait_idle(0); } +#endif /* !CONFIG_MCUBOOT */ void __start(void) { @@ -272,11 +273,17 @@ void __start(void) } #endif -#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU) && \ - !defined(CONFIG_MCUBOOT) - map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_irom_start, - _app_irom_vaddr, _app_irom_size); +#if !defined(CONFIG_MCUBOOT) + map_rom_segments(0, &map); + + /* Show map segments continue using same log format as during MCUboot phase */ + ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "IROM", + map.irom_flash_offset, map.irom_map_addr, map.irom_size, map.irom_size); + ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "DROM", + map.drom_flash_offset, map.drom_map_addr, map.drom_size, map.drom_size); + esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); #endif + #ifndef CONFIG_SOC_SERIES_ESP32C2 /* Disable RNG entropy source as it was already used */ soc_random_disable(); @@ -286,7 +293,7 @@ void __start(void) ESP_EARLY_LOGI(TAG, "Disabling glitch detection"); ana_clock_glitch_reset_config(false); #endif -#if !defined(CONFIG_MCUBOOT) +#ifndef CONFIG_MCUBOOT ESP_EARLY_LOGI(TAG, "libc heap size %d kB.", libc_heap_size / 1024); #endif __esp_platform_start(); diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt index 844aee7ebc3..4de4df54cfe 100644 --- a/soc/espressif/esp32s3/CMakeLists.txt +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -62,7 +62,7 @@ if(CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT) -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() + endif() endif() diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld index 2242fbd9297..79f8af91bd5 100644 --- a/soc/espressif/esp32s3/default.ld +++ b/soc/espressif/esp32s3/default.ld @@ -17,9 +17,25 @@ procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_SIZE; procpu_iram_org = SRAM_USER_IRAM_START; procpu_iram_len = procpu_iram_end - procpu_iram_org; +procpu_dram_org2 = ORIGIN(dram0_0_seg); procpu_dram_org = SRAM1_DRAM_START; procpu_dram_len = procpu_dram_end - procpu_dram_org; +/* User available ROM memory segments */ +procpu_irom_end = ICACHE0_START + ICACHE0_SIZE - APPCPU_ROM_SIZE; +procpu_drom_end = DCACHE0_START + DCACHE0_SIZE - APPCPU_ROM_SIZE; + +procpu_irom_org = ICACHE0_START; +procpu_irom_len = ICACHE0_SIZE - APPCPU_ROM_SIZE; + +procpu_drom_org = DCACHE0_START; +procpu_drom_len = DCACHE0_SIZE - APPCPU_ROM_SIZE; + +#if defined(CONFIG_ESP_SPIRAM) +procpu_extram_org = DCACHE0_START; +procpu_extram_len = CONFIG_ESP_SPIRAM_SIZE; +#endif + /* Aliases */ #define FLASH_CODE_REGION irom0_0_seg #define RODATA_REGION drom0_0_seg @@ -61,8 +77,8 @@ MEMORY iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN + irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len + drom0_0_seg(R): org = procpu_drom_org, len = procpu_drom_len /* The `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region. * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in` @@ -70,8 +86,8 @@ MEMORY #if defined(CONFIG_ESP_SPIRAM) /* `ext_[id]ram_seg` and `drom0_0_seg` share the same bus and the address region. * A dummy section is used to avoid overlap. See `.ext_ram.dummy` */ - ext_dram_seg(RW): org = DROM_SEG_ORG, len = (CONFIG_ESP_SPIRAM_SIZE) - ext_iram_seg(RX): org = IROM_SEG_ORG, len = (CONFIG_ESP_SPIRAM_SIZE) + ext_dram_seg(RW): org = procpu_extram_org, len = procpu_extram_len + ext_iram_seg(RX): org = procpu_extram_org, len = procpu_extram_len #endif /* RTC fast memory (executable). Persists over deep sleep. @@ -149,7 +165,7 @@ SECTIONS */ LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data_end) + SIZEOF(.dram0.data_end) - LOADADDR(.dram0.data)) /* RTC_IRAM metadata: * 8. Destination address (VMA) for RTC_IRAM region @@ -559,8 +575,8 @@ SECTIONS /* Spacer section is required to skip .iram0.text area because * iram0_0_seg and dram0_0_seg reflect the same address space on different buses. */ - . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START; - . = ALIGN(4) + 16; + . = ORIGIN(dram0_0_seg) + (MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START); + . = ALIGN(16); } GROUP_LINK_IN(RAMABLE_REGION) .dram0.data : @@ -753,7 +769,7 @@ SECTIONS #include #pragma pop_macro("GROUP_ROM_LINK_IN") - .dram0.end : + .dram0.data_end : { __data_end = ABSOLUTE(.); _data_end = ABSOLUTE(.); diff --git a/soc/espressif/esp32s3/default_appcpu.ld b/soc/espressif/esp32s3/default_appcpu.ld index 2b36ef3d19e..ef11fccb218 100644 --- a/soc/espressif/esp32s3/default_appcpu.ld +++ b/soc/espressif/esp32s3/default_appcpu.ld @@ -24,11 +24,19 @@ appcpu_dram_org = appcpu_dram_end - APPCPU_SRAM_SIZE; appcpu_iram_len = APPCPU_SRAM_SIZE; appcpu_dram_len = APPCPU_SRAM_SIZE; +/* User available ROM memory segments */ +appcpu_irom_org = (ICACHE0_START + ICACHE0_SIZE) - APPCPU_ROM_SIZE; +appcpu_drom_org = (DCACHE0_START + DCACHE0_SIZE) - APPCPU_ROM_SIZE; + +appcpu_irom_len = APPCPU_ROM_SIZE; +appcpu_drom_len = APPCPU_ROM_SIZE; + /* Aliases */ -#define ROMABLE_REGION FLASH -#define RODATA_REGION dram0_1_seg /* drom0_1_seg */ -#define RAMABLE_REGION dram0_1_seg -#define IRAM_REGION iram0_1_seg +#define FLASH_CODE_REGION irom0_1_seg +#define RODATA_REGION drom0_1_seg +#define IRAM_REGION iram0_1_seg +#define RAMABLE_REGION dram0_1_seg +#define ROMABLE_REGION FLASH /* Zephyr macro re-definitions */ #undef GROUP_DATA_LINK_IN @@ -51,13 +59,16 @@ appcpu_dram_len = APPCPU_SRAM_SIZE; MEMORY { - mcuboot_hdr (R): org = 0x0, len = 0x20 - metadata (R): org = 0x20, len = 0x20 - FLASH (R): org = 0x40, len = FLASH_SIZE - 0x40 + mcuboot_hdr (R): org = 0x0, len = 0x20 + metadata (R): org = 0x20, len = 0x60 + FLASH (R): org = 0x80, len = FLASH_SIZE - 0x80 iram0_1_seg(RX): org = appcpu_iram_org, len = appcpu_iram_len dram0_1_seg(RW): org = appcpu_dram_org, len = appcpu_dram_len + irom0_1_seg(RX): org = appcpu_irom_org, len = appcpu_irom_len + drom0_1_seg(R): org = appcpu_drom_org, len = appcpu_drom_len + #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 #endif @@ -106,6 +117,42 @@ SECTIONS LONG(ADDR(.dram0.data)) LONG(LOADADDR(.dram0.data)) LONG(_data_end - _data_start) + + /* RTC_IRAM metadata: + * 8. Destination address (VMA) for RTC_IRAM region + * 9. Flash offset (LMA) for start of RTC_IRAM region + * 10. Size of RTC_IRAM region + */ + LONG(0); + LONG(0); + LONG(0); + + /* RTC_DRAM metadata: + * 11. Destination address (VMA) for RTC_DRAM region + * 12. Flash offset (LMA) for start of RTC_DRAM region + * 13. Size of RTC_DRAM region + */ + LONG(0); + LONG(0); + LONG(0); + + /* IROM metadata: + * 14. Destination address (VMA) for IROM region + * 15. Flash offset (LMA) for start of IROM region + * 16. Size of IROM region + */ + LONG(_image_irom_vaddr); + LONG(_image_irom_start); + LONG(_image_irom_size); + + /* DROM metadata: + * 17. Destination address (VMA) for DROM region + * 18. Flash offset (LMA) for start of DROM region + * 19. Size of DROM region + */ + LONG(_image_drom_vaddr); + LONG(_image_drom_start); + LONG(_image_drom_size); } > metadata #include @@ -159,21 +206,18 @@ SECTIONS .iram0.text : ALIGN(4) { + /* Code marked as running out of IRAM */ _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_packaged.*(.literal .text .literal.* .text.*) *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) @@ -182,50 +226,138 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_minimal.*(.literal .literal.* .text .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:soc_flash_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:console_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:soc_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:hw_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:soc_random.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_mmu_map.*(.literal .literal.* .text .text.*) + *libdrivers__interrupt_controller.a:(.literal .literal.* .text .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) + *liblib__libc__picolibc.a:string.*(.literal .text .literal.* .text.*) *libphy.a:(.phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + /* APPCPU_ENABLED */ + *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libzephyr.a:flash_mmap.*(.literal .text .literal.* .text.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .text .literal.* .text.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*) + + /* [mapping:log] */ + *(.literal.esp_log_write .text.esp_log_write) + *(.literal.esp_log_timestamp .text.esp_log_timestamp) + *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *(.literal.esp_log_impl_lock .text.esp_log_impl_lock) + *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout) + *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_ops.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *(.literal.esp_system_abort .text.esp_system_abort) + + /* [mapping:esp_hw_support] */ + *(.literal.esp_cpu_stall .text.esp_cpu_stall) + *(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *(.literal.esp_cpu_reset .text.esp_cpu_reset) + *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config) + *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*) + *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*) + *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_efuse.*(.literal .literal.* .text .text.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + . = ALIGN(16); } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - .flash.text : ALIGN(16) + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : { - _stext = .; - _text_start = ABSOLUTE(.); + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */ + . = ALIGN(4) + 16; + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - *(.literal .text .literal.* .text.*) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ + .iram0.data : + { . = ALIGN(4); - _flash_cache_start = ABSOLUTE(0); + _iram_data_start = ABSOLUTE(.); + *(.iram.data) + *(.iram.data*) + _iram_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + _iram_bss_start = ABSOLUTE(.); + *(.iram.bss) + *(.iram.bss*) + _iram_bss_end = ABSOLUTE(.); . = ALIGN(4); _iram_end = ABSOLUTE(.); - - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + } GROUP_LINK_IN(IRAM_REGION) /* --- END OF IRAM --- */ @@ -233,15 +365,21 @@ SECTIONS .dram0.dummy (NOLOAD): { - . = ORIGIN(dram0_1_seg) + MAX(_iram_end, appcpu_iram_org) - appcpu_iram_org; + . = ORIGIN(dram0_1_seg) + (MAX(_iram_end, _init_start) - _init_start); . = ALIGN(16); } GROUP_LINK_IN(RAMABLE_REGION) .dram0.data : { . = ALIGN (8); - __data_start = ABSOLUTE(.); _data_start = ABSOLUTE(.); + __data_start = ABSOLUTE(.); + + /* bluetooth library requires this symbol to be defined */ + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); *(.data) *(.data.*) @@ -253,20 +391,126 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) + *(.srodata) + *(.srodata.*) /* rodata for panic handler(libarch__xtensa__core.a) and all * dependent functions should be placed in DRAM to avoid issue * when flash cache is disabled */ *libarch__xtensa__core.a:(.rodata .rodata.*) *libkernel.a:fatal.*(.rodata .rodata.*) *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete.*(.rodata .rodata.*) *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:log_minimal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) + *libzephyr.a:flash_init.*(.rodata .rodata.*) + *libzephyr.a:soc_flash_init.*(.rodata .rodata.*) + *libzephyr.a:console_init.*(.rodata .rodata.*) + *libzephyr.a:soc_init.*(.rodata .rodata.*) + *libzephyr.a:hw_init.*(.rodata .rodata.*) + *libzephyr.a:soc_random.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_mmu_map.*(.rodata .rodata.*) + *libdrivers__interrupt_controller.a:(.rodata .rodata.*) + + /* APPCPU_ENABLE */ + *libzephyr.a:esp32s3-mp.*(.rodata .rodata.*) + *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_mmap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + + /* [mapping:esp_psram] */ + *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*) + *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*) + + /* [mapping:hal] */ + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.*) + + /* [mapping:soc] */ + *libzephyr.a:lldesc.*(.rodata .rodata.*) + + /* [mapping:log] */ + *(.rodata.esp_log_write) + *(.rodata.esp_log_timestamp) + *(.rodata.esp_log_early_timestamp) + *(.rodata.esp_log_impl_lock) + *(.rodata.esp_log_impl_lock_timeout) + *(.rodata.esp_log_impl_unlock) + + /* [mapping:spi_flash] */ + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.*) + *libzephyr.a:flash_qio_mode.*(.rodata .rodata.*) + *libzephyr.a:flash_ops.*(.rodata .rodata.*) + + /* [mapping:esp_mm] */ + *libzephyr.a:esp_cache.*(.rodata .rodata.*) + + /* [mapping:esp_hw_support] */ + *(.rodata.esp_cpu_stall) + *(.rodata.esp_cpu_unstall) + *(.rodata.esp_cpu_reset) + *(.rodata.esp_cpu_wait_for_intr) + *(.rodata.esp_cpu_compare_and_set) + *(.rodata.esp_gpio_reserve_pins) + *(.rodata.esp_gpio_is_pin_reserved) + *(.rodata.rtc_vddsdio_get_config) + *(.rodata.rtc_vddsdio_set_config) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk_init.*(.rodata .rodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*) + *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*) + *(.rodata.sar_periph_ctrl_power_enable) + + /* [mapping:soc_pm] */ + *(.rodata.GPIO_HOLD_MASK) + + /* [mapping:esp_rom] */ + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) + *libzephyr.a:cache_utils.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*) + *libzephyr.a:esp_rom_efuse.*(.rodata .rodata.*) + + /* [mapping:esp_system] */ + *libzephyr.a:esp_err.*(.rodata .rodata.*) + *(.rodata.esp_system_abort) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + /* [mapping:esp_wifi] */ + *(.rodata.wifi_clock_enable_wrapper) + *(.rodata.wifi_clock_disable_wrapper) + + /* [mapping:esp_phy] */ + *(.rodata.esp_phy_enable) + *(.rodata.esp_phy_disable) + *(.rodata.esp_wifi_bt_power_domain_off) +#endif . = ALIGN(4); #include @@ -274,7 +518,7 @@ SECTIONS KEEP(*(.jcr)) *(.dram1 .dram1.*) - . = ALIGN(16); + . = ALIGN(4); } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) @@ -283,108 +527,15 @@ SECTIONS #include #include #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN #include + #pragma pop_macro("GROUP_ROM_LINK_IN") - .dram0.rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - __rodata_region_start = ABSOLUTE(.); - . = ALIGN(4); - #include - - . = ALIGN(4); - *(EXCLUDE_FILE ( - *libarch__xtensa__core.a:* - *libkernel.a:fatal.* - *libkernel.a:init.* - *libzephyr.a:cbprintf_complete* - *libzephyr.a:log_core.* - *libzephyr.a:log_backend_uart.* - *libzephyr.a:log_output.* - *libzephyr.a:loader.* - *libdrivers__serial.a:uart_esp32.*) .rodata) - - *(EXCLUDE_FILE ( - *libarch__xtensa__core.a:* - *libkernel.a:fatal.* - *libkernel.a:init.* - *libzephyr.a:cbprintf_complete* - *libzephyr.a:log_core.* - *libzephyr.a:log_backend_uart.* - *libzephyr.a:log_output.* - *libzephyr.a:loader.* - *libdrivers__serial.a:uart_esp32.*) .rodata.*) - - . = ALIGN(4); - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) - *(.rodata_wlog) - *(.rodata_wlog*) - _thread_local_end = ABSOLUTE(.); - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. - * Executing directly from LMA is not possible. */ - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - .dram0.rodata_end : ALIGN(16) - { - . = ALIGN(16); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - .dram0.end : + .dram0.data_end : { __data_end = ABSOLUTE(.); _data_end = ABSOLUTE(.); @@ -431,6 +582,161 @@ SECTIONS /* --- END OF DRAM --- */ + /* --- START OF IROM --- */ + + /* Symbols used during the application memory mapping */ + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; + _image_irom_vaddr = ADDR(.flash.text); + + /* Align next section to 64k to allow mapping */ + .flash.text_dummy (NOLOAD) : + { + . = ALIGN(CACHE_ALIGN); + } GROUP_LINK_IN(ROMABLE_REGION) + + .flash.text : ALIGN(16) + { + _stext = .; + _text_start = ABSOLUTE(.); + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + *(.literal .text .literal.* .text.*) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + . = ALIGN(4); + _flash_cache_start = ABSOLUTE(0); + + . = ALIGN(4); + + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /* --- END OF IROM --- */ + + /* --- START OF DROM --- */ + + /* This dummy section represents the .flash.text section but in default_rodata_seg. + * Thus, it must have its alignment and (at least) its size. + */ + .cache.rodata_dummy (NOLOAD): + { + _cache_rodata_dummy_start = ABSOLUTE(.); + . += SIZEOF(.flash.text); + . = ALIGN(CACHE_ALIGN); + _cache_rodata_dummy_end = ABSOLUTE(.); + } GROUP_LINK_IN(RODATA_REGION) + + .flash.rodata_dummy (NOLOAD): + { + _flash_rodata_dummy_start = ABSOLUTE(.); + . += SIZEOF(.flash.text); + . = ALIGN(CACHE_ALIGN); + _flash_rodata_dummy_end = ABSOLUTE(.); + } GROUP_LINK_IN(ROMABLE_REGION) + + _image_drom_start = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start; + _image_drom_vaddr = ADDR(.flash.rodata); + + .flash.rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); + #include + + . = ALIGN(4); + + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + *(.rodata_wlog) + *(.rodata_wlog*) + _thread_local_end = ABSOLUTE(.); + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + .flash.rodata_end : ALIGN(16) + { + . = ALIGN(16); + _rodata_reserved_end = ABSOLUTE(.); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + /* --- END OF DROM --- */ + + /* --- XTENSA GLUE AND DEBUG BEGIN --- */ + #ifdef CONFIG_GEN_ISR_TABLES #include #endif @@ -472,5 +778,10 @@ SECTIONS } } + /* --- XTENSA GLUE AND DEBUG END --- */ + ASSERT(((_iram_end - ORIGIN(iram0_1_seg)) <= LENGTH(iram0_1_seg)), "IRAM0 segment data does not fit.") + +ASSERT(((_end - ORIGIN(dram0_1_seg)) <= LENGTH(dram0_1_seg)), + "DRAM segment data does not fit.") diff --git a/soc/espressif/esp32s3/esp32s3-mp.c b/soc/espressif/esp32s3/esp32s3-mp.c index a174db1e23c..80207a823d6 100644 --- a/soc/espressif/esp32s3/esp32s3-mp.c +++ b/soc/espressif/esp32s3/esp32s3-mp.c @@ -12,11 +12,15 @@ #include #include +#include #include #include "esp_rom_uart.h" #include "esp_mcuboot_image.h" #include "esp_memory_utils.h" +#include "hw_init.h" + +#define TAG "amp" /* AMP support */ #ifdef CONFIG_SOC_ENABLE_APPCPU @@ -47,7 +51,7 @@ static int load_segment(uint32_t src_addr, uint32_t src_len, uint32_t dst_addr) const uint32_t *data = (const uint32_t *)sys_mmap(src_addr, src_len); if (!data) { - ets_printf("%s: mmap failed", __func__); + ESP_EARLY_LOGE(TAG, "%s: mmap failed", __func__); return -1; } @@ -64,12 +68,12 @@ static int load_segment(uint32_t src_addr, uint32_t src_len, uint32_t dst_addr) int IRAM_ATTR esp_appcpu_image_load(unsigned int hdr_offset, unsigned int *entry_addr) { - const uint32_t img_off = FIXED_PARTITION_OFFSET(slot0_appcpu_partition); + const uint32_t fa_offset = FIXED_PARTITION_OFFSET(slot0_appcpu_partition); const uint32_t fa_size = FIXED_PARTITION_SIZE(slot0_appcpu_partition); const uint8_t fa_id = FIXED_PARTITION_ID(slot0_appcpu_partition); if (entry_addr == NULL) { - ets_printf("Can't return the entry address. Aborting!\n"); + ESP_EARLY_LOGE(TAG, "Can't return the entry address. Aborting!"); abort(); return -1; } @@ -77,7 +81,7 @@ int IRAM_ATTR esp_appcpu_image_load(unsigned int hdr_offset, unsigned int *entry uint32_t mcuboot_header[8] = {0}; esp_image_load_header_t image_header = {0}; - const uint32_t *data = (const uint32_t *)sys_mmap(img_off, 0x40); + const uint32_t *data = (const uint32_t *)sys_mmap(fa_offset, 0x80); memcpy((void *)&mcuboot_header, data, sizeof(mcuboot_header)); memcpy((void *)&image_header, data + (hdr_offset / sizeof(uint32_t)), @@ -86,49 +90,69 @@ int IRAM_ATTR esp_appcpu_image_load(unsigned int hdr_offset, unsigned int *entry sys_munmap(data); if (image_header.header_magic == ESP_LOAD_HEADER_MAGIC) { - ets_printf("APPCPU image, area id: %d, offset: 0x%x, hdr.off: 0x%x, size: %d kB\n", - fa_id, img_off, hdr_offset, fa_size / 1024); + ESP_EARLY_LOGI(TAG, + "APPCPU image, area id: %d, offset: 0x%x, hdr.off: 0x%x, size: %d kB", + fa_id, fa_offset, hdr_offset, fa_size / 1024); } else if ((image_header.header_magic & 0xff) == 0xE9) { - ets_printf("ESP image format is not supported\n"); + ESP_EARLY_LOGE(TAG, "ESP image format is not supported"); abort(); } else { - ets_printf("Unknown or empty image detected. Aborting!\n"); + ESP_EARLY_LOGE(TAG, "Unknown or empty image detected. Aborting!"); abort(); } if (!esp_ptr_in_iram((void *)image_header.iram_dest_addr) || !esp_ptr_in_iram((void *)(image_header.iram_dest_addr + image_header.iram_size))) { - ets_printf("IRAM region in load header is not valid. Aborting"); + ESP_EARLY_LOGE(TAG, "IRAM region in load header is not valid. Aborting"); abort(); } if (!esp_ptr_in_dram((void *)image_header.dram_dest_addr) || !esp_ptr_in_dram((void *)(image_header.dram_dest_addr + image_header.dram_size))) { - ets_printf("DRAM region in load header is not valid. Aborting"); + ESP_EARLY_LOGE(TAG, "DRAM region in load header is not valid. Aborting"); abort(); } if (!esp_ptr_in_iram((void *)image_header.entry_addr)) { - ets_printf("Application entry point (%xh) is not in IRAM. Aborting", + ESP_EARLY_LOGE(TAG, "Application entry point (%xh) is not in IRAM. Aborting", image_header.entry_addr); abort(); } - ets_printf("IRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load\n", - (img_off + image_header.iram_flash_offset), image_header.iram_dest_addr, + ESP_EARLY_LOGI(TAG, "IRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load", + (fa_offset + image_header.iram_flash_offset), image_header.iram_dest_addr, image_header.iram_size, image_header.iram_size); - load_segment(img_off + image_header.iram_flash_offset, image_header.iram_size, + load_segment(fa_offset + image_header.iram_flash_offset, image_header.iram_size, image_header.iram_dest_addr); - ets_printf("DRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load\n", - (img_off + image_header.dram_flash_offset), image_header.dram_dest_addr, + ESP_EARLY_LOGI(TAG, "DRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load", + (fa_offset + image_header.dram_flash_offset), image_header.dram_dest_addr, image_header.dram_size, image_header.dram_size); - load_segment(img_off + image_header.dram_flash_offset, image_header.dram_size, + load_segment(fa_offset + image_header.dram_flash_offset, image_header.dram_size, image_header.dram_dest_addr); - ets_printf("Application start=%xh\n\n", image_header.entry_addr); + ESP_EARLY_LOGI(TAG, "IROM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) map", + (fa_offset + image_header.irom_flash_offset), image_header.irom_map_addr, + image_header.irom_size, image_header.irom_size); + + ESP_EARLY_LOGI(TAG, "DROM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) map", + (fa_offset + image_header.drom_flash_offset), image_header.drom_map_addr, + image_header.drom_size, image_header.drom_size); + + struct rom_segments rom = { + image_header.drom_map_addr, + image_header.drom_flash_offset + fa_offset, + image_header.drom_size, + image_header.irom_map_addr, + image_header.irom_flash_offset + fa_offset, + image_header.irom_size, + }; + + map_rom_segments(1, &rom); + + ESP_EARLY_LOGI(TAG, "Application start=%xh\n\n", image_header.entry_addr); esp_rom_uart_tx_wait_idle(0); assert(entry_addr != NULL); diff --git a/soc/espressif/esp32s3/memory.h b/soc/espressif/esp32s3/memory.h index e435abe95a7..98885425053 100644 --- a/soc/espressif/esp32s3/memory.h +++ b/soc/espressif/esp32s3/memory.h @@ -78,31 +78,37 @@ #define USER_IRAM_END (USER_DRAM_END + IRAM_DRAM_OFFSET) /* AMP */ -#if defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32S3_APPCPU) +#if (defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32S3_APPCPU)) #define APPCPU_IRAM_SIZE CONFIG_ESP_APPCPU_IRAM_SIZE #define APPCPU_DRAM_SIZE CONFIG_ESP_APPCPU_DRAM_SIZE #define AMP_COMM_SIZE DT_REG_SIZE(DT_NODELABEL(ipmmem0)) + DT_REG_SIZE(DT_NODELABEL(shm0)) + \ DT_REG_SIZE(DT_NODELABEL(ipm0)) + DT_REG_SIZE(DT_NODELABEL(mbox0)) #undef DRAM_RESERVED_START #define DRAM_RESERVED_START 0x3fce5000 +#define APPCPU_IROM_SIZE CONFIG_ESP_APPCPU_IROM_SIZE +#define APPCPU_DROM_SIZE CONFIG_ESP_APPCPU_DROM_SIZE #else #define APPCPU_IRAM_SIZE 0 #define APPCPU_DRAM_SIZE 0 #define AMP_COMM_SIZE 0 +#define APPCPU_IROM_SIZE 0 +#define APPCPU_DROM_SIZE 0 #endif #define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE) +#define APPCPU_ROM_SIZE (APPCPU_IROM_SIZE + APPCPU_DROM_SIZE) -/* Flash */ +/* Cached memory */ +#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0)) +#define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0)) +#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0)) +#define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0)) + +#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE + +/* Flash memory */ #ifdef CONFIG_FLASH_SIZE #define FLASH_SIZE CONFIG_FLASH_SIZE #else #define FLASH_SIZE 0x800000 #endif - -/* Cached memory */ -#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -#define DROM_SEG_ORG 0x3c000000 -#define DROM_SEG_LEN FLASH_SIZE