drivers/spi: SPI driver for SiFive Freedom
A driver for the sifive,spi0 SPI device on SiFive Freedom platforms Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit is contained in:
Nathaniel Graff
Kumar Gala
parent
5dbb147993
commit
9e2ef8db6d
5 changed files with 384 additions and 0 deletions
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@ -7,6 +7,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SIFIVE spi_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_SPI spi_nrfx_spi.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_SPIM spi_nrfx_spim.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_SPIS spi_nrfx_spis.c)
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@ -180,6 +180,8 @@ source "drivers/spi/Kconfig.sam"
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source "drivers/spi/Kconfig.sam0"
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source "drivers/spi/Kconfig.sifive"
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source "drivers/spi/Kconfig.nrfx"
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endif # SPI
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31
drivers/spi/Kconfig.sifive
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31
drivers/spi/Kconfig.sifive
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@ -0,0 +1,31 @@
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# Kconfig - SiFive SPI Driver configuration options
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#
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# Copyright (c) 2018 SiFive Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig SPI_SIFIVE
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bool "SiFive SPI controller driver"
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depends on SPI
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depends on SOC_SERIES_RISCV32_SIFIVE_FREEDOM
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help
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Enable the SPI peripherals on SiFive Freedom processors
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if SPI_SIFIVE
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config SIFIVE_SPI_0_ROM
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bool "SPI 0 is used to access SPI Flash ROM"
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default y
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depends on SPI_SIFIVE
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help
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If enabled, SPI 0 is reserved for accessing the SPI flash ROM and a
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driver interface won't be instantiated for SPI 0.
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Beware disabling this option on HiFive 1! The SPI flash ROM is where the
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program is stored, and if this driver initializes the interface for
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peripheral control the FE310 will crash on boot.
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endif # SPI_SIFIVE
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275
drivers/spi/spi_sifive.c
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275
drivers/spi/spi_sifive.c
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@ -0,0 +1,275 @@
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/*
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* Copyright (c) 2018 SiFive Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_sifive);
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#include "spi_sifive.h"
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#include <stdbool.h>
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/* Helper Functions */
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static inline void sys_set_mask(mem_addr_t addr, u32_t mask, u32_t value)
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{
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u32_t temp = sys_read32(addr);
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temp &= ~(mask);
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temp |= value;
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sys_write32(temp, addr);
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}
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int spi_config(struct device *dev, u32_t frequency, u16_t operation)
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{
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u32_t div;
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u32_t fmt_len;
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if (SPI_OP_MODE_GET(operation) != SPI_OP_MODE_MASTER) {
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return -ENOTSUP;
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}
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if (operation & SPI_MODE_LOOP) {
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return -ENOTSUP;
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}
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/* Set the SPI frequency */
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div = (SPI_CFG(dev)->f_sys / (2 * frequency)) - 1;
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sys_write32((SF_SCKDIV_DIV_MASK & div), SPI_REG(dev, REG_SCKDIV));
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/* Set the polarity */
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if (operation & SPI_MODE_CPOL) {
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/* If CPOL is set, then SCK idles at logical 1 */
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sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL);
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} else {
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/* SCK idles at logical 0 */
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sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL);
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}
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/* Set the phase */
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if (operation & SPI_MODE_CPHA) {
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/*
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* If CPHA is set, then data is sampled
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* on the trailing SCK edge
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*/
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sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA);
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} else {
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/* Data is sampled on the leading SCK edge */
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sys_clear_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA);
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}
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/* Get the frame length */
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fmt_len = SPI_WORD_SIZE_GET(operation);
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if (fmt_len > SF_FMT_LEN_MASK) {
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return -ENOTSUP;
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}
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/* Set the frame length */
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fmt_len = fmt_len << SF_FMT_LEN;
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fmt_len &= SF_FMT_LEN_MASK;
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sys_set_mask(SPI_REG(dev, REG_FMT), SF_FMT_LEN_MASK, fmt_len);
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if ((operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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return -ENOTSUP;
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}
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/* Set single line operation */
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sys_set_mask(SPI_REG(dev, REG_FMT),
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SF_FMT_PROTO_MASK,
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SF_FMT_PROTO_SINGLE);
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/* Set the endianness */
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if (operation & SPI_TRANSFER_LSB) {
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sys_set_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN);
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} else {
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sys_clear_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN);
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}
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return 0;
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}
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void spi_sifive_send(struct device *dev, u16_t frame)
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{
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while (SPI_REG(dev, REG_TXDATA) & SF_TXDATA_FULL)
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;
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sys_write32((u32_t) frame, SPI_REG(dev, REG_TXDATA));
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}
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u16_t spi_sifive_recv(struct device *dev)
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{
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u32_t val;
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while ((val = sys_read32(SPI_REG(dev, REG_RXDATA))) & SF_RXDATA_EMPTY)
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;
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return (u16_t) val;
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}
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void spi_sifive_xfer(struct device *dev, const bool hw_cs_control)
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{
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struct spi_context *ctx = &SPI_DATA(dev)->ctx;
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u32_t send_len = spi_context_longest_current_buf(ctx);
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for (u32_t i = 0; i < send_len; i++) {
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/* Send a frame */
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if (i < ctx->tx_len) {
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spi_sifive_send(dev, (u16_t) (ctx->tx_buf)[i]);
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} else {
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/* Send dummy bytes */
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spi_sifive_send(dev, 0);
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}
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/* Receive a frame */
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if (i < ctx->rx_len) {
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ctx->rx_buf[i] = (u8_t) spi_sifive_recv(dev);
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} else {
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/* Discard returned value */
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spi_sifive_recv(dev);
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}
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}
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/* Deassert the CS line */
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if (!hw_cs_control) {
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spi_context_cs_control(&SPI_DATA(dev)->ctx, false);
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} else {
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sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
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}
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spi_context_complete(ctx, 0);
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}
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/* API Functions */
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int spi_sifive_init(struct device *dev)
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{
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/* Disable SPI Flash mode */
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sys_clear_bit(SPI_REG(dev, REG_FCTRL), SF_FCTRL_EN);
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/* Make sure the context is unlocked */
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spi_context_unlock_unconditionally(&SPI_DATA(dev)->ctx);
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return 0;
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}
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int spi_sifive_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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int rc = 0;
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bool hw_cs_control = false;
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/* Lock the SPI Context */
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spi_context_lock(&SPI_DATA(dev)->ctx, false, NULL);
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/* Configure the SPI bus */
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SPI_DATA(dev)->ctx.config = config;
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/*
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* If the chip select configuration is not present, we'll ask the
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* SPI peripheral itself to control the CS line
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*/
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if (config->cs == NULL) {
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hw_cs_control = true;
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}
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if (!hw_cs_control) {
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/*
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* If the user has requested manual GPIO control, ask the
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* context for control and disable HW control
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*/
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spi_context_cs_configure(&SPI_DATA(dev)->ctx);
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sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
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} else {
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/*
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* Tell the hardware to control the requested CS pin.
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* NOTE:
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* For the SPI peripheral, the pin number is not the
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* GPIO pin, but the index into the list of available
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* CS lines for the SPI peripheral.
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*/
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sys_write32(config->slave, SPI_REG(dev, REG_CSID));
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sys_write32(SF_CSMODE_OFF, SPI_REG(dev, REG_CSMODE));
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}
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rc = spi_config(dev, config->frequency, config->operation);
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if (rc < 0) {
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spi_context_release(&SPI_DATA(dev)->ctx, rc);
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return rc;
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}
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spi_context_buffers_setup(&SPI_DATA(dev)->ctx, tx_bufs, rx_bufs, 1);
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/* Assert the CS line */
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if (!hw_cs_control) {
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spi_context_cs_control(&SPI_DATA(dev)->ctx, true);
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} else {
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sys_write32(SF_CSMODE_HOLD, SPI_REG(dev, REG_CSMODE));
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}
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/* Perform transfer */
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spi_sifive_xfer(dev, hw_cs_control);
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rc = spi_context_wait_for_completion(&SPI_DATA(dev)->ctx);
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spi_context_release(&SPI_DATA(dev)->ctx, rc);
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return rc;
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}
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int spi_sifive_release(struct device *dev, const struct spi_config *config)
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{
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spi_context_unlock_unconditionally(&SPI_DATA(dev)->ctx);
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return 0;
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}
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/* Device Instantiation */
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static struct spi_driver_api spi_sifive_api = {
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.transceive = spi_sifive_transceive,
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.release = spi_sifive_release,
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};
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#define SPI_INIT(n) \
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static struct spi_sifive_data spi_sifive_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_sifive_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_sifive_data_##n, ctx), \
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}; \
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static struct spi_sifive_cfg spi_sifive_cfg_##n = { \
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.base = DT_SIFIVE_SPI0_##n##_CONTROL_BASE_ADDRESS, \
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.f_sys = DT_SIFIVE_SPI0_##n##_CLOCK_FREQUENCY, \
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}; \
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DEVICE_AND_API_INIT(spi_##n, \
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DT_SIFIVE_SPI0_##n##_LABEL, \
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spi_sifive_init, \
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&spi_sifive_data_##n, \
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&spi_sifive_cfg_##n, \
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POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, \
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&spi_sifive_api)
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#ifndef CONFIG_SIFIVE_SPI_0_ROM
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#ifdef DT_SIFIVE_SPI0_0_LABEL
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SPI_INIT(0);
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#endif /* DT_SIFIVE_SPI0_0_LABEL */
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#endif /* !DT_SIFIVE_SPI0_0_ROM */
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#ifdef DT_SIFIVE_SPI0_1_LABEL
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SPI_INIT(1);
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#endif /* DT_SIFIVE_SPI0_1_LABEL */
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#ifdef DT_SIFIVE_SPI0_2_LABEL
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SPI_INIT(2);
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#endif /* DT_SIFIVE_SPI0_2_LABEL */
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75
drivers/spi/spi_sifive.h
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75
drivers/spi/spi_sifive.h
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2018 SiFive Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SPI_SIFIVE__H
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#define _SPI_SIFIVE__H
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#include "spi_context.h"
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#include <sys_io.h>
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#include <device.h>
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#include <spi.h>
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#define SPI_CFG(dev) ((struct spi_sifive_cfg *) ((dev)->config->config_info))
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#define SPI_DATA(dev) ((struct spi_sifive_data *) ((dev)->driver_data))
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#define SPI_REG(dev, offset) ((mem_addr_t) (SPI_CFG(dev)->base + (offset)))
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/* Register Offsets */
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#define REG_SCKDIV 0x000
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#define REG_SCKMODE 0x004
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#define REG_CSID 0x010
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#define REG_CSDEF 0x014
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#define REG_CSMODE 0x018
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#define REG_DELAY0 0x028
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#define REG_DELAY1 0x02C
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#define REG_FMT 0x040
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#define REG_TXDATA 0x048
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#define REG_RXDATA 0x04C
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#define REG_TXMARK 0x050
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#define REG_RXMARK 0x054
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#define REG_FCTRL 0x060
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#define REG_FFMT 0x064
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#define REG_IE 0x070
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#define REG_IP 0x074
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/* Masks */
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#define SF_SCKDIV_DIV_MASK (0xFFF << 0)
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#define SF_FMT_PROTO_MASK (0x3 << 0)
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#define SF_FMT_LEN_MASK (0xF << 16)
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/* Offsets */
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#define SF_SCKMODE_POL 1
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#define SF_SCKMODE_PHA 0
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#define SF_FMT_LEN 16
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#define SF_FMT_ENDIAN 2
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#define SF_FCTRL_EN 0
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/* Values */
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#define SF_CSMODE_AUTO 0
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#define SF_CSMODE_HOLD 2
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#define SF_CSMODE_OFF 3
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#define SF_FMT_PROTO_SINGLE 0
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#define SF_TXDATA_FULL (1 << 31)
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#define SF_RXDATA_EMPTY (1 << 31)
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/* Structure Declarations */
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struct spi_sifive_data {
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struct spi_context ctx;
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};
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struct spi_sifive_cfg {
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u32_t base;
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u32_t f_sys;
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};
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#endif /* _SPI_SIFIVE__H */
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