drivers: uart_pl011: Implemented runtime configure
Implemented runtime configure functions for the driver. Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
This commit is contained in:
Lukas Gehreke
Anas Nashif
parent
95bf346b3b
commit
9e06a8a1e6
1 changed files with 123 additions and 15 deletions
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@ -9,6 +9,7 @@
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#define DT_DRV_COMPAT arm_pl011
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#define SBSA_COMPAT arm_sbsa_uart
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#include <string.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/init.h>
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@ -44,7 +45,7 @@ struct pl011_config {
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/* Device data structure */
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struct pl011_data {
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DEVICE_MMIO_RAM;
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uint32_t baud_rate; /* Baud rate */
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struct uart_config uart_cfg;
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bool sbsa; /* SBSA mode */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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volatile bool sw_call_txdrdy;
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@ -139,6 +140,115 @@ static void pl011_poll_out(const struct device *dev,
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get_uart(dev)->dr = (uint32_t)c;
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}
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static int pl011_runtime_configure_internal(const struct device *dev,
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const struct uart_config *cfg,
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bool disable)
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{
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const struct pl011_config *config = dev->config;
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struct pl011_data *data = dev->data;
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uint32_t lcrh;
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int ret = -ENOTSUP;
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if (data->sbsa) {
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goto out;
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}
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if (disable) {
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pl011_disable(dev);
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pl011_disable_fifo(dev);
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}
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lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK | PL011_LCRH_STP2);
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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lcrh &= ~(BIT(1) | BIT(2));
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break;
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case UART_CFG_PARITY_ODD:
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lcrh |= PL011_LCRH_PARITY_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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lcrh |= PL011_LCRH_PARTIY_EVEN;
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break;
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default:
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goto enable;
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}
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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lcrh &= ~(PL011_LCRH_STP2);
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break;
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case UART_CFG_STOP_BITS_2:
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lcrh |= PL011_LCRH_STP2;
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break;
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default:
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goto enable;
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}
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switch (cfg->data_bits) {
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case UART_CFG_DATA_BITS_5:
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lcrh |= PL011_LCRH_WLEN_SIZE(5) << PL011_LCRH_WLEN_SHIFT;
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break;
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case UART_CFG_DATA_BITS_6:
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lcrh |= PL011_LCRH_WLEN_SIZE(6) << PL011_LCRH_WLEN_SHIFT;
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break;
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case UART_CFG_DATA_BITS_7:
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lcrh |= PL011_LCRH_WLEN_SIZE(7) << PL011_LCRH_WLEN_SHIFT;
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break;
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case UART_CFG_DATA_BITS_8:
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lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
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break;
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default:
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goto enable;
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}
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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break;
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default:
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goto enable;
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}
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/* Set baud rate */
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ret = pl011_set_baudrate(dev, config->sys_clk_freq, cfg->baudrate);
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if (ret != 0) {
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goto enable;
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}
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/* Update settings */
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get_uart(dev)->lcr_h = lcrh;
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memcpy(&data->uart_cfg, cfg, sizeof(data->uart_cfg));
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enable:
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if (disable) {
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pl011_enable_fifo(dev);
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pl011_enable(dev);
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}
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out:
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return ret;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int pl011_runtime_configure(const struct device *dev,
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const struct uart_config *cfg)
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{
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return pl011_runtime_configure_internal(dev, cfg, true);
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}
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static int pl011_runtime_config_get(const struct device *dev,
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struct uart_config *cfg)
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{
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struct pl011_data *data = dev->data;
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*cfg = data->uart_cfg;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int pl011_fifo_fill(const struct device *dev,
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const uint8_t *tx_data, int len)
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@ -268,6 +378,10 @@ static void pl011_irq_callback_set(const struct device *dev,
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static const struct uart_driver_api pl011_driver_api = {
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.poll_in = pl011_poll_in,
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.poll_out = pl011_poll_out,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = pl011_runtime_configure,
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.config_get = pl011_runtime_config_get,
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#endif
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = pl011_fifo_fill,
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.fifo_read = pl011_fifo_read,
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@ -291,7 +405,6 @@ static int pl011_init(const struct device *dev)
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const struct pl011_config *config = dev->config;
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struct pl011_data *data = dev->data;
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int ret;
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uint32_t lcrh;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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@ -324,18 +437,7 @@ static int pl011_init(const struct device *dev)
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}
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}
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/* Set baud rate */
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ret = pl011_set_baudrate(dev, config->sys_clk_freq,
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data->baud_rate);
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if (ret != 0) {
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return ret;
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}
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/* Setting the default character format */
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lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
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lcrh &= ~(BIT(0) | BIT(7));
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lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
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get_uart(dev)->lcr_h = lcrh;
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pl011_runtime_configure_internal(dev, &data->uart_cfg, false);
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/* Setting transmit and receive interrupt FIFO level */
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get_uart(dev)->ifls = FIELD_PREP(PL011_IFLS_TXIFLSEL_M, TXIFLSEL_1_8_FULL)
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@ -439,7 +541,13 @@ void pl011_isr(const struct device *dev)
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PL011_CONFIG_PORT(n) \
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\
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static struct pl011_data pl011_data_port_##n = { \
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.baud_rate = DT_INST_PROP(n, current_speed), \
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.uart_cfg = { \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.parity = UART_CFG_PARITY_NONE, \
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.stop_bits = UART_CFG_STOP_BITS_1, \
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.data_bits = UART_CFG_DATA_BITS_8, \
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.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &pl011_init, \
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