diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 28b8d438e6b..211d101439d 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -220,8 +220,8 @@ static void i2c_stm32_irq_config_func_1(struct device *port); static const struct i2c_stm32_config i2c_stm32_cfg_1 = { .i2c = (I2C_TypeDef *)CONFIG_I2C_1_BASE_ADDRESS, .pclken = { - .enr = LL_APB1_GRP1_PERIPH_I2C1, - .bus = STM32_CLOCK_BUS_APB1, + .enr = CONFIG_I2C_1_CLOCK_BITS, + .bus = CONFIG_I2C_1_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_1, @@ -266,8 +266,8 @@ static void i2c_stm32_irq_config_func_2(struct device *port); static const struct i2c_stm32_config i2c_stm32_cfg_2 = { .i2c = (I2C_TypeDef *)CONFIG_I2C_2_BASE_ADDRESS, .pclken = { - .enr = LL_APB1_GRP1_PERIPH_I2C2, - .bus = STM32_CLOCK_BUS_APB1, + .enr = CONFIG_I2C_2_CLOCK_BITS, + .bus = CONFIG_I2C_2_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_2, @@ -316,8 +316,8 @@ static void i2c_stm32_irq_config_func_3(struct device *port); static const struct i2c_stm32_config i2c_stm32_cfg_3 = { .i2c = (I2C_TypeDef *)CONFIG_I2C_3_BASE_ADDRESS, .pclken = { - .enr = LL_APB1_GRP1_PERIPH_I2C3, - .bus = STM32_CLOCK_BUS_APB1, + .enr = CONFIG_I2C_3_CLOCK_BITS, + .bus = CONFIG_I2C_3_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_3, @@ -360,8 +360,8 @@ static void i2c_stm32_irq_config_func_4(struct device *port); static const struct i2c_stm32_config i2c_stm32_cfg_4 = { .i2c = (I2C_TypeDef *)CONFIG_I2C_4_BASE_ADDRESS, .pclken = { - .enr = LL_APB1_GRP2_PERIPH_I2C4, - .bus = STM32_CLOCK_BUS_APB1_2, + .enr = CONFIG_I2C_4_CLOCK_BITS, + .bus = CONFIG_I2C_4_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_4, @@ -390,4 +390,3 @@ static void i2c_stm32_irq_config_func_4(struct device *dev) #endif #endif /* CONFIG_I2C_4 */ - diff --git a/soc/arm/st_stm32/stm32f0/dts_fixup.h b/soc/arm/st_stm32/stm32f0/dts_fixup.h index 7cbc106b57b..c2c694e7382 100644 --- a/soc/arm/st_stm32/stm32f0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f0/dts_fixup.h @@ -19,12 +19,16 @@ #define CONFIG_I2C_1_NAME ST_STM32_I2C_V2_40005400_LABEL #define CONFIG_I2C_1_COMBINED_IRQ ST_STM32_I2C_V2_40005400_IRQ_COMBINED #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V2_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS #define CONFIG_I2C_2_COMBINED_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_2_NAME ST_STM32_I2C_V2_40005800_LABEL #define CONFIG_I2C_2_COMBINED_IRQ ST_STM32_I2C_V2_40005800_IRQ_COMBINED #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V2_40005800_CLOCK_BUS #define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY diff --git a/soc/arm/st_stm32/stm32f1/dts_fixup.h b/soc/arm/st_stm32/stm32f1/dts_fixup.h index 61920cbd954..f60c9edea25 100644 --- a/soc/arm/st_stm32/stm32f1/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f1/dts_fixup.h @@ -33,6 +33,8 @@ #define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_IRQ_EVENT #define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_IRQ_ERROR #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V1_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V1_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V1_40005800_BASE_ADDRESS #define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY @@ -41,6 +43,8 @@ #define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V1_40005800_IRQ_EVENT #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V1_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V1_40005800_CLOCK_BUS #define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY diff --git a/soc/arm/st_stm32/stm32f3/dts_fixup.h b/soc/arm/st_stm32/stm32f3/dts_fixup.h index 566db28378d..30fcf8224b5 100644 --- a/soc/arm/st_stm32/stm32f3/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f3/dts_fixup.h @@ -27,6 +27,8 @@ #define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V2_40005400_IRQ_EVENT #define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V2_40005400_IRQ_ERROR #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V2_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS #define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY @@ -35,6 +37,8 @@ #define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V2_40005800_IRQ_EVENT #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V2_40005800_CLOCK_BUS #define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V2_40007800_BASE_ADDRESS #define CONFIG_I2C_3_EVENT_IRQ_PRI ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY @@ -43,6 +47,8 @@ #define CONFIG_I2C_3_EVENT_IRQ ST_STM32_I2C_V2_40007800_IRQ_EVENT #define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V2_40007800_IRQ_ERROR #define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY +#define CONFIG_I2C_3_CLOCK_BITS ST_STM32_I2C_V2_40007800_CLOCK_BITS +#define CONFIG_I2C_3_CLOCK_BUS ST_STM32_I2C_V2_40007800_CLOCK_BUS #define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY diff --git a/soc/arm/st_stm32/stm32f4/dts_fixup.h b/soc/arm/st_stm32/stm32f4/dts_fixup.h index 79d74c71a15..c6aa63848bf 100644 --- a/soc/arm/st_stm32/stm32f4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f4/dts_fixup.h @@ -33,6 +33,8 @@ #define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_IRQ_EVENT #define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_IRQ_ERROR #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V1_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V1_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V1_40005800_BASE_ADDRESS #define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY @@ -41,6 +43,8 @@ #define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V1_40005800_IRQ_EVENT #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V1_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V1_40005800_CLOCK_BUS #define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V1_40005C00_BASE_ADDRESS #define CONFIG_I2C_3_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY @@ -49,6 +53,8 @@ #define CONFIG_I2C_3_EVENT_IRQ ST_STM32_I2C_V1_40005C00_IRQ_EVENT #define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V1_40005C00_IRQ_ERROR #define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY +#define CONFIG_I2C_3_CLOCK_BITS ST_STM32_I2C_V1_40005C00_CLOCK_BITS +#define CONFIG_I2C_3_CLOCK_BUS ST_STM32_I2C_V1_40005C00_CLOCK_BUS #define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY diff --git a/soc/arm/st_stm32/stm32f7/dts_fixup.h b/soc/arm/st_stm32/stm32f7/dts_fixup.h index b80a5526745..ff1cfd304de 100644 --- a/soc/arm/st_stm32/stm32f7/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f7/dts_fixup.h @@ -57,6 +57,8 @@ #define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V2_40005400_IRQ_EVENT #define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V2_40005400_IRQ_ERROR #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V2_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS #define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY @@ -65,6 +67,8 @@ #define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V2_40005800_IRQ_EVENT #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V2_40005800_CLOCK_BUS #define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V2_40005C00_BASE_ADDRESS #define CONFIG_I2C_3_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY @@ -73,6 +77,8 @@ #define CONFIG_I2C_3_EVENT_IRQ ST_STM32_I2C_V2_40005C00_IRQ_EVENT #define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V2_40005C00_IRQ_ERROR #define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY +#define CONFIG_I2C_3_CLOCK_BITS ST_STM32_I2C_V2_40005C00_CLOCK_BITS +#define CONFIG_I2C_3_CLOCK_BUS ST_STM32_I2C_V2_40005C00_CLOCK_BUS #define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY diff --git a/soc/arm/st_stm32/stm32l0/dts_fixup.h b/soc/arm/st_stm32/stm32l0/dts_fixup.h index fcd6919e960..30b594a2b7a 100644 --- a/soc/arm/st_stm32/stm32l0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32l0/dts_fixup.h @@ -25,18 +25,24 @@ #define CONFIG_I2C_1_NAME ST_STM32_I2C_V2_40005400_LABEL #define CONFIG_I2C_1_COMBINED_IRQ ST_STM32_I2C_V2_40005400_IRQ_COMBINED #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V2_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS #define CONFIG_I2C_2_COMBINED_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_2_NAME ST_STM32_I2C_V2_40005800_LABEL #define CONFIG_I2C_2_COMBINED_IRQ ST_STM32_I2C_V2_40005800_IRQ_COMBINED #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V2_40005800_CLOCK_BUS #define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V2_40007800_BASE_ADDRESS #define CONFIG_I2C_3_COMBINED_IRQ_PRI ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_3_NAME ST_STM32_I2C_V2_40007800_LABEL #define CONFIG_I2C_3_COMBINED_IRQ ST_STM32_I2C_V2_40007800_IRQ_COMBINED #define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY +#define CONFIG_I2C_3_CLOCK_BITS ST_STM32_I2C_V2_40007800_CLOCK_BITS +#define CONFIG_I2C_3_CLOCK_BUS ST_STM32_I2C_V2_40007800_CLOCK_BUS #define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY diff --git a/soc/arm/st_stm32/stm32l4/dts_fixup.h b/soc/arm/st_stm32/stm32l4/dts_fixup.h index 0e201e1dfac..81410cf2936 100644 --- a/soc/arm/st_stm32/stm32l4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32l4/dts_fixup.h @@ -45,6 +45,8 @@ #define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V2_40005400_IRQ_EVENT #define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V2_40005400_IRQ_ERROR #define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define CONFIG_I2C_1_CLOCK_BITS ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define CONFIG_I2C_1_CLOCK_BUS ST_STM32_I2C_V2_40005400_CLOCK_BUS #define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS #define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY @@ -53,6 +55,8 @@ #define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V2_40005800_IRQ_EVENT #define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR #define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define CONFIG_I2C_2_CLOCK_BITS ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define CONFIG_I2C_2_CLOCK_BUS ST_STM32_I2C_V2_40005800_CLOCK_BUS #define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V2_40005C00_BASE_ADDRESS #define CONFIG_I2C_3_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY @@ -61,6 +65,8 @@ #define CONFIG_I2C_3_EVENT_IRQ ST_STM32_I2C_V2_40005C00_IRQ_EVENT #define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V2_40005C00_IRQ_ERROR #define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY +#define CONFIG_I2C_3_CLOCK_BITS ST_STM32_I2C_V2_40005C00_CLOCK_BITS +#define CONFIG_I2C_3_CLOCK_BUS ST_STM32_I2C_V2_40005C00_CLOCK_BUS #define CONFIG_I2C_4_BASE_ADDRESS ST_STM32_I2C_V2_40008400_BASE_ADDRESS #define CONFIG_I2C_4_EVENT_IRQ_PRI ST_STM32_I2C_V2_40008400_IRQ_EVENT_PRIORITY @@ -69,6 +75,8 @@ #define CONFIG_I2C_4_EVENT_IRQ ST_STM32_I2C_V2_40008400_IRQ_EVENT #define CONFIG_I2C_4_ERROR_IRQ ST_STM32_I2C_V2_40008400_IRQ_ERROR #define CONFIG_I2C_4_BITRATE ST_STM32_I2C_V2_40008400_CLOCK_FREQUENCY +#define CONFIG_I2C_4_CLOCK_BITS ST_STM32_I2C_V2_40008400_CLOCK_BITS +#define CONFIG_I2C_4_CLOCK_BUS ST_STM32_I2C_V2_40008400_CLOCK_BUS #define CONFIG_RTC_0_BASE_ADDRESS ST_STM32_RTC_40002800_BASE_ADDRESS #define CONFIG_RTC_0_IRQ_PRI ST_STM32_RTC_40002800_IRQ_0_PRIORITY