soc: xtensa: adsp: add support for NXP ADSP
Add a common part for all i.MX boards. Add support for i.MX8, which represents i.MX8QM. This has a 1 Xtensa HiFi4 core, with 64 KB TCM, 448 KB OCRAM, 8MB SDRAM and 1 ESAI, 1 SAI as audio interfaces. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit is contained in:
Iuliana Prodan
Christopher Friedt
parent
a5fdf26ca0
commit
9dcd562608
16 changed files with 1196 additions and 0 deletions
6
soc/xtensa/nxp_adsp/CMakeLists.txt
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6
soc/xtensa/nxp_adsp/CMakeLists.txt
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@ -0,0 +1,6 @@
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# NXP i.MX8 SoC family CMake file
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#
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(common)
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19
soc/xtensa/nxp_adsp/Kconfig
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19
soc/xtensa/nxp_adsp/Kconfig
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# NXP i.MX8 SoC family configuration options
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#
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_NXP_ADSP
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bool
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select ARCH_HAS_COHERENCE
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if SOC_FAMILY_NXP_ADSP
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config SOC_FAMILY
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string
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default "nxp_adsp"
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# Select SoC Part No. and configuration options
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source "soc/xtensa/nxp_adsp/*/Kconfig.soc"
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endif # SOC_FAMILY_NXP_ADSP
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6
soc/xtensa/nxp_adsp/Kconfig.defconfig
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6
soc/xtensa/nxp_adsp/Kconfig.defconfig
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# NXP i.MX8 SoC family default configuration options
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#
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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source "soc/xtensa/nxp_adsp/*/Kconfig.defconfig.series"
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6
soc/xtensa/nxp_adsp/Kconfig.soc
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6
soc/xtensa/nxp_adsp/Kconfig.soc
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@ -0,0 +1,6 @@
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# NXP i.MX8 SoC series selection
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#
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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source "soc/xtensa/nxp_adsp/*/Kconfig.series"
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17
soc/xtensa/nxp_adsp/common/CMakeLists.txt
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17
soc/xtensa/nxp_adsp/common/CMakeLists.txt
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# NXP SoC family CMake file
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#
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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zephyr_interface_library_named(NXP_ADSP_COMMON)
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zephyr_library_named(nxp_adsp_common)
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zephyr_library_include_directories(include)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_library_sources(soc.c)
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zephyr_library_link_libraries(NXP_ADSP_COMMON)
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target_include_directories(NXP_ADSP_COMMON INTERFACE include)
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target_link_libraries(NXP_ADSP_COMMON INTERFACE nxp_adsp_common)
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18
soc/xtensa/nxp_adsp/common/include/adsp/cache.h
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soc/xtensa/nxp_adsp/common/include/adsp/cache.h
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/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __COMMON_ADSP_CACHE_H__
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#define __COMMON_ADSP_CACHE_H__
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#include <xtensa/hal.h>
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/* Macros for data cache operations */
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#define SOC_DCACHE_FLUSH(addr, size) \
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z_xtensa_cache_flush((addr), (size))
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#define SOC_DCACHE_INVALIDATE(addr, size) \
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z_xtensa_cache_inv((addr), (size))
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#endif
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41
soc/xtensa/nxp_adsp/common/include/adsp/io.h
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41
soc/xtensa/nxp_adsp/common/include/adsp/io.h
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/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INCLUDE_IO__
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#define __INCLUDE_IO__
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#include <stdint.h>
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#include <soc/memory.h>
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#include <sys/sys_io.h>
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#include <arch/common/sys_io.h>
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static inline uint32_t io_reg_read(uint32_t reg)
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{
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return sys_read32(reg);
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}
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static inline void io_reg_write(uint32_t reg, uint32_t val)
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{
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sys_write32(val, reg);
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}
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static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
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uint32_t value)
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{
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io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
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}
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static inline uint16_t io_reg_read16(uint32_t reg)
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{
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return sys_read16(reg);
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}
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static inline void io_reg_write16(uint32_t reg, uint16_t val)
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{
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sys_write16(val, reg);
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}
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#endif
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33
soc/xtensa/nxp_adsp/common/include/soc.h
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33
soc/xtensa/nxp_adsp/common/include/soc.h
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/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <errno.h>
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#include <sys/sys_io.h>
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#include <adsp/cache.h>
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#ifndef __INC_IMX_SOC_H
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#define __INC_IMX_SOC_H
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/* Macros related to interrupt handling */
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#define XTENSA_IRQ_NUM_SHIFT 0
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#define XTENSA_IRQ_NUM_MASK 0xff
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/*
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* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
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*
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* 1. Peripheral Register bit offset.
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*/
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#define XTENSA_IRQ_NUMBER(_irq) \
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((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
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extern void z_soc_irq_enable(uint32_t irq);
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extern void z_soc_irq_disable(uint32_t irq);
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extern int z_soc_irq_is_enabled(unsigned int irq);
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#endif /* __INC_IMX_SOC_H */
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46
soc/xtensa/nxp_adsp/common/soc.c
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46
soc/xtensa/nxp_adsp/common/soc.c
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/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <xtensa/xtruntime.h>
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#include <irq_nextlevel.h>
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#include <xtensa/hal.h>
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#include <init.h>
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#include "soc.h"
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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#include <sw_isr_table.h>
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#endif
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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void z_soc_irq_enable(uint32_t irq)
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{
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/*
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* enable core interrupt
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*/
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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}
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void z_soc_irq_disable(uint32_t irq)
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{
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/*
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* disable the interrupt in interrupt controller
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*/
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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int ret = 0;
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/* regular interrupt */
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ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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return ret;
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}
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53
soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series
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53
soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NXP_IMX8
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config SOC_SERIES
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string
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default "imx8"
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config SOC_TOOLCHAIN_NAME
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string
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default "nxp_imx_adsp"
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config SOC
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string
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default "nxp_imx8"
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config SMP
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default n
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config XTENSA_TIMER
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default y
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 400000000 if XTENSA_TIMER
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config SYS_CLOCK_TICKS_PER_SEC
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default 50000
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config IRQ_OFFLOAD_INTNUM
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default 0
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config KERNEL_ENTRY
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default "__start"
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config MULTI_LEVEL_INTERRUPTS
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default n
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config 2ND_LEVEL_INTERRUPTS
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default n
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config DYNAMIC_INTERRUPTS
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default y
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config LOG
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default y
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# To prevent test uses TEST_LOGGING_MINIMAL
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config TEST_LOGGING_DEFAULTS
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default n
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depends on TEST
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endif # SOC_SERIES_NXP_IMX8
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13
soc/xtensa/nxp_adsp/imx8/Kconfig.series
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13
soc/xtensa/nxp_adsp/imx8/Kconfig.series
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NXP_IMX8
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bool "NXP i.MX8"
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select SOC_FAMILY_NXP_ADSP
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select XTENSA
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select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
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select XTENSA_RESET_VECTOR
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select XTENSA_USE_CORE_CRT1
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select ATOMIC_OPERATIONS_BUILTIN
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help
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NXP i.MX8
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11
soc/xtensa/nxp_adsp/imx8/Kconfig.soc
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11
soc/xtensa/nxp_adsp/imx8/Kconfig.soc
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# Copyright (c) 2021 NXP
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "NXP i.MX SoC Selection"
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config SOC_NXP_IMX8
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bool "i.MX8 SoC"
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depends on SOC_SERIES_NXP_IMX8
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endchoice
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177
soc/xtensa/nxp_adsp/imx8/include/_soc_inthandlers.h
Normal file
177
soc/xtensa/nxp_adsp/imx8/include/_soc_inthandlers.h
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/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* Functions here are designed to produce efficient code to
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* search an Xtensa bitmask of interrupts, inspecting only those bits
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* declared to be associated with a given interrupt level. Each
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* dispatcher will handle exactly one flagged interrupt, in numerical
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* order (low bits first) and will return a mask of that bit that can
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* then be cleared by the calling code. Unrecognized bits for the
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* level will invoke an error handler.
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*/
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#include <xtensa/config/core-isa.h>
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#include <sys/util.h>
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#include <sw_isr_table.h>
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#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2
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||||||
|
#error core-isa.h interrupt level does not match dispatcher!
|
||||||
|
#endif
|
||||||
|
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2
|
||||||
|
#error core-isa.h interrupt level does not match dispatcher!
|
||||||
|
#endif
|
||||||
|
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2
|
||||||
|
#error core-isa.h interrupt level does not match dispatcher!
|
||||||
|
#endif
|
||||||
|
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2
|
||||||
|
#error core-isa.h interrupt level does not match dispatcher!
|
||||||
|
#endif
|
||||||
|
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2
|
||||||
|
#error core-isa.h interrupt level does not match dispatcher!
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||||
|
{
|
||||||
|
int irq;
|
||||||
|
|
||||||
|
if (mask & BIT(8)) {
|
||||||
|
mask = BIT(8);
|
||||||
|
irq = 8;
|
||||||
|
goto handle_irq;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
handle_irq:
|
||||||
|
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||||
|
return mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||||
|
{
|
||||||
|
int irq;
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
mask &= XCHAL_INTLEVEL2_MASK;
|
||||||
|
for (i = 0; i <= 31; i++)
|
||||||
|
if (mask & BIT(i)) {
|
||||||
|
mask = BIT(i);
|
||||||
|
irq = i;
|
||||||
|
goto handle_irq;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
handle_irq:
|
||||||
|
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||||
|
return mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||||
|
{
|
||||||
|
int irq;
|
||||||
|
|
||||||
|
if (mask & BIT(1)) {
|
||||||
|
mask = BIT(1);
|
||||||
|
irq = 1;
|
||||||
|
goto handle_irq;
|
||||||
|
}
|
||||||
|
if (mask & BIT(3)) {
|
||||||
|
mask = BIT(3);
|
||||||
|
irq = 3;
|
||||||
|
goto handle_irq;
|
||||||
|
}
|
||||||
|
if (mask & BIT(31)) {
|
||||||
|
mask = BIT(31);
|
||||||
|
irq = 31;
|
||||||
|
goto handle_irq;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
handle_irq:
|
||||||
|
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||||
|
return mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||||
|
{
|
||||||
|
int irq;
|
||||||
|
|
||||||
|
if (mask & BIT(0)) {
|
||||||
|
mask = BIT(0);
|
||||||
|
irq = 0;
|
||||||
|
goto handle_irq;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
handle_irq:
|
||||||
|
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||||
|
return mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
214
soc/xtensa/nxp_adsp/imx8/include/soc/memory.h
Normal file
214
soc/xtensa/nxp_adsp/imx8/include/soc/memory.h
Normal file
|
|
@ -0,0 +1,214 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2021 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __INC_MEMORY_H
|
||||||
|
#define __INC_MEMORY_H
|
||||||
|
|
||||||
|
#define PLATFORM_CORE_COUNT 1
|
||||||
|
|
||||||
|
/** Id of master DSP core */
|
||||||
|
#define PLATFORM_PRIMARY_CORE_ID 0
|
||||||
|
|
||||||
|
#define IRAM_RESERVE_HEADER_SPACE 0x400
|
||||||
|
|
||||||
|
#define IRAM_BASE 0x596f8000
|
||||||
|
#define IRAM_SIZE 0x800
|
||||||
|
|
||||||
|
#define SDRAM0_BASE 0x92400000
|
||||||
|
#define SDRAM0_SIZE 0x800000
|
||||||
|
|
||||||
|
#define SDRAM1_BASE 0x92C00000
|
||||||
|
#define SDRAM1_SIZE 0x800000
|
||||||
|
|
||||||
|
/* The reset vector address in SRAM and its size */
|
||||||
|
#define MEM_RESET_TEXT_SIZE 0x2e0
|
||||||
|
#define MEM_RESET_LIT_SIZE 0x120
|
||||||
|
|
||||||
|
/* This is the base address of all the vectors defined in IRAM */
|
||||||
|
#define XCHAL_VECBASE_RESET_PADDR_IRAM \
|
||||||
|
(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
|
||||||
|
|
||||||
|
#define MEM_VECBASE_LIT_SIZE 0x178
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EXCEPTIONS and VECTORS
|
||||||
|
*/
|
||||||
|
#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x596F8000
|
||||||
|
|
||||||
|
/* Vector and literal sizes */
|
||||||
|
#define MEM_VECT_LIT_SIZE 0x4
|
||||||
|
#define MEM_VECT_TEXT_SIZE 0x30
|
||||||
|
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
|
||||||
|
MEM_VECT_LIT_SIZE)
|
||||||
|
|
||||||
|
/* The addresses of the vectors.
|
||||||
|
* Only the mem_error vector continues to point to its ROM address.
|
||||||
|
*/
|
||||||
|
#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
|
||||||
|
|
||||||
|
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
|
||||||
|
|
||||||
|
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
|
||||||
|
|
||||||
|
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
|
||||||
|
|
||||||
|
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
|
||||||
|
|
||||||
|
#define XCHAL_USER_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_KERNEL_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
|
||||||
|
|
||||||
|
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
|
||||||
|
(XCHAL_USER_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE)
|
||||||
|
|
||||||
|
/* Location for the intList section which is later used to construct the
|
||||||
|
* Interrupt Descriptor Table (IDT). This is a bogus address as this
|
||||||
|
* section will be stripped off in the final image.
|
||||||
|
*/
|
||||||
|
#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
|
||||||
|
|
||||||
|
/* size of the Interrupt Descriptor Table (IDT) */
|
||||||
|
#define IDT_SIZE 0x2000
|
||||||
|
|
||||||
|
/* physical DSP addresses */
|
||||||
|
#define IRAM_BASE 0x596f8000
|
||||||
|
#define IRAM_SIZE 0x800
|
||||||
|
|
||||||
|
#define DRAM0_BASE 0x596e8000
|
||||||
|
#define DRAM0_SIZE 0x8000
|
||||||
|
|
||||||
|
#define DRAM1_BASE 0x596f0000
|
||||||
|
#define DRAM1_SIZE 0x8000
|
||||||
|
|
||||||
|
#define SDRAM0_BASE 0x92400000
|
||||||
|
#define SDRAM0_SIZE 0x800000
|
||||||
|
|
||||||
|
#define SDRAM1_BASE 0x92C00000
|
||||||
|
#define SDRAM1_SIZE 0x800000
|
||||||
|
|
||||||
|
#define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000
|
||||||
|
#define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR
|
||||||
|
|
||||||
|
#define EDMA0_BASE 0x59200000
|
||||||
|
#define EDMA0_SIZE 0x10000
|
||||||
|
|
||||||
|
#define ESAI_BASE 0x59010000
|
||||||
|
#define ESAI_SIZE 0x00010000
|
||||||
|
|
||||||
|
#define SAI_1_BASE 0x59050000
|
||||||
|
#define SAI_1_SIZE 0x00010000
|
||||||
|
|
||||||
|
#define UUID_ENTRY_ELF_BASE 0x1FFFA000
|
||||||
|
#define UUID_ENTRY_ELF_SIZE 0x6000
|
||||||
|
|
||||||
|
#define LOG_ENTRY_ELF_BASE 0x20000000
|
||||||
|
#define LOG_ENTRY_ELF_SIZE 0x2000000
|
||||||
|
|
||||||
|
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
|
||||||
|
#define EXT_MANIFEST_ELF_SIZE 0x2000000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Heap and Stack on i.MX8 are organized like this :-
|
||||||
|
*
|
||||||
|
* +--------------------------------------------------------------------------+
|
||||||
|
* | Offset | Region | Size |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
* | SDRAM_BASE | RO Data | SOF_DATA_SIZE |
|
||||||
|
* | | Data | |
|
||||||
|
* | | BSS | |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
* | SOF_STACK_BASE | | |
|
||||||
|
* +---------------------+----------------+-----------------------------------+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SRAM_OUTBOX_BASE SDRAM1_BASE
|
||||||
|
#define SRAM_OUTBOX_SIZE 0x1000
|
||||||
|
#define SRAM_OUTBOX_OFFSET 0
|
||||||
|
|
||||||
|
#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
|
||||||
|
#define SRAM_INBOX_SIZE 0x1000
|
||||||
|
#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
|
||||||
|
|
||||||
|
#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
|
||||||
|
#define SRAM_DEBUG_SIZE 0x800
|
||||||
|
#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
|
||||||
|
|
||||||
|
#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
|
||||||
|
#define SRAM_EXCEPT_SIZE 0x800
|
||||||
|
#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
|
||||||
|
|
||||||
|
#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
|
||||||
|
#define SRAM_STREAM_SIZE 0x1000
|
||||||
|
#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
|
||||||
|
|
||||||
|
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
|
||||||
|
#define SRAM_TRACE_SIZE 0x1000
|
||||||
|
#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
|
||||||
|
|
||||||
|
#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
|
||||||
|
+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
|
||||||
|
+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
|
||||||
|
|
||||||
|
/* Heap section sizes for module pool */
|
||||||
|
#define HEAP_RT_COUNT8 0
|
||||||
|
#define HEAP_RT_COUNT16 48
|
||||||
|
#define HEAP_RT_COUNT32 48
|
||||||
|
#define HEAP_RT_COUNT64 32
|
||||||
|
#define HEAP_RT_COUNT128 32
|
||||||
|
#define HEAP_RT_COUNT256 32
|
||||||
|
#define HEAP_RT_COUNT512 4
|
||||||
|
#define HEAP_RT_COUNT1024 4
|
||||||
|
#define HEAP_RT_COUNT2048 4
|
||||||
|
|
||||||
|
/* Heap section sizes for system runtime heap */
|
||||||
|
#define HEAP_SYS_RT_COUNT64 128
|
||||||
|
#define HEAP_SYS_RT_COUNT512 16
|
||||||
|
#define HEAP_SYS_RT_COUNT1024 8
|
||||||
|
|
||||||
|
/* Heap configuration */
|
||||||
|
#define HEAP_SYSTEM_BASE SDRAM1_BASE + SOF_MAILBOX_SIZE
|
||||||
|
#define HEAP_SYSTEM_SIZE 0xe000
|
||||||
|
|
||||||
|
#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
|
||||||
|
#define HEAP_SYS_RUNTIME_SIZE \
|
||||||
|
(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
|
||||||
|
HEAP_SYS_RT_COUNT1024 * 1024)
|
||||||
|
|
||||||
|
#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
|
||||||
|
#define HEAP_RUNTIME_SIZE \
|
||||||
|
(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
|
||||||
|
HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
|
||||||
|
HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
|
||||||
|
HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \
|
||||||
|
HEAP_RT_COUNT2048 * 2048)
|
||||||
|
|
||||||
|
#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
|
||||||
|
#define HEAP_BUFFER_SIZE \
|
||||||
|
(SDRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -\
|
||||||
|
HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
|
||||||
|
|
||||||
|
/* Stack configuration */
|
||||||
|
#define SOF_STACK_SIZE 0x1000
|
||||||
|
#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE
|
||||||
|
#define SOF_STACK_BASE (SDRAM1_BASE + SDRAM1_SIZE)
|
||||||
|
#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
|
||||||
|
|
||||||
|
/* Host page size */
|
||||||
|
#define HOST_PAGE_SIZE 4096
|
||||||
|
|
||||||
|
#endif /* __INC_MEMORY_H */
|
||||||
21
soc/xtensa/nxp_adsp/imx8/include/soc/platform.h
Normal file
21
soc/xtensa/nxp_adsp/imx8/include/soc/platform.h
Normal file
|
|
@ -0,0 +1,21 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2021 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __PLATFORM_PLATFORM_H__
|
||||||
|
#define __PLATFORM_PLATFORM_H__
|
||||||
|
|
||||||
|
#define PLATFORM_PRIMARY_CORE_ID 0
|
||||||
|
|
||||||
|
#define MAX_CORE_COUNT 1
|
||||||
|
|
||||||
|
#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
|
||||||
|
#error "Invalid core count - exceeding core limit"
|
||||||
|
/* IPC Interrupt */
|
||||||
|
#define PLATFORM_IPC_INTERRUPT IRQ_NUM_MU
|
||||||
|
#define PLATFORM_IPC_INTERRUPT_NAME NULL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __PLATFORM_PLATFORM_H__ */
|
||||||
515
soc/xtensa/nxp_adsp/imx8/linker.ld
Normal file
515
soc/xtensa/nxp_adsp/imx8/linker.ld
Normal file
|
|
@ -0,0 +1,515 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2021 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file
|
||||||
|
* @brief Linker command/script file
|
||||||
|
*
|
||||||
|
* Linker script for the NXP i.MX8 platform
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_ARCH(xtensa)
|
||||||
|
|
||||||
|
#include <devicetree.h>
|
||||||
|
#include <xtensa/config/core-isa.h>
|
||||||
|
#include <soc/memory.h>
|
||||||
|
#include <autoconf.h>
|
||||||
|
#include <linker/sections.h>
|
||||||
|
|
||||||
|
#include <linker/linker-defs.h>
|
||||||
|
#include <linker/linker-tool.h>
|
||||||
|
|
||||||
|
PROVIDE(__memctl_default = 0x00000000);
|
||||||
|
PROVIDE(_MemErrorHandler = 0x00000000);
|
||||||
|
|
||||||
|
#define RAMABLE_REGION sdram0 :sdram0_phdr
|
||||||
|
#define ROMABLE_REGION sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
vector_reset_text :
|
||||||
|
org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
|
||||||
|
len = MEM_RESET_TEXT_SIZE
|
||||||
|
vector_reset_lit :
|
||||||
|
org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
|
||||||
|
len = MEM_RESET_LIT_SIZE
|
||||||
|
vector_base_text :
|
||||||
|
org = XCHAL_VECBASE_RESET_PADDR_IRAM,
|
||||||
|
len = MEM_VECBASE_LIT_SIZE
|
||||||
|
vector_int2_lit :
|
||||||
|
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_int2_text :
|
||||||
|
org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
vector_int3_lit :
|
||||||
|
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_int3_text :
|
||||||
|
org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
vector_int4_lit :
|
||||||
|
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_int4_text :
|
||||||
|
org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
vector_int5_lit :
|
||||||
|
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_int5_text :
|
||||||
|
org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
vector_kernel_lit :
|
||||||
|
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_kernel_text :
|
||||||
|
org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
vector_user_lit :
|
||||||
|
org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_user_text :
|
||||||
|
org = XCHAL_USER_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
vector_double_lit :
|
||||||
|
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
|
||||||
|
len = MEM_VECT_LIT_SIZE
|
||||||
|
vector_double_text :
|
||||||
|
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
|
||||||
|
len = MEM_VECT_TEXT_SIZE
|
||||||
|
iram_text_start :
|
||||||
|
org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
|
||||||
|
len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
|
||||||
|
sdram0 :
|
||||||
|
org = SDRAM0_BASE,
|
||||||
|
len = SDRAM0_SIZE
|
||||||
|
sdram1 :
|
||||||
|
org = SDRAM1_BASE + SOF_MAILBOX_SIZE,
|
||||||
|
len = SDRAM1_SIZE - SOF_MAILBOX_SIZE
|
||||||
|
#ifdef CONFIG_GEN_ISR_TABLES
|
||||||
|
IDT_LIST :
|
||||||
|
org = IDT_BASE,
|
||||||
|
len = IDT_SIZE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static_uuid_entries_seg (!ari) :
|
||||||
|
org = UUID_ENTRY_ELF_BASE,
|
||||||
|
len = UUID_ENTRY_ELF_SIZE
|
||||||
|
static_log_entries_seg (!ari) :
|
||||||
|
org = LOG_ENTRY_ELF_BASE,
|
||||||
|
len = LOG_ENTRY_ELF_SIZE
|
||||||
|
fw_metadata_seg (!ari) :
|
||||||
|
org = EXT_MANIFEST_ELF_BASE,
|
||||||
|
len = EXT_MANIFEST_ELF_SIZE
|
||||||
|
}
|
||||||
|
|
||||||
|
PHDRS
|
||||||
|
{
|
||||||
|
vector_reset_text_phdr PT_LOAD;
|
||||||
|
vector_reset_lit_phdr PT_LOAD;
|
||||||
|
vector_base_text_phdr PT_LOAD;
|
||||||
|
vector_base_lit_phdr PT_LOAD;
|
||||||
|
vector_int2_text_phdr PT_LOAD;
|
||||||
|
vector_int2_lit_phdr PT_LOAD;
|
||||||
|
vector_int3_text_phdr PT_LOAD;
|
||||||
|
vector_int3_lit_phdr PT_LOAD;
|
||||||
|
vector_int4_text_phdr PT_LOAD;
|
||||||
|
vector_int4_lit_phdr PT_LOAD;
|
||||||
|
vector_int5_text_phdr PT_LOAD;
|
||||||
|
vector_int5_lit_phdr PT_LOAD;
|
||||||
|
vector_kernel_text_phdr PT_LOAD;
|
||||||
|
vector_kernel_lit_phdr PT_LOAD;
|
||||||
|
vector_user_text_phdr PT_LOAD;
|
||||||
|
vector_user_lit_phdr PT_LOAD;
|
||||||
|
vector_double_text_phdr PT_LOAD;
|
||||||
|
vector_double_lit_phdr PT_LOAD;
|
||||||
|
iram_text_start_phdr PT_LOAD;
|
||||||
|
sdram0_phdr PT_LOAD;
|
||||||
|
sdram1_phdr PT_LOAD;
|
||||||
|
static_uuid_entries_phdr PT_NOTE;
|
||||||
|
static_log_entries_phdr PT_NOTE;
|
||||||
|
metadata_entries_phdr PT_NOTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
_rom_store_table = 0;
|
||||||
|
|
||||||
|
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
|
||||||
|
|
||||||
|
ENTRY(CONFIG_KERNEL_ENTRY)
|
||||||
|
|
||||||
|
/* Various memory-map dependent cache attribute settings: */
|
||||||
|
_memmap_cacheattr_wb_base = 0x44024000;
|
||||||
|
_memmap_cacheattr_wt_base = 0x11021000;
|
||||||
|
_memmap_cacheattr_bp_base = 0x22022000;
|
||||||
|
_memmap_cacheattr_unused_mask = 0x00F00FFF;
|
||||||
|
_memmap_cacheattr_wb_trapnull = 0x4422422F;
|
||||||
|
_memmap_cacheattr_wba_trapnull = 0x4422422F;
|
||||||
|
_memmap_cacheattr_wbna_trapnull = 0x25222222;
|
||||||
|
_memmap_cacheattr_wt_trapnull = 0x1122122F;
|
||||||
|
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||||
|
_memmap_cacheattr_wb_strict = 0x44F24FFF;
|
||||||
|
_memmap_cacheattr_wt_strict = 0x11F21FFF;
|
||||||
|
_memmap_cacheattr_bp_strict = 0x22F22FFF;
|
||||||
|
_memmap_cacheattr_wb_allvalid = 0x44224222;
|
||||||
|
_memmap_cacheattr_wt_allvalid = 0x11221222;
|
||||||
|
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||||
|
/*
|
||||||
|
* Every 512M in 4GB space has dedicate cache attribute.
|
||||||
|
* 1: write through
|
||||||
|
* 2: cache bypass
|
||||||
|
* 4: write back
|
||||||
|
* F: invalid access
|
||||||
|
*/
|
||||||
|
_memmap_cacheattr_imx8_wt_allvalid = 0x22212222;
|
||||||
|
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid);
|
||||||
|
|
||||||
|
_EXT_MAN_ALIGN_ = 16;
|
||||||
|
EXTERN(ext_man_fw_ver)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
#include <linker/rel-sections.ld>
|
||||||
|
.ResetVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_ResetVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.ResetVector.text))
|
||||||
|
_ResetVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_reset_text :vector_reset_text_phdr
|
||||||
|
|
||||||
|
.ResetVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_ResetVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.ResetVector.literal)
|
||||||
|
_ResetVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_reset_lit :vector_reset_lit_phdr
|
||||||
|
|
||||||
|
.WindowVectors.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_WindowVectors_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.WindowVectors.text))
|
||||||
|
_WindowVectors_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_base_text :vector_base_text_phdr
|
||||||
|
|
||||||
|
.Level2InterruptVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.Level2InterruptVector.literal)
|
||||||
|
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int2_lit :vector_int2_lit_phdr
|
||||||
|
|
||||||
|
.Level2InterruptVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.Level2InterruptVector.text))
|
||||||
|
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int2_text :vector_int2_text_phdr
|
||||||
|
|
||||||
|
.Level3InterruptVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.Level3InterruptVector.literal)
|
||||||
|
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int3_lit :vector_int3_lit_phdr
|
||||||
|
|
||||||
|
.Level3InterruptVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.Level3InterruptVector.text))
|
||||||
|
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int3_text :vector_int3_text_phdr
|
||||||
|
|
||||||
|
.DebugExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.DebugExceptionVector.literal)
|
||||||
|
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int4_lit :vector_int4_lit_phdr
|
||||||
|
|
||||||
|
.DebugExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.DebugExceptionVector.text))
|
||||||
|
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int4_text :vector_int4_text_phdr
|
||||||
|
|
||||||
|
.NMIExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.NMIExceptionVector.literal)
|
||||||
|
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int5_lit :vector_int5_lit_phdr
|
||||||
|
|
||||||
|
.NMIExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.NMIExceptionVector.text))
|
||||||
|
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int5_text :vector_int5_text_phdr
|
||||||
|
|
||||||
|
.KernelExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.KernelExceptionVector.literal)
|
||||||
|
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||||
|
|
||||||
|
.KernelExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.KernelExceptionVector.text))
|
||||||
|
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_kernel_text :vector_kernel_text_phdr
|
||||||
|
|
||||||
|
.UserExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.UserExceptionVector.literal)
|
||||||
|
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_user_lit :vector_user_lit_phdr
|
||||||
|
|
||||||
|
.UserExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.UserExceptionVector.text))
|
||||||
|
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_user_text :vector_user_text_phdr
|
||||||
|
|
||||||
|
.DoubleExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.DoubleExceptionVector.literal)
|
||||||
|
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_double_lit :vector_double_lit_phdr
|
||||||
|
|
||||||
|
.DoubleExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.DoubleExceptionVector.text))
|
||||||
|
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_double_text :vector_double_text_phdr
|
||||||
|
|
||||||
|
.iram.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_stext = .;
|
||||||
|
_iram_text_start = ABSOLUTE(.);
|
||||||
|
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||||||
|
_iram_text_end = ABSOLUTE(.);
|
||||||
|
} >iram_text_start :iram_text_start_phdr
|
||||||
|
|
||||||
|
.rodata : ALIGN(4)
|
||||||
|
{
|
||||||
|
_rodata_start = ABSOLUTE(.);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
*(.gnu.linkonce.r.*)
|
||||||
|
*(.rodata1)
|
||||||
|
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||||
|
KEEP (*(.xt_except_table))
|
||||||
|
KEEP (*(.gcc_except_table .gcc_except_table.*))
|
||||||
|
*(.gnu.linkonce.e.*)
|
||||||
|
*(.gnu.version_r)
|
||||||
|
KEEP (*(.eh_frame))
|
||||||
|
KEEP (*crtbegin.o(.ctors))
|
||||||
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||||
|
KEEP (*(SORT(.ctors.*)))
|
||||||
|
KEEP (*(.ctors))
|
||||||
|
KEEP (*crtbegin.o(.dtors))
|
||||||
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||||
|
KEEP (*(SORT(.dtors.*)))
|
||||||
|
KEEP (*(.dtors))
|
||||||
|
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||||
|
*(.xt_except_desc)
|
||||||
|
*(.gnu.linkonce.h.*)
|
||||||
|
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||||
|
*(.xt_except_desc_end)
|
||||||
|
*(.dynamic)
|
||||||
|
*(.gnu.version_d)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_table_start = ABSOLUTE(.);
|
||||||
|
LONG(_bss_start)
|
||||||
|
LONG(_bss_end)
|
||||||
|
_bss_table_end = ABSOLUTE(.);
|
||||||
|
_rodata_end = ABSOLUTE(.);
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
.module_init : ALIGN(4)
|
||||||
|
{
|
||||||
|
_module_init_start = ABSOLUTE(.);
|
||||||
|
*(*.module_init)
|
||||||
|
_module_init_end = ABSOLUTE(.);
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_stext = .;
|
||||||
|
_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.ResetVector.text))
|
||||||
|
*(.ResetVector.literal)
|
||||||
|
*(.entry.text)
|
||||||
|
*(.init.literal)
|
||||||
|
KEEP(*(.init))
|
||||||
|
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||||
|
*(.fini.literal)
|
||||||
|
KEEP(*(.fini))
|
||||||
|
*(.gnu.version)
|
||||||
|
_text_end = ABSOLUTE(.);
|
||||||
|
_etext = .;
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
#include <linker/common-rom.ld>
|
||||||
|
|
||||||
|
.fw_ready : ALIGN(4)
|
||||||
|
{
|
||||||
|
KEEP(*(".fw_ready"));
|
||||||
|
KEEP (*(.fw_ready_metadata))
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
.noinit : ALIGN(4)
|
||||||
|
{
|
||||||
|
*(.noinit)
|
||||||
|
*(.noinit.*)
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
_data_start = ABSOLUTE(.);
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.gnu.linkonce.d.*)
|
||||||
|
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||||
|
*(.data1)
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata.*)
|
||||||
|
*(.gnu.linkonce.s.*)
|
||||||
|
*(.sdata2)
|
||||||
|
*(.sdata2.*)
|
||||||
|
*(.gnu.linkonce.s2.*)
|
||||||
|
KEEP(*(.jcr))
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.gna_model)
|
||||||
|
_data_end = ABSOLUTE(.);
|
||||||
|
. = ALIGN(4096);
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
.lit4 : ALIGN(4)
|
||||||
|
{
|
||||||
|
_lit4_start = ABSOLUTE(.);
|
||||||
|
*(*.lit4)
|
||||||
|
*(.lit4.*)
|
||||||
|
*(.gnu.linkonce.lit4.*)
|
||||||
|
_lit4_end = ABSOLUTE(.);
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
#include <linker/common-ram.ld>
|
||||||
|
|
||||||
|
.bss (NOLOAD) : ALIGN(8)
|
||||||
|
{
|
||||||
|
. = ALIGN (8);
|
||||||
|
_bss_start = ABSOLUTE(.);
|
||||||
|
*(.dynsbss)
|
||||||
|
*(.sbss)
|
||||||
|
*(.sbss.*)
|
||||||
|
*(.gnu.linkonce.sb.*)
|
||||||
|
*(.scommon)
|
||||||
|
*(.sbss2)
|
||||||
|
*(.sbss2.*)
|
||||||
|
*(.gnu.linkonce.sb2.*)
|
||||||
|
*(.dynbss)
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(.gnu.linkonce.b.*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN (8);
|
||||||
|
_bss_end = ABSOLUTE(.);
|
||||||
|
} >sdram0 :sdram0_phdr
|
||||||
|
|
||||||
|
.heap_mem (NOLOAD) : ALIGN(8)
|
||||||
|
{
|
||||||
|
. = ALIGN (8);
|
||||||
|
_heap_mem_start = ABSOLUTE(.);
|
||||||
|
*(*.heap_mem)
|
||||||
|
_heap_mem_end = ABSOLUTE(.);
|
||||||
|
} >sdram1 :sdram1_phdr
|
||||||
|
|
||||||
|
/* stack */
|
||||||
|
_end = ALIGN (8);
|
||||||
|
PROVIDE(end = ALIGN (8));
|
||||||
|
|
||||||
|
__stack = SDRAM1_BASE + SDRAM1_SIZE;
|
||||||
|
.comment 0 : { *(.comment) }
|
||||||
|
.debug 0 : { *(.debug) }
|
||||||
|
.line 0 : { *(.line) }
|
||||||
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||||
|
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||||
|
.debug_aranges 0 : { *(.debug_aranges) }
|
||||||
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||||
|
.debug_info 0 : { *(.debug_info) }
|
||||||
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||||
|
.debug_line 0 : { *(.debug_line) }
|
||||||
|
.debug_frame 0 : { *(.debug_frame) }
|
||||||
|
.debug_str 0 : { *(.debug_str) }
|
||||||
|
.debug_loc 0 : { *(.debug_loc) }
|
||||||
|
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||||
|
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||||
|
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||||
|
.debug_typenames 0 : { *(.debug_typenames) }
|
||||||
|
.debug_varnames 0 : { *(.debug_varnames) }
|
||||||
|
.debug_ranges 0 : { *(.debug_ranges) }
|
||||||
|
.xtensa.info 0 : { *(.xtensa.info) }
|
||||||
|
.xt.insn 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.insn))
|
||||||
|
KEEP (*(.gnu.linkonce.x.*))
|
||||||
|
}
|
||||||
|
.xt.prop 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.prop))
|
||||||
|
KEEP (*(.xt.prop.*))
|
||||||
|
KEEP (*(.gnu.linkonce.prop.*))
|
||||||
|
}
|
||||||
|
.xt.lit 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.lit))
|
||||||
|
KEEP (*(.xt.lit.*))
|
||||||
|
KEEP (*(.gnu.linkonce.p.*))
|
||||||
|
}
|
||||||
|
.xt.profile_range 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.profile_range))
|
||||||
|
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||||
|
}
|
||||||
|
.xt.profile_ranges 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.profile_ranges))
|
||||||
|
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||||
|
}
|
||||||
|
.xt.profile_files 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.profile_files))
|
||||||
|
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||||
|
}
|
||||||
|
#ifdef CONFIG_GEN_ISR_TABLES
|
||||||
|
#include <linker/intlist.ld>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.static_uuid_entries (COPY) : ALIGN(1024)
|
||||||
|
{
|
||||||
|
*(*.static_uuids)
|
||||||
|
} > static_uuid_entries_seg :static_uuid_entries_phdr
|
||||||
|
|
||||||
|
.static_log_entries (COPY) : ALIGN(1024)
|
||||||
|
{
|
||||||
|
*(*.static_log*)
|
||||||
|
} > static_log_entries_seg :static_log_entries_phdr
|
||||||
|
|
||||||
|
.fw_metadata (COPY) : ALIGN(1024)
|
||||||
|
{
|
||||||
|
KEEP (*(.fw_metadata))
|
||||||
|
. = ALIGN(_EXT_MAN_ALIGN_);
|
||||||
|
} >fw_metadata_seg :metadata_entries_phdr
|
||||||
|
}
|
||||||
Loading…
Add table
Add a link
Reference in a new issue