soc: xtensa: adsp: add support for NXP ADSP

Add a common part for all i.MX boards.

Add support for i.MX8, which represents i.MX8QM.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
448 KB OCRAM, 8MB SDRAM and 1 ESAI, 1 SAI as
audio interfaces.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>

soc/xtensa/nxp_adsp/common/CMakeLists.txt

@@ -0,0 +1,17 @@
+# NXP SoC family CMake file
+#
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_interface_library_named(NXP_ADSP_COMMON)
+
+zephyr_library_named(nxp_adsp_common)
+zephyr_library_include_directories(include)
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_library_sources(soc.c)
+
+zephyr_library_link_libraries(NXP_ADSP_COMMON)
+
+target_include_directories(NXP_ADSP_COMMON INTERFACE include)
+target_link_libraries(NXP_ADSP_COMMON INTERFACE nxp_adsp_common)

soc/xtensa/nxp_adsp/common/include/adsp/cache.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __COMMON_ADSP_CACHE_H__
+#define __COMMON_ADSP_CACHE_H__
+
+#include <xtensa/hal.h>
+
+/* Macros for data cache operations */
+#define SOC_DCACHE_FLUSH(addr, size)		\
+	z_xtensa_cache_flush((addr), (size))
+#define SOC_DCACHE_INVALIDATE(addr, size)	\
+	z_xtensa_cache_inv((addr), (size))
+
+#endif

soc/xtensa/nxp_adsp/common/include/adsp/io.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INCLUDE_IO__
+#define __INCLUDE_IO__
+
+#include <stdint.h>
+#include <soc/memory.h>
+#include <sys/sys_io.h>
+#include <arch/common/sys_io.h>
+
+static inline uint32_t io_reg_read(uint32_t reg)
+{
+	return sys_read32(reg);
+}
+
+static inline void io_reg_write(uint32_t reg, uint32_t val)
+{
+	sys_write32(val, reg);
+}
+
+static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
+				      uint32_t value)
+{
+	io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
+}
+
+static inline uint16_t io_reg_read16(uint32_t reg)
+{
+	return sys_read16(reg);
+}
+
+static inline void io_reg_write16(uint32_t reg, uint16_t val)
+{
+	sys_write16(val, reg);
+}
+
+#endif

soc/xtensa/nxp_adsp/common/include/soc.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <errno.h>
+
+#include <sys/sys_io.h>
+
+#include <adsp/cache.h>
+
+#ifndef __INC_IMX_SOC_H
+#define __INC_IMX_SOC_H
+
+/* Macros related to interrupt handling */
+#define XTENSA_IRQ_NUM_SHIFT			0
+#define XTENSA_IRQ_NUM_MASK			0xff
+
+/*
+ * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
+ *
+ * 1. Peripheral Register bit offset.
+ */
+#define XTENSA_IRQ_NUMBER(_irq) \
+	((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
+
+extern void z_soc_irq_enable(uint32_t irq);
+extern void z_soc_irq_disable(uint32_t irq);
+extern int z_soc_irq_is_enabled(unsigned int irq);
+
+#endif /* __INC_IMX_SOC_H */

soc/xtensa/nxp_adsp/common/soc.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <xtensa/xtruntime.h>
+#include <irq_nextlevel.h>
+#include <xtensa/hal.h>
+#include <init.h>
+
+#include "soc.h"
+
+#ifdef CONFIG_DYNAMIC_INTERRUPTS
+#include <sw_isr_table.h>
+#endif
+#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
+#include <logging/log.h>
+LOG_MODULE_REGISTER(soc);
+
+void z_soc_irq_enable(uint32_t irq)
+{
+	/*
+	 * enable core interrupt
+	 */
+	z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
+}
+
+void z_soc_irq_disable(uint32_t irq)
+{
+	/*
+	 * disable the interrupt in interrupt controller
+	 */
+	z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+}
+
+int z_soc_irq_is_enabled(unsigned int irq)
+{
+	int ret = 0;
+
+	/* regular interrupt */
+	ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
+
+	return ret;
+}