ITE: drivers/i2c/target: Remove hardware reset setting
In the interrupt pending routine, only the interrupt status needs to be cleared at the end of the interrupt routine. There is no need to do a hardware reset(HALT) to avoid clearing the next transfer interrupt when the current transfer is completed. Test: Testing this function does not cause I2C data/clk to get stuck on the system platform. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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2 changed files with 0 additions and 6 deletions
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@ -1433,8 +1433,6 @@ enum chip_pll_mode {
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#define IT8XXX2_I2C_IDR_CLR BIT(2)
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#define IT8XXX2_I2C_SLVDATAFLG BIT(1)
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#define IT8XXX2_I2C_P_CLR BIT(0)
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#define IT8XXX2_I2C_INT_ANY (IT8XXX2_I2C_CNT_HOLD | IT8XXX2_I2C_IDW_CLR | \
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IT8XXX2_I2C_IDR_CLR | IT8XXX2_I2C_SLVDATAFLG)
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/* 0x13: Nack Status */
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#define IT8XXX2_I2C_NST_CNS BIT(7)
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#define IT8XXX2_I2C_NST_ID_NACK BIT(3)
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