aarch64: Rewrite reset code using C
There is no strict reason to use assembly for the reset routine. Move as much code as possible to C code using the proper helpers. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
Anas Nashif
parent
bba7abe975
commit
9d908c78fa
10 changed files with 346 additions and 203 deletions
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@ -14,6 +14,7 @@ zephyr_library_sources(
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irq_manage.c
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prep_c.c
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reset.S
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reset.c
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switch.S
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thread.c
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vector_table.S
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@ -4,12 +4,6 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Reset handler
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*
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* Reset handler that prepares the system for running C code.
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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@ -19,14 +13,74 @@
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_ASM_FILE_PROLOGUE
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/*
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* Platform may do platform specific init at EL3.
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* The function implementation must preserve callee saved registers as per
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* AArch64 ABI PCS.
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* Platform specific pre-C init code
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*
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* Note: - Stack is not yet available
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* - x23 must be preserved
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*/
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WTEXT(z_arch_el3_plat_init)
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SECTION_FUNC(TEXT,z_arch_el3_plat_init)
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ret
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WTEXT(z_arm64_el3_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el3_plat_prep_c)
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ret
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WTEXT(z_arm64_el2_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el2_plat_prep_c)
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ret
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WTEXT(z_arm64_el1_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el1_plat_prep_c)
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ret
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/*
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* Set the minimum necessary to safely call C code
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*/
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GTEXT(__reset_prep_c)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c)
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/* return address: x23 */
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mov x23, x30
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switch_el x0, 3f, 2f, 1f
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3:
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/* Reinitialize SCTLR from scratch in EL3 */
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ldr w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)
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msr sctlr_el3, x0
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/* Custom plat prep_c init */
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bl z_arm64_el3_plat_prep_c
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b out
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2:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el2
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bic x0, x0, SCTLR_A_BIT
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msr sctlr_el2, x0
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/* Custom plat prep_c init */
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bl z_arm64_el2_plat_prep_c
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b out
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1:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el1
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bic x0, x0, SCTLR_A_BIT
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msr sctlr_el1, x0
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/* Custom plat prep_c init */
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bl z_arm64_el1_plat_prep_c
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out:
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isb
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/* Select SP_EL0 */
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msr SPSel, #0
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/* Initialize stack */
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ldr x0, =(z_interrupt_stacks)
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add x0, x0, #(CONFIG_ISR_STACK_SIZE)
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mov sp, x0
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ret x23
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/*
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* Reset vector
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@ -34,9 +88,6 @@ ret
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* Ran when the system comes out of reset. The processor is in thread mode with
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* privileged level. At this point, neither SP_EL0 nor SP_ELx point to a valid
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* area in SRAM.
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*
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* When these steps are completed, jump to z_arm64_prep_c(), which will finish
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* setting up the system for running C code.
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*/
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GTEXT(__reset)
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@ -44,103 +95,44 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
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GTEXT(__start)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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/* Mask all exceptions */
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msr DAIFSet, #0xf
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/* Setup vector table */
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adr x19, _vector_table
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/* Prepare for calling C code */
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bl __reset_prep_c
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switch_el x1, 3f, 2f, 1f
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/* Platform hook for highest EL */
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bl z_arm64_el_highest_init
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switch_el:
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switch_el x0, 3f, 2f, 1f
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3:
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/*
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* Zephyr entry happened in EL3. Do EL3 specific init before
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* dropping to lower EL.
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*/
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/* EL3 init */
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bl z_arm64_el3_init
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/* Initialize VBAR */
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msr vbar_el3, x19
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isb
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/* Switch to SP_EL0 and setup the stack */
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msr spsel, #0
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ldr x0, =(z_interrupt_stacks)
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add x0, x0, #(CONFIG_ISR_STACK_SIZE)
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mov sp, x0
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/* Initialize SCTLR_EL3 to reset value */
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mov_imm x1, SCTLR_EL3_RES1
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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/*
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* Disable access traps to EL3 for CPACR, Trace, FP, ASIMD,
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* SVE from lower EL.
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*/
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mov_imm x0, CPTR_EL3_RES0
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mov_imm x1, (CPTR_EL3_TTA_BIT | CPTR_EL3_TFP_BIT | CPTR_EL3_TCPAC_BIT)
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bic x0, x0, x1
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orr x0, x0, #(CPTR_EL3_EZ_BIT)
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msr cptr_el3, x0
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isb
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/* Platform specific configurations needed in EL3 */
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bl z_arch_el3_plat_init
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/* Enable access control configuration from lower EL */
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mrs x0, actlr_el3
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orr x0, x0, #(ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_L2ECTLR_BIT \
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| ACTLR_EL3_L2CTLR_BIT)
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orr x0, x0, #(ACTLR_EL3_CPUACTLR_BIT | ACTLR_EL3_CPUECTLR_BIT)
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msr actlr_el3, x0
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/* Initialize SCTLR_EL1 to reset value */
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mov_imm x0, SCTLR_EL1_RES1
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msr sctlr_el1, x0
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/* Disable EA/IRQ/FIQ routing to EL3 and set EL1 to AArch64 */
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mov x0, xzr
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orr x0, x0, #(SCR_RW_BIT)
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msr scr_el3, x0
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/* On eret return to secure EL1h with DAIF masked */
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mov_imm x0, (SPSR_DAIF_MASK | SPSR_MODE_EL1H)
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msr spsr_el3, x0
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adr x0, 1f
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msr elr_el3, x0
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/* Get next EL */
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adr x0, switch_el
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bl z_arm64_el3_get_next_el
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eret
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2:
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/* Booting from EL2 is not supported */
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b .
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/* EL2 init */
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bl z_arm64_el2_init
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/* Move to EL1 with all exceptions masked */
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mov_imm x0, (SPSR_DAIF_MASK | SPSR_MODE_EL1T)
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msr spsr_el2, x0
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adr x0, 1f
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msr elr_el2, x0
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eret
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1:
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/* Initialize VBAR */
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msr vbar_el1, x19
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/* EL1 init */
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bl z_arm64_el1_init
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/* Enable SError interrupts */
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msr DAIFClr, #(DAIFCLR_ABT_BIT)
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isb
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/* Switch to SP_EL0 and setup the stack */
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msr spsel, #0
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ldr x0, =(z_interrupt_stacks)
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add x0, x0, #(CONFIG_ISR_STACK_SIZE)
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mov sp, x0
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/* Disable access trapping in EL1 for NEON/FP */
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mov_imm x0, CPACR_EL1_FPEN_NOTRAP
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msr cpacr_el1, x0
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/* Enable the instruction cache and EL1 stack alignment check. */
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mov_imm x1, (SCTLR_I_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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msr sctlr_el1, x0
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0:
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isb
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/* Enable the SError interrupt */
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msr daifclr, #(DAIFCLR_ABT_BIT)
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bl z_arm64_prep_c
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b z_arm64_prep_c
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146
arch/arm/core/aarch64/reset.c
Normal file
146
arch/arm/core/aarch64/reset.c
Normal file
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@ -0,0 +1,146 @@
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/*
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* Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel_internal.h>
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#include "vector_table.h"
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void __weak z_arm64_el_highest_plat_init(void)
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{
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/* do nothing */
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}
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void __weak z_arm64_el3_plat_init(void)
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{
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/* do nothing */
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}
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void __weak z_arm64_el2_plat_init(void)
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{
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/* do nothing */
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}
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void __weak z_arm64_el1_plat_init(void)
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{
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/* do nothing */
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}
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void z_arm64_el_highest_init(void)
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{
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write_cntfrq_el0(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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z_arm64_el_highest_plat_init();
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isb();
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}
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void z_arm64_el3_init(void)
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{
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uint64_t reg;
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/* Setup vector table */
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write_vbar_el3((uint64_t)_vector_table);
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isb();
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reg = 0U; /* Mostly RES0 */
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reg &= ~(CPTR_TTA_BIT | /* Do not trap sysreg accesses */
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CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
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CPTR_TCPAC_BIT); /* Do not trap CPTR_EL2 / CPACR_EL1 accesses */
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write_cptr_el3(reg);
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reg = 0U; /* Reset */
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#ifdef CONFIG_ARMV8_A_NS
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reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */
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#endif
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reg |= (SCR_RES1 | /* RES1 */
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SCR_RW_BIT | /* EL2 execution state is AArch64 */
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SCR_ST_BIT | /* Do not trap EL1 accesses to timer */
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SCR_HCE_BIT | /* Do not trap HVC */
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SCR_SMD_BIT); /* Do not trap SMC */
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write_scr_el3(reg);
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z_arm64_el3_plat_init();
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isb();
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}
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void z_arm64_el2_init(void)
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{
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uint64_t reg;
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reg = read_sctlr_el2();
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reg |= (SCTLR_EL2_RES1 | /* RES1 */
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SCTLR_I_BIT | /* Enable i-cache */
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SCTLR_SA_BIT); /* Enable SP alignment check */
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write_sctlr_el2(reg);
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reg = read_hcr_el2();
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reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */
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write_hcr_el2(reg);
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reg = 0U; /* RES0 */
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reg |= CPTR_EL2_RES1; /* RES1 */
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reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
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CPTR_TCPAC_BIT); /* Do not trap CPACR_EL1 accesses */
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write_cptr_el2(reg);
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zero_cntvoff_el2(); /* Set 64-bit virtual timer offset to 0 */
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zero_cnthctl_el2();
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zero_cnthp_ctl_el2();
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z_arm64_el2_plat_init();
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isb();
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}
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void z_arm64_el1_init(void)
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{
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uint64_t reg;
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/* Setup vector table */
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write_vbar_el1((uint64_t)_vector_table);
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isb();
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reg = 0U; /* RES0 */
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reg |= CPACR_EL1_FPEN_NOTRAP; /* Do not trap NEON/SIMD/FP */
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/* TODO: CONFIG_FLOAT_*_FORBIDDEN */
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write_cpacr_el1(reg);
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reg = read_sctlr_el1();
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reg |= (SCTLR_EL1_RES1 | /* RES1 */
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SCTLR_I_BIT | /* Enable i-cache */
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SCTLR_SA_BIT); /* Enable SP alignment check */
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write_sctlr_el1(reg);
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z_arm64_el1_plat_init();
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isb();
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}
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void z_arm64_el3_get_next_el(uint64_t switch_addr)
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{
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uint64_t spsr;
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write_elr_el3(switch_addr);
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/* Mask the DAIF */
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spsr = SPSR_DAIF_MASK;
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/*
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* Is considered an illegal return "[..] a return to EL2 when EL3 is
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* implemented and the value of the SCR_EL3.NS bit is 0 if
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* ARMv8.4-SecEL2 is not implemented" (D1.11.2 from ARM DDI 0487E.a)
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*/
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if (is_el_implemented(2) &&
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((is_in_secure_state() && is_el2_sec_supported()) || !is_in_secure_state())) {
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/* Dropping into EL2 */
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spsr |= SPSR_MODE_EL2T;
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} else {
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/* Dropping into EL1 */
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spsr |= SPSR_MODE_EL1T;
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}
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write_spsr_el3(spsr);
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}
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@ -136,6 +136,31 @@ static ALWAYS_INLINE void disable_fiq(void)
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#define __DMB() dmb()
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#define __DSB() dsb()
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static inline bool is_el_implemented(unsigned int el)
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{
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unsigned int shift;
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if (el > 3) {
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return false;
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}
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shift = ID_AA64PFR0_EL1_SHIFT * el;
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return (((read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK) != 0U);
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}
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static inline bool is_el2_sec_supported(void)
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{
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return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) &
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ID_AA64PFR0_SEL2_MASK) != 0U);
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}
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static inline bool is_in_secure_state(void)
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{
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/* We cannot read SCR_EL3 from EL2 or EL1 */
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return !IS_ENABLED(CONFIG_ARMV8_A_NS);
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}
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#endif /* !_ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_LIB_HELPERS_H_ */
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@ -4,6 +4,6 @@ zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_SOC_BCM58402_A72 plat_core.S)
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zephyr_sources_ifdef(CONFIG_SOC_BCM58402_A72 plat_core.c)
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zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
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@ -1,65 +0,0 @@
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/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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*@file
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*@brief plat/core specific init
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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GTEXT(z_arch_el3_plat_init)
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GTEXT(plat_l2_init)
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SECTION_FUNC(TEXT, z_arch_el3_plat_init)
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mov x20, x30
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/* Enable GIC v3 system interface */
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mov_imm x0, (ICC_SRE_ELx_DFB_BIT | ICC_SRE_ELx_DIB_BIT | \
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ICC_SRE_ELx_SRE_BIT | ICC_SRE_EL3_EN_BIT)
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msr ICC_SRE_EL3, x0
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/* L2 config */
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bl plat_l2_init
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mov x30, x20
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ret
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SECTION_FUNC(TEXT,plat_l2_init)
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/*
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* Set L2 Auxiliary Control Register of Cortex-A72
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*/
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/* Disable cluster coherency */
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mrs x0, CORTEX_A72_L2ACTLR_EL1
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orr x0, x0, #CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT
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msr CORTEX_A72_L2ACTLR_EL1, x0
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|
||||
/* Set L2 Control Register */
|
||||
mov_imm x1, ((CORTEX_A72_L2_DATA_RAM_LATENCY_MASK << \
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(CORTEX_A72_L2_TAG_RAM_LATENCY_MASK << \
|
||||
CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT) | \
|
||||
(CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE << \
|
||||
CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | \
|
||||
(CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE << \
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT))
|
||||
bic x0, x0, x1
|
||||
mov_imm x1, ((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE << \
|
||||
CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) | \
|
||||
(CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE << \
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT))
|
||||
orr x0, x0, x1
|
||||
msr CORTEX_A72_L2CTLR_EL1, x0
|
||||
|
||||
dsb sy
|
||||
isb
|
||||
ret
|
||||
57
soc/arm/bcm_vk/viper/plat_core.c
Normal file
57
soc/arm/bcm_vk/viper/plat_core.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright 2020 Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <toolchain.h>
|
||||
#include <linker/sections.h>
|
||||
#include <arch/cpu.h>
|
||||
|
||||
void z_arm64_el3_plat_init(void)
|
||||
{
|
||||
uint64_t reg, val;
|
||||
|
||||
/* Enable access control configuration from lower EL */
|
||||
reg = read_actlr_el3();
|
||||
reg |= (ACTLR_EL3_L2ACTLR_BIT |
|
||||
ACTLR_EL3_L2ECTLR_BIT |
|
||||
ACTLR_EL3_L2CTLR_BIT |
|
||||
ACTLR_EL3_CPUACTLR_BIT |
|
||||
ACTLR_EL3_CPUECTLR_BIT);
|
||||
write_actlr_el3(reg);
|
||||
|
||||
reg = (ICC_SRE_ELx_DFB_BIT | ICC_SRE_ELx_DIB_BIT |
|
||||
ICC_SRE_ELx_SRE_BIT | ICC_SRE_EL3_EN_BIT);
|
||||
|
||||
write_sysreg(reg, ICC_SRE_EL3);
|
||||
|
||||
reg = read_sysreg(CORTEX_A72_L2ACTLR_EL1);
|
||||
reg |= CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT;
|
||||
write_sysreg(reg, CORTEX_A72_L2ACTLR_EL1);
|
||||
|
||||
val = ((CORTEX_A72_L2_DATA_RAM_LATENCY_MASK <<
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) |
|
||||
(CORTEX_A72_L2_TAG_RAM_LATENCY_MASK <<
|
||||
CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT) |
|
||||
(CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE <<
|
||||
CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) |
|
||||
(CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE <<
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT));
|
||||
|
||||
reg &= ~val;
|
||||
|
||||
val = ((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES <<
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) |
|
||||
(CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE <<
|
||||
CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT) |
|
||||
(CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE <<
|
||||
CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT));
|
||||
|
||||
reg |= val;
|
||||
|
||||
write_sysreg(reg, CORTEX_A72_L2CTLR_EL1);
|
||||
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
|
@ -3,4 +3,4 @@
|
|||
|
||||
zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_SOC_QEMU_CORTEX_A53 plat_core.S)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_QEMU_CORTEX_A53 plat_core.c)
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* Copyright 2020 Carlo Caione <ccaione@baylibre.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
*@file
|
||||
*@brief plat/core specific init
|
||||
*/
|
||||
|
||||
#include <toolchain.h>
|
||||
#include <linker/sections.h>
|
||||
#include <arch/cpu.h>
|
||||
|
||||
_ASM_FILE_PROLOGUE
|
||||
|
||||
GTEXT(z_arch_el3_plat_init)
|
||||
|
||||
SECTION_FUNC(TEXT, z_arch_el3_plat_init)
|
||||
|
||||
mov x20, x30
|
||||
|
||||
#ifdef CONFIG_GIC_V3
|
||||
/* Enable GIC v3 system interface */
|
||||
mov_imm x0, (ICC_SRE_ELx_DFB_BIT | ICC_SRE_ELx_DIB_BIT | \
|
||||
ICC_SRE_ELx_SRE_BIT | ICC_SRE_EL3_EN_BIT)
|
||||
msr ICC_SRE_EL3, x0
|
||||
#endif
|
||||
|
||||
mov x30, x20
|
||||
ret
|
||||
19
soc/arm/qemu_cortex_a53/plat_core.c
Normal file
19
soc/arm/qemu_cortex_a53/plat_core.c
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright 2020 Carlo Caione <ccaione@baylibre.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <toolchain.h>
|
||||
#include <linker/sections.h>
|
||||
#include <arch/cpu.h>
|
||||
|
||||
void z_arm64_el3_plat_init(void)
|
||||
{
|
||||
uint64_t reg = 0;
|
||||
|
||||
reg = (ICC_SRE_ELx_DFB_BIT | ICC_SRE_ELx_DIB_BIT |
|
||||
ICC_SRE_ELx_SRE_BIT | ICC_SRE_EL3_EN_BIT);
|
||||
|
||||
write_sysreg(reg, ICC_SRE_EL3);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue