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soc: intel_adsp: Remove old support for cAVS 2.5 "alternate boot"

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The linker script (and a little bit of SOF) still has support for an
older mechanism for bootstrapping secondary cores by copying code into
lp-sram from a "manifest" emitted by the linker.  This actually never
worked in Zephyr, and we've implemented a different scheme that uses a
small runtime-copied trampoline instead.

Remove.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-09-04 17:32:11 -07:00 • committed by Anas Nashif
commit 9d7da4cdec
2 changed files with 9 additions and 68 deletions
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68
soc/xtensa/intel_adsp/cavs_v25/linker.ld
View file

@ -145,19 +145,6 @@ MEMORY
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
lpsram_alt_reset_vec_seg :
org = LP_SRAM_ALT_RESET_VEC_BASE,
len = LP_SRAM_ALT_RESET_VEC_SIZE
lpsram_alt_reset_int_vec_seg :
org = LP_SRAM_ALT_RESET_INT_VEC_BASE,
len = LP_SRAM_ALT_RESET_INT_VEC_SIZE
lpsram_code_seg :
org = LP_SRAM_CODE_BASE,
len = LP_SRAM_CODE_SIZE
lpsram_mem :
org = LP_SRAM_START,
len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)
}
PHDRS
@ -190,18 +177,11 @@ PHDRS
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
lpsram_mem_phdr PT_LOAD;
sram_alt_fw_reset_vec_phdr PT_LOAD;
sram_alt_fw_reset_vec_int_phdr PT_LOAD;
lpsram_code_phdr PT_LOAD;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
ENTRY(CONFIG_KERNEL_ENTRY)
EXTERN(_LpsramHeader)
EXTERN(_AltResetVector)
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
@ -400,30 +380,6 @@ SECTIONS
. = ALIGN(4096);
} >ram :ram_phdr
.AlternateResetVector.text : ALIGN(64)
{
_alternate_reset_vector_start = ABSOLUTE(.);
KEEP (*(*.AlternateResetVector.text))
. = ALIGN(16);
_alternate_reset_vector_start_end = ABSOLUTE(.);
} >lpsram_alt_reset_vec_seg AT> ram : sram_alt_fw_reset_vec_phdr
.AlternateResetL2IntVector.text : ALIGN(16)
{
_alternate_reset_l2_int_vector_start = ABSOLUTE(.);
KEEP (*(*.AlternateResetL2IntVector.text))
. = ALIGN(16);
_alternate_reset_l2_int_vector_end = ABSOLUTE(.);
} >lpsram_alt_reset_int_vec_seg AT> ram : sram_alt_fw_reset_vec_int_phdr
.LpsramCode.text : ALIGN(16)
{
_lpsram_code_start = ABSOLUTE(.);
KEEP (*(*.LpsramCode.text))
. = ALIGN(16);
_lpsram_code_end = ABSOLUTE(.);
} >lpsram_code_seg AT> ram : lpsram_code_phdr
.rodata : ALIGN(4096)
{
_rodata_start = ABSOLUTE(.);
@ -528,30 +484,6 @@ SECTIONS
#include <linker/common-ram.ld>
.AltBootManifest SEGSTART_CACHED : ALIGN(8)
{
/* Single entry of strorage manifest
* consist of 3 items. Entries array
* is preceded by a single dword with
* entries count. */
_loader_storage_manifest_start = ABSOLUTE(.);
/* Number of entries*/
LONG(3);
/* Entry 1 */
LONG(LOADADDR(.AlternateResetVector.text));
LONG(ADDR(.AlternateResetVector.text));
LONG(SIZEOF(.AlternateResetVector.text));
/* Entry 2 */
LONG(LOADADDR(.AlternateResetL2IntVector.text));
LONG(ADDR(.AlternateResetL2IntVector.text));
LONG(SIZEOF(.AlternateResetL2IntVector.text));
/* Entry 3 */
LONG(LOADADDR(.LpsramCode.text));
LONG(ADDR(.LpsramCode.text));
LONG(SIZEOF(.LpsramCode.text));
_loader_storage_manifest_end = ABSOLUTE(.);
} >ram :ram_phdr
.tm_clone_table :
{
*(.tm_clone_table)

9
soc/xtensa/intel_adsp/common/soc_mp.c
View file

@ -67,6 +67,15 @@ static struct k_spinlock mplock;
char *z_mp_stack_top;
/* Vestigial silliness: An old mechanism for core startup would embed
* a "manifest" of code to copy to LP-SRAM at startup (vs. the tiny
* trampoline we use here). This was constructed in the linker
* script, and the first word would encode the number of entries. As
* it happens, SOF still emits the code to copy this data, so it needs
* to see this symbol point to a zero.
*/
uint32_t _loader_storage_manifest_start;
/* Simple array of CPUs that are active and available for an IPI. The
* IDC interrupt is ALSO used to bring a CPU out of reset, so we need
* to be absolutely sure we don't try to IPI a CPU that isn't ready to