From 9cf6d660626fa2c1724caa7ed6052a63530b82cf Mon Sep 17 00:00:00 2001 From: Alvis Sun Date: Fri, 16 May 2025 09:31:23 +0800 Subject: [PATCH] soc: npcx: npcx9: disable CCDEV_SEL in early initialization. Enabling CCDEV_SEL_EN may interfere with the expected behavior of VCC1_RST#. To prevent potential issues, this commit sets CCDEV_SEL_EN to be disabled by default, ensuring reliable VCC1_RST# behavior. Signed-off-by: Alvis Sun Signed-off-by: Mulin Chao --- soc/nuvoton/npcx/common/npcxn/include/reg_def.h | 7 +++++++ soc/nuvoton/npcx/npcx9/soc.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/soc/nuvoton/npcx/common/npcxn/include/reg_def.h b/soc/nuvoton/npcx/common/npcxn/include/reg_def.h index ee0fadc72da..0505a337af3 100644 --- a/soc/nuvoton/npcx/common/npcxn/include/reg_def.h +++ b/soc/nuvoton/npcx/common/npcxn/include/reg_def.h @@ -198,6 +198,13 @@ struct scfg_reg { #define NPCX_JEN_CTL1_JEN_ENABLE 0x9 #define NPCX_JEN_CTL1_JEN_DISABLE 0x6 +#define NPCX_JEN_CTL2_OFFSET 0x121 +#define NPCX_JEN_CTL2(base) (*(volatile uint8_t *)(base + (NPCX_JEN_CTL2_OFFSET))) + +#define NPCX_JEN_CTL2_CCDEV_SEL_EN FIELD(0, 4) +#define NPCX_JEN_CTL2_CCDEV_SEL_ENABLE 0x9 +#define NPCX_JEN_CTL2_CCDEV_SEL_DISABLE 0x6 + /* SCFG register fields */ #define NPCX_DEVCNT_F_SPI_TRIS 6 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) diff --git a/soc/nuvoton/npcx/npcx9/soc.c b/soc/nuvoton/npcx/npcx9/soc.c index 99144ce904c..60a13aa4390 100644 --- a/soc/nuvoton/npcx/npcx9/soc.c +++ b/soc/nuvoton/npcx/npcx9/soc.c @@ -20,6 +20,9 @@ void soc_early_init_hook(void) SET_FIELD(NPCX_JEN_CTL1(scfg_base), NPCX_JEN_CTL1_JEN_HEN, NPCX_JEN_CTL1_JEN_DISABLE); + + SET_FIELD(NPCX_JEN_CTL2(scfg_base), NPCX_JEN_CTL2_CCDEV_SEL_EN, + NPCX_JEN_CTL2_CCDEV_SEL_DISABLE); } scfg_init(); }