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dts: arm: silabs: Move efr32bg22 to xg22 directory

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Introduce subdirectory for xg22 socs.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit is contained in:
Aksel Skauge Mellbye 2025-05-14 14:49:08 +02:00 • committed by Benjamin Cabé
commit 9cea156611
6 changed files with 483 additions and 147 deletions
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2
boards/silabs/dev_kits/sltb010a/sltb010a.dts
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@ -5,7 +5,7 @@
*/
/dts-v1/;
#include <silabs/efr32bg22.dtsi>
#include <silabs/xg22/efr32bg22c224f512im40.dtsi>
#include "sltb010a-pinctrl.dtsi"
#include "thunderboard.dtsi"
#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>

146
dts/arm/silabs/efr32bg22.dtsi
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@ -1,146 +0,0 @@
/*
* Copyright (c) 2021 Sateesh Kotapati
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "efr32bg2x.dtsi"
#include <dt-bindings/clock/silabs/xg22-clock.h>
#include <dt-bindings/dma/silabs/xg22-dma.h>
#include <mem.h>
/ {
clocks {
euart0clk: euart0clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&em01grpaclk>;
};
};
soc {
clkin0: clkin0@5003c454 {
#clock-cells = <0>;
compatible = "fixed-clock";
reg = <0x5003c454 0x4>;
clock-frequency = <DT_FREQ_M(38)>;
};
};
};
&cmu {
interrupts = <46 2>;
};
&hfxo {
interrupts = <44 0>;
interrupt-names = "hfxo";
};
&msc {
flash0: flash@0 {
compatible = "soc-nv-flash";
write-block-size = <4>;
erase-block-size = <8192>;
reg = <0x0 DT_SIZE_K(512)>;
};
};
&sram0 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
&gpio {
interrupts = <25 2>, <26 2>;
interrupt-names = "gpio_odd", "gpio_even";
clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
gpioa: gpio@5003c000 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C000 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@5003c030 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C030 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@5003c060 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C060 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@5003c090 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C090 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
&dma0 {
interrupts = <21 0>;
};
&i2c0 {
interrupts = <27 2>;
clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
};
&i2c1 {
interrupts = <28 2>;
clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
};
&usart0 {
interrupts = <13 2>, <14 2>;
clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
};
&usart1 {
interrupts = <15 2>, <16 2>;
clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
};
&burtc0 {
interrupts = <18 2>;
clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
};
&rtcc0 {
interrupts = <12 2>;
interrupt-names = "rtcc";
clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
};
&dcdc {
interrupts = <61 2>;
};
&adc0 {
interrupts = <48 2>;
clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
};
&wdog0 {
interrupts = <43 2>;
clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
};
&radio {
interrupts = <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>,
<37 1>, <38 1>, <39 1>, <40 1>, <41 1>, <42 1>;
interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
"rac_rsm", "rac_seq", "rdmailbox", "rfsense", "prortc",
"synth";
};

14
dts/arm/silabs/xg22/efr32bg22.dtsi Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <silabs/xg22/efr32xg22.dtsi>
&radio {
bt_hci_silabs: bt_hci_silabs {
compatible = "silabs,bt-hci-efr32";
status = "disabled";
};
};

25
dts/arm/silabs/xg22/efr32bg22c224f512im40.dtsi Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2021 Sateesh Kotapati
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <silabs/xg22/efr32bg22.dtsi>
#include <mem.h>
/ {
soc {
compatible = "silabs,efr32bg22c224f512im40", "silabs,efr32bg22", "silabs,xg22",
"silabs,efr32", "simple-bus";
model = "Silicon Labs EFR32BG22C224F512IM40 SoC";
};
};
&flash0 {
reg = <0x0 DT_SIZE_K(512)>;
};
&sram0 {
reg = <0x20000000 DT_SIZE_K(32)>;
};

26
dts/arm/silabs/xg22/efr32xg22.dtsi Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <silabs/xg22/xg22.dtsi>
/ {
soc {
radio: radio@b0000000 {
compatible = "silabs,series2-radio";
reg = <0xb0000000 0x1000000>;
interrupts = <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>,
<37 1>, <38 1>, <39 1>, <40 1>, <41 1>, <42 1>;
interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
"rac_rsm", "rac_seq", "rdmailbox", "rfsense", "prortc",
"synth";
pa-initial-power-dbm = <10>;
pa-ramp-time-us = <2>;
pa-voltage-mv = <3300>;
pa-2p4ghz = "highest";
};
};
};

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dts/arm/silabs/xg22/xg22.dtsi Normal file
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@ -0,0 +1,417 @@
/*
* Copyright (c) 2021 Sateesh Kotapati
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <dt-bindings/clock/silabs/xg22-clock.h>
#include <dt-bindings/dma/silabs/xg22-dma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/adc/adc.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &msc;
zephyr,entropy = &trng;
};
clocks {
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hfrcodpll>;
};
hclk: hclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sysclk>;
/* Divisors 1, 2, 4, 8, 16 allowed */
clock-div = <1>;
};
pclk: pclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hclk>;
/* Divisors 1, 2 allowed */
clock-div = <2>;
};
lspclk: lspclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&pclk>;
/* Fixed divisor of 2 */
clock-div = <2>;
};
hclkdiv1024: hclkdiv1024 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hclk>;
/* Fixed divisor of 1024 */
clock-div = <1024>;
};
traceclk: traceclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sysclk>;
/* Divisors 1, 2, 3, 4 allowed */
clock-div = <1>;
};
em01grpaclk: em01grpaclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hfrcodpll>;
};
em01grpbclk: em01grpbclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hfrcodpll>;
};
iadcclk: iadcclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&em01grpaclk>;
};
em23grpaclk: em23grpaclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&lfrco>;
};
em4grpaclk: em4grpaclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&lfrco>;
};
rtccclk: rtccclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&lfrco>;
};
wdog0clk: wdog0clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&lfrco>;
};
systickclk: systickclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hclk>;
};
euart0clk: euart0clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&em01grpaclk>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33";
reg = <0>;
/*
* EM1 is enabled by default because it is
* unconditionally safe.
*
* EM2/3 can be enabled by the board code if proper
* timing configuration is ensured:
* - for EM2, EM3: BURTC used as sys_clock
* - for EM3: BURTC clocked from ULFRCO
* Using BURTC as sys_clock instead of SysTick
* has implications on system performance. Read
* KConfig documentation entry before enabling it.
*
* The minimum residency and exit latency is
* managed by sl_power_manager on S2 devices.
*/
cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv8m-itm";
reg = <0xe0000000 0x1000>;
};
};
power-states {
/*
* EM1 is a basic "CPU WFI idle", all high-freq clocks remain
* enabled.
*/
pstate_em1: em1 {
compatible = "zephyr,power-state";
power-state-name = "runtime-idle";
/* HFXO remains active */
};
/*
* EM2 is a deepsleep with HF clocks disabled by HW, voltages
* scaled down, etc.
*/
pstate_em2: em2 {
compatible = "zephyr,power-state";
power-state-name = "suspend-to-idle";
};
/*
* EM3 seems to be exactly the same as EM2 except that
* LFXO & LFRCO should be disabled, so you must use ULFRCO
* as BURTC clock for the system to not lose track of time and
* wake up.
*/
pstate_em3: em3 {
compatible = "zephyr,power-state";
power-state-name = "standby";
};
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
soc {
cmu: clock@50008000 {
compatible = "silabs,series-clock";
reg = <0x50008000 0x4000>;
interrupts = <46 2>;
interrupt-names = "cmu";
status = "okay";
#clock-cells = <2>;
};
fsrco: fsrco@50018000 {
#clock-cells = <0>;
compatible = "fixed-clock";
reg = <0x50018000 0x4000>;
clock-frequency = <DT_FREQ_M(20)>;
};
clk_hfxo: hfxo: hfxo@5000c000 {
#clock-cells = <0>;
compatible = "silabs,hfxo";
reg = <0x5000c000 0x4000>;
clock-frequency = <DT_FREQ_K(38400)>;
interrupts = <44 0>;
interrupt-names = "hfxo";
ctune = <140>;
precision = <50>;
status = "disabled";
};
lfxo: lfxo@50020000 {
#clock-cells = <0>;
compatible = "silabs,series2-lfxo";
reg = <0x50020000 0x4000>;
clock-frequency = <32768>;
ctune = <63>;
precision = <50>;
timeout = <4096>;
status = "disabled";
};
hfrcodpll: hfrcodpll@50010000 {
#clock-cells = <0>;
compatible = "silabs,series2-hfrcodpll";
reg = <0x50010000 0x4000>;
clock-frequency = <DT_FREQ_M(19)>;
};
lfrco: lfrco@50024000 {
#clock-cells = <0>;
compatible = "silabs,series2-lfrco";
reg = <0x50024000 0x4000>;
clock-frequency = <32768>;
};
ulfrco: ulfrco@50028000 {
#clock-cells = <0>;
compatible = "fixed-clock";
reg = <0x50028000 0x4000>;
clock-frequency = <1000>;
};
msc: flash-controller@50030000 {
compatible = "silabs,series2-flash-controller";
reg = <0x50030000 0xC69>;
interrupts = <49 2>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
write-block-size = <4>;
erase-block-size = <8192>;
};
};
usart0: usart@5005c000 {
compatible = "silabs,usart-spi";
reg = <0x5005C000 0x400>;
interrupts = <13 2>, <14 2>;
interrupt-names = "rx", "tx";
clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
usart1: usart@50060000 {
compatible = "silabs,usart-uart";
reg = <0x50060000 0x400>;
interrupts = <15 2>, <16 2>;
interrupt-names = "rx", "tx";
clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
status = "disabled";
};
burtc0: burtc@50064000 {
compatible = "silabs,gecko-burtc";
reg = <0x50064000 0x3034>;
interrupts = <18 2>;
clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
status = "disabled";
};
rtcc0: stimer0: rtcc@58000000 {
compatible = "silabs,gecko-stimer";
reg = <0x58000000 0x3054>;
interrupts = <12 2>;
interrupt-names = "rtcc";
clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
clock-frequency = <32768>;
prescaler = <1>;
status = "disabled";
};
trng: trng@4c021000 {
compatible = "silabs,gecko-trng";
reg = <0x4C021000 0x1000>;
status = "disabled";
interrupts = <0x1 0x2>;
};
i2c0: i2c@5a010000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
reg = <0x5a010000 0x3044>;
interrupts = <27 2>;
clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@50068000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
reg = <0x50068000 0x3044>;
interrupts = <28 2>;
clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpio: gpio@5003c000 {
compatible = "silabs,gecko-gpio";
reg = <0x5003C000 0x440>;
ranges;
interrupts = <25 2>, <26 2>;
interrupt-names = "gpio_odd", "gpio_even";
clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
#address-cells = <1>;
#size-cells = <1>;
gpioa: gpio@5003c000 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C000 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@5003c030 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C030 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@5003c060 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C060 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@5003c090 {
compatible = "silabs,gecko-gpio-port";
reg = <0x5003C090 0x30>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
pinctrl: pin-controller@5003c440 {
compatible = "silabs,dbus-pinctrl";
reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
reg-names = "dbus", "abus";
};
clkin0: clkin0@5003c454 {
#clock-cells = <0>;
compatible = "fixed-clock";
reg = <0x5003c454 0x4>;
clock-frequency = <DT_FREQ_M(38)>;
};
dma0: dma@40040000{
compatible = "silabs,ldma";
reg = <0x40040000 0x4000>;
interrupts = <21 0>;
#dma-cells = <1>;
dma-channels = <8>;
status = "disabled";
};
wdog0: wdog@4a018000 {
compatible = "silabs,gecko-wdog";
reg = <0x4A018000 0x3028>;
interrupts = <43 2>;
clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
peripheral-id = <0>;
status = "disabled";
};
adc0: adc@5a004000 {
compatible = "silabs,gecko-iadc";
reg = <0x5a004000 0x4000>;
interrupts = <48 2>;
clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
status = "disabled";
#io-channel-cells = <1>;
};
dcdc: dcdc@50094000 {
compatible = "silabs,series2-dcdc";
reg = <0x50094000 0x4000>;
interrupts = <61 2>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};