modules: cmsis: move glue code to modules/cmsis

The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).

To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.

All files including CMSIS have been updated.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

arch/arm/core/aarch32/cortex_a_r/cache.c

@@ -14,7 +14,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 /* Cache Type Register */

arch/arm/core/aarch32/cortex_a_r/tcm.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 void z_arm_tcm_disable_ecc(void)
 {

arch/arm/core/aarch32/cortex_a_r/thread.c

@@ -5,7 +5,7 @@
  */
 
 #include <stdbool.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 bool z_arm_thread_is_in_user_mode(void)
 {

arch/arm/core/aarch32/cortex_m/cache.c

@@ -13,7 +13,7 @@
 
 #include <zephyr/arch/cpu.h>
 #include <zephyr/cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 void arch_dcache_enable(void)
 {

arch/arm/core/aarch32/cortex_m/fpu.c

@@ -6,7 +6,7 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/fpu.h>
 
 /**

arch/arm/core/aarch32/cortex_m/irq_init.c

@@ -11,7 +11,7 @@
  */
 
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_m/scb.c

@@ -18,7 +18,7 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/barrier.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/cache.h>
 

arch/arm/core/aarch32/cortex_m/thread.c

@@ -5,7 +5,7 @@
  */
 
 #include <stdbool.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 bool z_arm_thread_is_in_user_mode(void)
 {

arch/arm/core/aarch32/cortex_m/timing.c

@@ -15,7 +15,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/timing/timing.h>
 #include <aarch32/cortex_m/dwt.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys_clock.h>
 
 /**

arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <aarch32/cortex_m/tz.h>
 #include <aarch32/cortex_m/exc.h>
 

arch/arm/core/aarch32/irq_manage.c

@@ -17,7 +17,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
 	|| defined(CONFIG_CPU_AARCH32_CORTEX_R)
 #include <zephyr/drivers/interrupt_controller/gic.h>

arch/arm/core/aarch32/mmu/arm_mmu.c

@@ -29,7 +29,7 @@
 #include <zephyr/sys/mem_manage.h>
 #include <zephyr/sys/barrier.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "arm_mmu_priv.h"

arch/arm/include/aarch32/cortex_m/dwt.h

@@ -20,7 +20,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/__assert.h>
 
 #ifdef __cplusplus

arch/arm/include/aarch32/cortex_m/exc.h

@@ -22,7 +22,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/exc.h>
 #include <zephyr/irq_offload.h>
 

arch/arm/include/aarch32/cortex_m/stack.h

@@ -20,7 +20,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #ifdef __cplusplus
 extern "C" {

boards/arm/arty/board.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/gpio.h>

drivers/cache/cache_aspeed.c

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/drivers/syscon.h>
 #include <zephyr/sys/barrier.h>
 

drivers/clock_control/clock_control_mchp_xec.c

@@ -8,7 +8,7 @@
 
 #include <soc.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
 #include <zephyr/drivers/pinctrl.h>

drivers/display/display_stm32_ltdc.c

@@ -55,7 +55,7 @@ LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
 #endif
 
 #if defined(CONFIG_HAS_CMSIS_CORE_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #if __DCACHE_PRESENT == 1
 #define CACHE_INVALIDATE(addr, size)	SCB_InvalidateDCache_by_Addr((addr), (size))

drivers/gpio/gpio_mchp_xec_v2.c

@@ -13,7 +13,7 @@
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 
 #include <zephyr/drivers/gpio/gpio_utils.h>

drivers/interrupt_controller/intc_mchp_ecia_xec.c

@@ -13,7 +13,7 @@
 #define DT_DRV_COMPAT microchip_xec_ecia
 
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/device.h>
 #include <soc.h>
 #include <zephyr/sys/__assert.h>

drivers/kscan/kscan_mchp_xec.c

@@ -6,7 +6,7 @@
 
 #define DT_DRV_COMPAT microchip_xec_kscan
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <errno.h>
 #include <zephyr/device.h>
 #ifdef CONFIG_SOC_SERIES_MEC172X

drivers/ps2/ps2_mchp_xec.c

@@ -7,7 +7,7 @@
 
 #define DT_DRV_COMPAT microchip_xec_ps2
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <errno.h>
 #include <zephyr/device.h>
 #include <zephyr/kernel.h>

drivers/serial/uart_lpc11u6x.c

@@ -5,7 +5,7 @@
  */
 #define DT_DRV_COMPAT nxp_lpc11u6x_uart
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #include <zephyr/drivers/uart.h>
 #include <zephyr/drivers/clock_control.h>

drivers/timer/cortex_m_systick.c

@@ -7,7 +7,7 @@
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/spinlock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
 

drivers/timer/mchp_xec_rtos_timer.c

@@ -12,7 +12,7 @@
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/spinlock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 
 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");

include/zephyr/arch/arm/aarch32/barrier.h

@@ -11,9 +11,9 @@
 #endif
 
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #else
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #endif
 
 #ifdef __cplusplus

include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h

@@ -16,7 +16,7 @@
 
 #include <zephyr/types.h>
 #include <zephyr/sys/sys_io.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 #ifdef __cplusplus

include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h

@@ -8,7 +8,7 @@
 #ifndef _ASMLANGUAGE
 
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #endif
 
 /* Convenience macros to represent the ARMv7-M-specific

include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v8.h

@@ -32,7 +32,7 @@
 #define MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)
 #define MPU_RLAR_EN_Msk         (0x1UL)
 #else
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #endif
 
 /* Privileged No Access, Unprivileged No Access */

modules/cmsis/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} cmsis)
+
+if(CONFIG_CPU_CORTEX_M OR CONFIG_CPU_AARCH32_CORTEX_A OR CONFIG_CPU_AARCH32_CORTEX_R)
+  zephyr_include_directories(.)
+endif()

modules/cmsis/cmsis_core.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_H_
+
+#if defined(CONFIG_CPU_CORTEX_M)
+#include "cmsis_core_m.h"
+#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
+#include "cmsis_core_a_r.h"
+#endif
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_ */

modules/cmsis/cmsis_core_a_r.h

@@ -11,8 +11,8 @@
  * This header contains the interface to the ARM CMSIS Core headers.
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_
 
 #include <soc.h>
 
@@ -61,6 +61,6 @@ extern "C" {
 #error "Unknown device"
 #endif
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis_ext.h>
+#include "cmsis_core_a_r_ext.h"
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_ */
+#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_A_R_H_ */

modules/cmsis/cmsis_core_a_r_ext.h

@@ -15,8 +15,8 @@
  * NOTE: cmsis.h includes this file; do not manually include this file.
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_EXT_H_
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_A_R_EXT_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_EXT_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_A_R_EXT_H_
 
 /* FSR Register Definitions */
 #if defined(CONFIG_AARCH32_ARMV8_R)
@@ -74,4 +74,4 @@ __STATIC_FORCEINLINE uint32_t __get_DBGDSCR(void)
 	return result;
 }
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_EXT_H_ */
+#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_A_R_EXT_H_ */

modules/cmsis/cmsis_core_m.h

@@ -11,8 +11,8 @@
  * This header contains the interface to the ARM CMSIS Core headers.
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
+#ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_
+#define ZEPHYR_MODULES_CMSIS_CMSIS_M_H_
 
 #include <zephyr/arch/arm/aarch32/cortex_m/nvic.h>
 
@@ -105,4 +105,4 @@ typedef enum {
 #error "Unknown Cortex-M device"
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_CMSIS_H_ */
+#endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_H_ */

modules/trusted-firmware-m/interface/interface.c

@@ -8,7 +8,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/fpu.h>
 
 #include <tfm_ns_interface.h>

samples/application_development/code_relocation_nocopy/src/main.c

@@ -15,7 +15,7 @@
  * to configure the region appropriately in arm_mpu_regions.c.
  */
 #ifdef CONFIG_ARM_MPU
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 void disable_mpu_rasr_xn(void)
 {
 	uint32_t index;

samples/subsys/debug/debugmon/src/main.c

@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/sys/printk.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/exc.h>
 
 #define LED0_NODE DT_ALIAS(led0)

soc/arm/arm/fvp_aemv8r_aarch32/soc.c

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 void z_arm_platform_init(void)

soc/arm/atmel_sam/sam3x/soc.c

@@ -18,7 +18,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /*
  * PLL clock = Main * (MULA + 1) / DIVA

soc/arm/atmel_sam/sam4e/soc.c

@@ -18,7 +18,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Setup various clock on SoC at boot time.

soc/arm/atmel_sam/sam4s/soc.c

@@ -18,7 +18,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Setup various clock on SoC at boot time.

soc/arm/atmel_sam/same70/soc.c

@@ -15,7 +15,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL

soc/arm/atmel_sam/samv71/soc.c

@@ -15,7 +15,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL

soc/arm/atmel_sam0/common/soc_samd2x.c

@@ -22,12 +22,12 @@
  * GCLK Gen 3 -> ADC @ 8 MHz
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 
 #include <soc.h>
+#include <cmsis_core.h>
 
 /**
  * Fix different naming conventions for SAMD20

soc/arm/atmel_sam0/common/soc_saml2x.c

@@ -10,11 +10,11 @@
  * @brief Atmel SAML MCU series initialization code
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <soc.h>
+#include <cmsis_core.h>
 
 /* the SAML21 currently operates only in Performance Level 2... sleep
  * and low-power operation are not currently supported by the BSP

soc/arm/cypress/psoc6/soc.c

@@ -7,7 +7,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 
 #include "cy_syslib.h"

soc/arm/intel_socfpga_std/cyclonev/soc.c

@@ -12,9 +12,10 @@
 #include <zephyr/sys/util.h>
 #include <mmu.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 #include "soc.h"
 
+#include <cmsis_core.h>
+
 void arch_reserved_pages_update(void)
 {
 /* Function created to reserve the vector table  */

soc/arm/microchip_mec/mec1501/soc.c

@@ -10,7 +10,7 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /*
  * Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC

soc/arm/microchip_mec/mec172x/power.c

@@ -11,7 +11,7 @@
 #include <zephyr/pm/pm.h>
 #include <soc.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include "device_power.h"
 
 #include "soc_power_debug.h"

soc/arm/microchip_mec/mec172x/soc.c

@@ -10,7 +10,7 @@
 #include <soc.h>
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /* Enable SWD and ETM debug interface and pins.
  * NOTE: ETM TRACE pins exposed on MEC172x EVB J30 12,14,16,18,20.

soc/arm/nordic_nrf/nrf52/soc.c

@@ -14,11 +14,12 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <hal/nrf_power.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/nordic_nrf/nrf53/soc.c

@@ -14,7 +14,6 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 #include <nrf_erratas.h>
@@ -34,6 +33,8 @@
 #endif
 #include <soc_secure.h>
 
+#include <cmsis_core.h>
+
 #define PIN_XL1 0
 #define PIN_XL2 1
 

soc/arm/nordic_nrf/nrf91/soc.c

@@ -14,10 +14,11 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/nuvoton_npcx/common/power.c

@@ -45,7 +45,7 @@
  * INCLUDE FILES: soc_clock.h
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/espi.h>

soc/arm/nxp_imx/mcimx6x_m4/soc.c

@@ -8,9 +8,10 @@
 #include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include "wdog_imx.h"
 
+#include <cmsis_core.h>
+
 /* Initialize Resource Domain Controller. */
 static void SOC_RdcInit(void)
 {

soc/arm/nxp_imx/rt/soc_rt10xx.c

@@ -11,7 +11,6 @@
 #include <zephyr/linker/sections.h>
 #include <zephyr/linker/linker-defs.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
 #include <fsl_flexspi_nor_boot.h>
 #endif
@@ -22,6 +21,8 @@
 #include "usb.h"
 #endif
 
+#include <cmsis_core.h>
+
 #define CCM_NODE	DT_INST(0, nxp_imx_ccm)
 
 #define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b)				\

soc/arm/nxp_imx/rt/soc_rt11xx.c

@@ -14,7 +14,6 @@
 #include <fsl_gpc.h>
 #include <fsl_pmu.h>
 #include <fsl_dcdc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
 #include <fsl_flexspi_nor_boot.h>
 #endif
@@ -35,6 +34,8 @@
 #include "usb.h"
 #endif
 
+#include <cmsis_core.h>
+
 #define DUAL_CORE_MU_ENABLED \
 	(CONFIG_SECOND_CORE_MCUX && CONFIG_IPM && CONFIG_IPM_IMX_REV2)
 

soc/arm/nxp_kinetis/k2x/soc.c

@@ -23,7 +23,7 @@
 #include <fsl_common.h>
 #include <fsl_clock.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #define TIMESRC_OSCERCLK        (2)
 

soc/arm/nxp_kinetis/k6x/soc.c

@@ -20,7 +20,8 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 #define LPUART0SRC_OSCERCLK     (1)
 

soc/arm/nxp_kinetis/ke1xf/soc.c

@@ -13,7 +13,7 @@
 #include <zephyr/init.h>
 #include <fsl_clock.h>
 #include <fsl_cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #define ASSERT_WITHIN_RANGE(val, min, max, str) \
 	BUILD_ASSERT(val >= min && val <= max, str)

soc/arm/nxp_kinetis/kwx/soc_kw2xd.c

@@ -13,7 +13,8 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 #define PLLFLLSEL_MCGFLLCLK	(0)
 #define PLLFLLSEL_MCGPLLCLK	(1)

soc/arm/nxp_s32/s32k/soc.c

@@ -7,8 +7,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
+#include <cmsis_core.h>
 #include <OsIf.h>
 
 #ifdef CONFIG_XIP

soc/arm/nxp_s32/s32ze/soc.c

@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 #include <OsIf.h>

soc/arm/quicklogic_eos_s3/soc.c

@@ -8,7 +8,7 @@
 #include <zephyr/init.h>
 #include <soc.h>
 #include <soc_pinmap.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 void eos_s3_lock_enable(void)
 {

soc/arm/renesas_smartbond/da1469x/soc.c

@@ -5,7 +5,6 @@
  */
 
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <DA1469xAB.h>
@@ -14,6 +13,7 @@
 #include <da1469x_pd.h>
 #include <da1469x_pdc.h>
 #include <da1469x_trimv.h>
+#include <cmsis_core.h>
 
 #define REMAP_ADR0_QSPI           0x2
 

soc/arm/silabs_exx32/common/soc.c

@@ -9,7 +9,6 @@
  * @brief Common SoC initialization for the EXX32
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
@@ -18,6 +17,7 @@
 #include <em_cmu.h>
 #include <em_emu.h>
 #include <soc.h>
+#include <cmsis_core.h>
 
 #ifdef CONFIG_SOC_GECKO_DEV_INIT
 #include <sl_device_init_dcdc.h>

soc/arm/st_stm32/stm32c0/soc.c

@@ -11,10 +11,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *

soc/arm/st_stm32/stm32f0/soc.c

@@ -12,10 +12,11 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <cmsis_core.h>
+
 #if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
 extern void *_vector_table_pointer;
 #endif

soc/arm/st_stm32/stm32f1/soc.c

@@ -11,7 +11,8 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.

soc/arm/st_stm32/stm32f2/soc.c

@@ -13,11 +13,12 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <stm32_ll_system.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *

soc/arm/st_stm32/stm32f3/soc.c

@@ -12,7 +12,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.

soc/arm/st_stm32/stm32f4/soc.c

@@ -12,8 +12,8 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
+#include <cmsis_core.h>
 #include <stm32_ll_system.h>
 
 /**

soc/arm/st_stm32/stm32f7/soc.c

@@ -13,7 +13,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 #include <stm32_ll_system.h>
 
 /**

soc/arm/st_stm32/stm32g0/soc.c

@@ -12,9 +12,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
+
+#include <cmsis_core.h>
 #if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
 #include <stm32_ll_system.h>
 #include <stm32_ll_bus.h>

soc/arm/st_stm32/stm32g4/soc.c

@@ -12,8 +12,8 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
+#include <cmsis_core.h>
 #if defined(PWR_CR3_UCPD_DBDIS)
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>

soc/arm/st_stm32/stm32h5/soc.c

@@ -14,9 +14,10 @@
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_icache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/st_stm32/stm32h7/soc_m4.c

@@ -18,9 +18,10 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include "stm32_hsem.h"
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *

soc/arm/st_stm32/stm32h7/soc_m7.c

@@ -17,9 +17,10 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include "stm32_hsem.h"
 
+#include <cmsis_core.h>
+
 #if defined(CONFIG_STM32H7_DUAL_CORE)
 static int stm32h7_m4_wakeup(void)
 {

soc/arm/st_stm32/stm32l0/soc.c

@@ -11,13 +11,14 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_bus.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *

soc/arm/st_stm32/stm32l1/soc.c

@@ -11,12 +11,13 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 
+#include <cmsis_core.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *

soc/arm/st_stm32/stm32l4/soc.c

@@ -12,9 +12,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/st_stm32/stm32l5/soc.c

@@ -13,10 +13,11 @@
 #include <zephyr/init.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <stm32l5xx_ll_icache.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/st_stm32/stm32mp1/soc.c

@@ -14,7 +14,8 @@
 #include <zephyr/init.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+
+#include <cmsis_core.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.

soc/arm/st_stm32/stm32u5/soc.c

@@ -14,9 +14,10 @@
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_icache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/st_stm32/stm32wb/soc.c

@@ -11,9 +11,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/st_stm32/stm32wba/soc.c

@@ -16,10 +16,10 @@
 #include <stm32_ll_icache.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/irq.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/st_stm32/stm32wl/soc.c

@@ -11,12 +11,13 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 #include <stm32wlxx_ll_system.h>
 
 #include <zephyr/logging/log.h>
 
+#include <cmsis_core.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 

soc/arm/ti_lm3s6965/sys_arch_reboot.c

@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /**
  *

soc/arm/xilinx_zynq7000/xc7zxxx/soc.c

@@ -9,7 +9,7 @@
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "soc.h"
 

soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c

@@ -9,7 +9,7 @@
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "soc.h"
 

soc/arm/xilinx_zynqmp/soc.c

@@ -7,7 +7,8 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+
+#include <cmsis_core.h>
 
 void z_arm_platform_init(void)
 {

subsys/testsuite/include/zephyr/interrupt_util.h

@@ -10,7 +10,7 @@
 #define MS_TO_US(ms)  (ms * USEC_PER_MSEC)
 
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 static inline uint32_t get_available_nvic_line(uint32_t initial_offset)
 {

tests/application_development/code_relocation/src/main.c

@@ -17,7 +17,7 @@
  */
 
 #if (defined(CONFIG_ARM_MPU) && !defined(CONFIG_CPU_HAS_NXP_MPU))
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 void disable_mpu_rasr_xn(void)
 {
 	uint32_t index;

tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c

@@ -7,7 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/reboot.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/ztest.h>
 #include <zephyr/tc_util.h>
 

tests/arch/arm/arm_interrupt/src/arm_interrupt.c

@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 static volatile int test_flag;

tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c

@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 /* Offset for the Direct interrupt used in this test. */

tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c

@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #if defined(CONFIG_ARM_SECURE_FIRMWARE) && \
 	defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c

@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 static volatile int test_flag;

tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c

@@ -6,7 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/linker/sections.h>