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flash: it8xxx2: add a short delay before #CS be driven high

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The delay will ensure last byte has been latched in before

This also change the method of reading status register from re-send
read status command on each read to read status register continuously.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2021-08-11 16:18:57 +08:00 • committed by Christopher Friedt
commit 9c47f314a5
2 changed files with 27 additions and 8 deletions
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5
soc/riscv/riscv-ite/common/chip_chipregs.h
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@ -1856,6 +1856,11 @@ enum chip_pll_mode {
#define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02)
#define IT83XX_GCTRL_DBGROS ECREG(IT83XX_GCTRL_BASE + 0x03)
#define IT83XX_SMB_DBGR BIT(0)
/*
* Writing 00h to this register and the CPU program counter will be paused
* until the next low to high transition of the 65.536 clock.
*/
#define IT83XX_GCTRL_WNCKR ECREG(IT83XX_GCTRL_BASE + 0x0B)
#define IT83XX_GCTRL_RSTS ECREG(IT83XX_GCTRL_BASE + 0x06)
#define IT83XX_GCTRL_BADRSEL ECREG(IT83XX_GCTRL_BASE + 0x0A)