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boards: Update arc em_starterkit support from 2.2 to 2.3

Browse source 
Here are the main changes:
* board: Update EMSK onboard resources such as Button, Switch and LEDs
  + update soc.h for em7d, em9d, em11d
  + update board.h for em_starterkit board
* arc: Add floating point support and code density support
  + add kconfig configuration
  + add compiler options
  + add register definitions, marcos, assembly codes
  + fixes in existing codes and configurations.
* arc: Update detailed board configurations for cores of emsk 2.3
* script: Provide arc_debugger.sh for debugging em_starterkit board
  + make BOARD=em_starterkit debug
    This will start openocd server for emsk, and arc gdb will connect
    to this debug server, user can run `continue` command if user just
    want to run the application, or other commands if debugging needed.
  + make BOARD=em_starterkit debugserver
    This will start an openocd debugger server for emsk, and user can
    connect to this debugserver using arc gdb and do what they want to.
  + make BOARD=em_starterkit flash
    This will download the zephyr application elf file to emsk,
    and run it.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
This commit is contained in:
Huaqi Fang 2017-05-17 03:18:51 -04:00 • committed by ruuddw
commit 9bc69a46fa
26 changed files with 576 additions and 182 deletions
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62
arch/arc/Kconfig
View file

@ -24,6 +24,21 @@ config ARCH_DEFCONFIG
string
default "arch/arc/defconfig"
config CPU_HAS_MPU
bool
# Omit prompt to signify "hidden" option
default n
help
This option is enabled when the CPU has a Memory Protection Unit (MPU).
config CPU_HAS_FPU
# Hidden config selected by CPU family
bool
default n
help
This option is enabled when the CPU has hardware floating point
unit.
menu "ARC EM4 processor options"
config CPU_ARCEM4
@ -44,17 +59,6 @@ config CPU_ARCV2
help
This option signifies the use of a CPU of the ARCv2 family.
config NSIM
prompt "Running on the MetaWare nSIM simulator"
bool
default n
help
For running on nSIM simulator.
a) Uses non-XIP to run in RAM.
b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
a pc_size of 16 (default).
config DATA_ENDIANNESS_LITTLE
bool
default y
@ -156,8 +160,40 @@ config HARVARD
bool
default n
help
The ARC CPU can be configured to have two busses;
one for instruction fetching and another that serves as a data bus.
The ARC CPU can be configured to have two busses;
one for instruction fetching and another that serves as a data bus.
config CODE_DENSITY
prompt "Code Density Option"
bool
default n
help
Enbale code density option to get better code desntiy
menu "Floating Point Options"
depends on CPU_HAS_FPU
config FLOAT
bool
prompt "Floating point registers"
default n
help
This option allows tasks and fibers to use the floating point registers.
By default, only a single task or fiber may use the registers.
Disabling this option means that any task or fiber that uses a
floating point register will get a fatal exception.
config FP_SHARING
bool
prompt "Floating point register sharing"
depends on FLOAT
default n
help
This option allows multiple tasks and fibers to use the floating point
registers.
endmenu
config ICCM_SIZE
int "ICCM Size in kB"

8
arch/arc/Makefile
View file

@ -1,3 +1,8 @@
# Enable debug support in mdb
# Dwarf version 2 can be recognized by mdb
# The default dwarf version in gdb is not recognized by mdb
cflags-y += $(call cc-option, -g3 -gdwarf-2)
cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
# Without this (poorly named) option, compiler may generate undefined
@ -16,5 +21,4 @@ soc-cxxflags ?= $(soc-cflags)
soc-aflags ?= $(soc-cflags)
KBUILD_CFLAGS += $(soc-cflags)
KBUILD_CXXFLAGS += $(soc-cxxflags)
KBUILD_AFLAGS += $(soc-aflags)
KBUILD_AFLAGS += $(soc-aflags)

8
arch/arc/core/fast_irq.S
View file

@ -181,6 +181,14 @@ _firq_no_reschedule:
pop_s r0
mov lp_count,r0
ld r0,[saved_r0]
#ifdef CONFIG_CODE_DENSITY
pop_s r0
sr r0, [_ARC_V2_EI_BASE]
pop_s r0
sr r0, [_ARC_V2_LDI_BASE]
pop_s r0
sr r0, [_ARC_V2_JLI_BASE]
#endif
add sp,sp,8 /* don't need ilink & status32_po from stack */
#endif
rtie

18
arch/arc/core/offsets/offsets.c
View file

@ -52,6 +52,11 @@ GEN_OFFSET_SYM(_isf_t, blink);
GEN_OFFSET_SYM(_isf_t, lp_end);
GEN_OFFSET_SYM(_isf_t, lp_start);
GEN_OFFSET_SYM(_isf_t, lp_count);
#ifdef CONFIG_CODE_DENSITY
GEN_OFFSET_SYM(_isf_t, ei_base);
GEN_OFFSET_SYM(_isf_t, ldi_base);
GEN_OFFSET_SYM(_isf_t, jli_base);
#endif
GEN_OFFSET_SYM(_isf_t, pc);
GEN_OFFSET_SYM(_isf_t, status32);
GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
@ -75,6 +80,19 @@ GEN_OFFSET_SYM(_callee_saved_stack_t, r25);
GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
#ifdef CONFIG_FP_SHARING
GEN_OFFSET_SYM(_callee_saved_stack_t, r58);
GEN_OFFSET_SYM(_callee_saved_stack_t, r59);
GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_status);
GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_ctrl);
#ifdef CONFIG_FP_FPU_DA
GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2h);
GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2l);
GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1h);
GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1l);
#endif
#endif
GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));

6
arch/arc/core/regular_irq.S
View file

@ -121,7 +121,8 @@ SECTION_FUNC(TEXT, _rirq_exit)
*/
ldh_s r0, [r2, _thread_offset_to_preempt]
mov r3, _NON_PREEMPT_THRESHOLD
brhs.d r0, r3, _rirq_no_reschedule
cmp_s r0, r3
bhs.d _rirq_no_reschedule
/*
* Both (a)reschedule and (b)non-reschedule cases need to load the
@ -137,7 +138,8 @@ SECTION_FUNC(TEXT, _rirq_exit)
/* check if the current thread needs to be rescheduled */
ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
breq r0, r2, _rirq_no_reschedule
cmp_s r0, r2
beq _rirq_no_reschedule
/* cached thread to run is in r0, fall through */

15
arch/arc/include/kernel_arch_data.h
View file

@ -74,6 +74,8 @@ struct _irq_stack_frame {
typedef struct _irq_stack_frame _isf_t;
/* callee-saved registers pushed on the stack, not in k_thread */
struct _callee_saved_stack {
u32_t r13;
@ -94,6 +96,19 @@ struct _callee_saved_stack {
/* r28 is the stack pointer and saved separately */
/* r29 is ILINK and does not need to be saved */
u32_t r30;
#ifdef CONFIG_FP_SHARING
u32_t r58;
u32_t r59;
u32_t fpu_status;
u32_t fpu_ctrl;
#ifdef CONFIG_FP_FPU_DA
u32_t dpfp2h;
u32_t dpfp2l;
u32_t dpfp1h;
u32_t dpfp1l;
#endif
#endif
/*
* No need to save r31 (blink), it's either alread pushed as the pc or
* blink on an irq stack frame.

64
arch/arc/include/swap_macros.h
View file

@ -42,6 +42,26 @@ extern "C" {
st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
st fp, [sp, ___callee_saved_stack_t_fp_OFFSET]
st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
#ifdef CONFIG_FP_SHARING
st r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
st r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
lr r13, [_ARC_V2_FPU_STATUS]
st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
lr r13, [_ARC_V2_FPU_CTRL]
st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
#ifdef CONFIG_FP_FPU_DA
lr r13, [_ARC_V2_FPU_DPFP1L]
st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
lr r13, [_ARC_V2_FPU_DPFP1H]
st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
lr r13, [_ARC_V2_FPU_DPFP2L]
st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
lr r13, [_ARC_V2_FPU_DPFP2H]
st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
#endif
#endif
/* save stack pointer in struct tcs */
st sp, [r2, _thread_offset_to_sp]
@ -69,6 +89,31 @@ extern "C" {
ld fp, [sp, ___callee_saved_stack_t_fp_OFFSET]
ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
#ifdef CONFIG_FP_SHARING
ld r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
ld r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
sr r13, [_ARC_V2_FPU_STATUS]
ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
sr r13, [_ARC_V2_FPU_CTRL]
#ifdef CONFIG_FP_FPU_DA
ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
sr r13, [_ARC_V2_FPU_DPFP1L]
ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
sr r13, [_ARC_V2_FPU_DPFP1H]
ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
sr r13, [_ARC_V2_FPU_DPFP2L]
ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
sr r13, [_ARC_V2_FPU_DPFP2H]
#endif
#endif
add_s sp, sp, ___callee_saved_stack_t_SIZEOF
.endm
@ -111,6 +156,15 @@ extern "C" {
st_s r1, [sp, ___isf_t_lp_start_OFFSET]
st_s r0, [sp, ___isf_t_lp_end_OFFSET]
#ifdef CONFIG_CODE_DENSITY
lr r1, [_ARC_V2_JLI_BASE]
lr r0, [_ARC_V2_LDI_BASE]
lr r2, [_ARC_V2_EI_BASE]
st_s r1, [sp, ___isf_t_jli_base_OFFSET]
st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
st_s r2, [sp, ___isf_t_ei_base_OFFSET]
#endif
.endm
/*
@ -121,6 +175,15 @@ extern "C" {
ld blink, [sp, ___isf_t_blink_OFFSET]
#ifdef CONFIG_CODE_DENSITY
ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
sr r1, [_ARC_V2_JLI_BASE]
sr r0, [_ARC_V2_LDI_BASE]
sr r2, [_ARC_V2_EI_BASE]
#endif
ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
mov lp_count, r0
ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
@ -143,6 +206,7 @@ extern "C" {
ld_s r1, [sp, ___isf_t_r1_OFFSET]
ld_s r0, [sp, ___isf_t_r0_OFFSET]
/*
* All gprs have been reloaded, the only one that is still usable is
* ilink.

4
arch/arc/include/v2/irq.h
View file

@ -26,6 +26,7 @@ extern "C" {
#define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8
#define _ARC_V2_AUX_IRQ_CTRL_32_REGS 16
#define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
#define _ARC_V2_WAKE_IRQ_LEVEL _ARC_V2_DEF_IRQ_LEVEL
@ -43,6 +44,9 @@ static ALWAYS_INLINE void _irq_setup(void)
{
u32_t aux_irq_ctrl_value = (
_ARC_V2_AUX_IRQ_CTRL_LOOP_REGS | /* save lp_xxx registers */
#ifdef CONFIG_CODE_DENSITY
_ARC_V2_AUX_IRQ_CTRL_LP | /* save code density registers */
#endif
_ARC_V2_AUX_IRQ_CTRL_BLINK | /* save blink */
_ARC_V2_AUX_IRQ_CTRL_14_REGS /* save r0 -> r13 (caller-saved) */
);

5
arch/arc/soc/em11d/Kconfig.defconfig
View file

@ -19,7 +19,7 @@ config NUM_IRQ_PRIO_LEVELS
config NUM_IRQS
# must be > the highest interrupt number used
default 36
default 38
config RGF_NUM_BANKS
default 2
@ -58,6 +58,9 @@ config DCCM_SIZE
config CACHE_FLUSHING
def_bool y
config FP_FPU_DA
def_bool y
if GPIO
config GPIO_DW

2
arch/arc/soc/em11d/Kconfig.soc
View file

@ -1,3 +1,5 @@
config SOC_EM11D
bool "Synopsys ARC EM11D"
select CPU_HAS_FPU

18
arch/arc/soc/em11d/Makefile
View file

@ -1,2 +1,16 @@
soc-cflags = $(call cc-option,-mcpu=arcem) \
$(call cc-option,-mno-sdata)
# -mcpu=em4_fpuda is added to KBUILD_CFLAGS to make cc-option check the options correctly
KBUILD_CFLAGS += -mcpu=em4_fpuda
soc-cflags += $(call cc-option, -mcpu=em4_fpuda -mno-sdata -mdiv-rem -mswap -mnorm) \
$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
$(call cc-option,--param l1-cache-size=16384) \
$(call cc-option,--param l1-cache-line-size=32)
ifeq ($(CONFIG_CODE_DENSITY), y)
soc-cflags += $(call cc-option, -mcode-density)
endif
ifeq ($(CONFIG_FLOAT), y)
soc-cflags += $(call cc-option, -mfpu=fpuda_all)
endif

91
arch/arc/soc/em11d/soc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
* Copyright (c) 2017 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,63 +18,68 @@
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
/* IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_CORE_DMA_COMPLETE 22
#define IRQ_CORE_DMA_ERROR 23
#ifndef _ASMLANGUAGE
#include <misc/util.h>
#include <drivers/rand32.h>
#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define ARCV2_TIMER0_INT_PRI 0
#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define ARCV2_TIMER0_INT_PRI 0
#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define ARCV2_TIMER1_INT_PRI 1
#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define ARCV2_TIMER1_INT_PRI 1
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
/* I2C */
/* I2C_0 is on Pmod2 connector */
#define I2C_DW_0_BASE_ADDR 0xF0004000
#define I2C_DW_0_IRQ 23
#define I2C_DW_0_BASE_ADDR 0xF0004000
#define I2C_DW_0_IRQ 25
/* I2C_1 is on Pmod4 connector */
#define I2C_DW_1_BASE_ADDR 0xF0005000
#define I2C_DW_1_IRQ 24
#define I2C_DW_1_BASE_ADDR 0xF0005000
#define I2C_DW_1_IRQ 26
#define I2C_DW_IRQ_FLAGS 0
/* GPIO */
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define GPIO_DW_0_IRQ 22
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define GPIO_DW_0_IRQ 24
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
#define GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
#define GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
#define GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
#define GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
@ -83,15 +88,15 @@
/* SPI */
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define SPI_DW_PORT_0_REGS 0xF0006000
#define SPI_DW_PORT_1_REGS 0xF0007000
#define SPI_DW_PORT_0_REGS 0xF0006000
#define SPI_DW_PORT_1_REGS 0xF0007000
#define SPI_DW_PORT_0_IRQ 25
#define SPI_DW_PORT_1_IRQ 26
#define SPI_DW_PORT_0_IRQ 27
#define SPI_DW_PORT_1_IRQ 28
#define SPI_DW_IRQ_FLAGS 0
#define SPI_DW_IRQ_FLAGS 0
/*
* SPI Chip Select Assignments on EM Starter Kit
@ -106,18 +111,22 @@
/*
* UART
UART0 vector 27 0xF0008000
UART1 vector 28 0xF0009000
UART2 vector 29 0xF000A000
UART0 vector 29 0xF0008000
UART1 vector 30 0xF0009000
UART2 vector 31 0xF000A000
*/
#define UART_NS16550_PORT_0_BASE_ADDR 0xF0008000
#define UART_NS16550_PORT_0_IRQ 27
#define UART_NS16550_PORT_0_IRQ 29
#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_1_BASE_ADDR 0xF0009000
#define UART_NS16550_PORT_1_IRQ 28
#define UART_NS16550_PORT_1_IRQ 30
#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_2_BASE_ADDR 0xF000A000
#define UART_NS16550_PORT_2_IRQ 31
#define UART_NS16550_PORT_2_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_IRQ_FLAGS 0 /* Default */
#endif /* !_ASMLANGUAGE */

4
arch/arc/soc/em7d/Kconfig.defconfig
View file

@ -19,13 +19,13 @@ config NUM_IRQ_PRIO_LEVELS
config NUM_IRQS
# must be > the highest interrupt number used
default 36
default 38
config RGF_NUM_BANKS
default 1
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 30000000
default 25000000
config HARVARD
def_bool n

14
arch/arc/soc/em7d/Makefile
View file

@ -1,2 +1,12 @@
soc-cflags = $(call cc-option,-mcpu=arcem) \
$(call cc-option,-mno-sdata)
# -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
KBUILD_CFLAGS += -mcpu=em4_dmips
soc-cflags = $(call cc-option,-mcpu=em4_dmips -mno-sdata) \
$(call cc-option,-mdiv-rem -mswap -mnormm) \
$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
$(call cc-option,--param l1-cache-size=16384) \
$(call cc-option,--param l1-cache-line-size=32)
ifeq ($(CONFIG_CODE_DENSITY), y)
soc-cflags += $(call cc-option,-mcode-density)
endif

92
arch/arc/soc/em7d/soc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
* Copyright (c) 2017 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,63 +18,69 @@
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
/* IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_SEC_TIMER0 20
#define IRQ_CORE_DMA_COMPLETE 22
#define IRQ_CORE_DMA_ERROR 23
#ifndef _ASMLANGUAGE
#include <misc/util.h>
#include <drivers/rand32.h>
#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define ARCV2_TIMER0_INT_PRI 0
#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define ARCV2_TIMER0_INT_PRI 0
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define ARCV2_TIMER1_INT_PRI 1
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
/* I2C */
/* I2C_0 is on Pmod2 connector */
#define I2C_DW_0_BASE_ADDR 0xF0004000
#define I2C_DW_0_IRQ 23
#define I2C_DW_0_BASE_ADDR 0xF0004000
#define I2C_DW_0_IRQ 25
/* I2C_1 is on Pmod4 connector */
#define I2C_DW_1_BASE_ADDR 0xF0005000
#define I2C_DW_1_IRQ 24
#define I2C_DW_1_BASE_ADDR 0xF0005000
#define I2C_DW_1_IRQ 26
#define I2C_DW_IRQ_FLAGS 0
/* GPIO */
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define GPIO_DW_0_IRQ 22
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define GPIO_DW_0_IRQ 24
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
#define GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
#define GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
#define GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
#define GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
@ -83,15 +89,15 @@
/* SPI */
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define SPI_DW_PORT_0_REGS 0xF0006000
#define SPI_DW_PORT_1_REGS 0xF0007000
#define SPI_DW_PORT_0_REGS 0xF0006000
#define SPI_DW_PORT_1_REGS 0xF0007000
#define SPI_DW_PORT_0_IRQ 25
#define SPI_DW_PORT_1_IRQ 26
#define SPI_DW_PORT_0_IRQ 27
#define SPI_DW_PORT_1_IRQ 28
#define SPI_DW_IRQ_FLAGS 0
#define SPI_DW_IRQ_FLAGS 0
/*
* SPI Chip Select Assignments on EM Starter Kit
@ -106,18 +112,22 @@
/*
* UART
UART0 vector 27 0xF0008000
UART1 vector 28 0xF0009000
UART2 vector 29 0xF000A000
UART0 vector 29 0xF0008000
UART1 vector 30 0xF0009000
UART2 vector 31 0xF000A000
*/
#define UART_NS16550_PORT_0_BASE_ADDR 0xF0008000
#define UART_NS16550_PORT_0_IRQ 27
#define UART_NS16550_PORT_0_IRQ 29
#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_1_BASE_ADDR 0xF0009000
#define UART_NS16550_PORT_1_IRQ 28
#define UART_NS16550_PORT_1_IRQ 30
#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_2_BASE_ADDR 0xF000A000
#define UART_NS16550_PORT_2_IRQ 31
#define UART_NS16550_PORT_2_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_IRQ_FLAGS 0 /* Default */
#endif /* !_ASMLANGUAGE */

2
arch/arc/soc/em9d/Kconfig.defconfig
View file

@ -19,7 +19,7 @@ config NUM_IRQ_PRIO_LEVELS
config NUM_IRQS
# must be > the highest interrupt number used
default 36
default 38
config RGF_NUM_BANKS
default 2

1
arch/arc/soc/em9d/Kconfig.soc
View file

@ -1,3 +1,4 @@
config SOC_EM9D
bool "Synopsys ARC EM9D"
select CPU_HAS_FPU

16
arch/arc/soc/em9d/Makefile
View file

@ -1,2 +1,14 @@
soc-cflags = $(call cc-option,-mcpu=arcem) \
$(call cc-option,-mno-sdata)
# -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
KBUILD_CFLAGS += -mcpu=em4_fpus
soc-cflags += $(call cc-option,-mcpu=em4_fpus -mno-sdata) \
$(call cc-option,-mdiv-rem -mswap -mnormm) \
$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
ifeq ($(CONFIG_CODE_DENSITY), y)
soc-cflags += $(call cc-option,-mcode-density)
endif
ifeq ($(CONFIG_FLOAT), y)
soc-cflags += $(call cc-option,-mfpu=fpus_all)
endif

91
arch/arc/soc/em9d/soc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
* Copyright (c) 2017 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,63 +18,68 @@
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
/* IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_CORE_DMA_COMPLETE 22
#define IRQ_CORE_DMA_ERROR 23
#ifndef _ASMLANGUAGE
#include <misc/util.h>
#include <drivers/rand32.h>
#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define ARCV2_TIMER0_INT_PRI 0
#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define ARCV2_TIMER0_INT_PRI 0
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define ARCV2_TIMER1_INT_PRI 1
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
/* I2C */
/* I2C_0 is on Pmod2 connector */
#define I2C_DW_0_BASE_ADDR 0xF0004000
#define I2C_DW_0_IRQ 23
#define I2C_DW_0_BASE_ADDR 0xF0004000
#define I2C_DW_0_IRQ 25
/* I2C_1 is on Pmod4 connector */
#define I2C_DW_1_BASE_ADDR 0xF0005000
#define I2C_DW_1_IRQ 24
#define I2C_DW_1_BASE_ADDR 0xF0005000
#define I2C_DW_1_IRQ 26
#define I2C_DW_IRQ_FLAGS 0
/* GPIO */
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define GPIO_DW_0_IRQ 22
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define GPIO_DW_0_IRQ 24
#define GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
#define GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
#define GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
#define GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
#define GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
@ -83,15 +88,15 @@
/* SPI */
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define SPI_DW_PORT_0_REGS 0xF0006000
#define SPI_DW_PORT_1_REGS 0xF0007000
#define SPI_DW_PORT_0_REGS 0xF0006000
#define SPI_DW_PORT_1_REGS 0xF0007000
#define SPI_DW_PORT_0_IRQ 25
#define SPI_DW_PORT_1_IRQ 26
#define SPI_DW_PORT_0_IRQ 27
#define SPI_DW_PORT_1_IRQ 28
#define SPI_DW_IRQ_FLAGS 0
#define SPI_DW_IRQ_FLAGS 0
/*
* SPI Chip Select Assignments on EM Starter Kit
@ -106,18 +111,22 @@
/*
* UART
UART0 vector 27 0xF0008000
UART1 vector 28 0xF0009000
UART2 vector 29 0xF000A000
UART0 vector 29 0xF0008000
UART1 vector 30 0xF0009000
UART2 vector 31 0xF000A000
*/
#define UART_NS16550_PORT_0_BASE_ADDR 0xF0008000
#define UART_NS16550_PORT_0_IRQ 27
#define UART_NS16550_PORT_0_IRQ 29
#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_1_BASE_ADDR 0xF0009000
#define UART_NS16550_PORT_1_IRQ 28
#define UART_NS16550_PORT_1_IRQ 30
#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_2_BASE_ADDR 0xF000A000
#define UART_NS16550_PORT_2_IRQ 31
#define UART_NS16550_PORT_2_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_IRQ_FLAGS 0 /* Default */
#endif /* !_ASMLANGUAGE */

4
boards/arc/em_starterkit/Kconfig.board
View file

@ -10,7 +10,7 @@ config BOARD_EM_STARTERKIT
help
The DesignWare ARC EM Starter Kit board is a board
that can host up to 3 different SOC FPGA bit files.
Version 2.2 firmware supports EM7D, EM9D and EM11D configurations.
Version 2.3 firmware supports EM7D, EM9D and EM11D configurations.
EM9D using CCM memories and is a Harvard Architecture.
EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache.
EM7D has secureshield feature, which is not supported in Zephyr currently.

19
boards/arc/em_starterkit/Makefile.board
View file

@ -1,16 +1,7 @@
#
# TODO: This file is WRONG currently.
# The Zephyr-SDK tools don't yet support working with the ARC EM Starter Kit
# See doc/board/em_starterkit.rst for more details.
#
#FLASH_SCRIPT = openocd.sh
# ^^ Keep FLASH_SCRIPT undefined for now since flashing a self-boot image
# is not yet supported by Zephyr Makefile.
OPENOCD_PRE_CMD = "targets 1"
OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_BIN_NAME} $(CONFIG_ICCM_BASE_ADDRESS)"
OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} $(CONFIG_ICCM_BASE_ADDRESS)"
FLASH_SCRIPT = arc_debugger.sh
DEBUG_SCRIPT = arc_debugger.sh
GDB_PORT = 3333
export OPENOCD_PRE_CMD FLASH_SCRIPT OPENOCD_VERIFY_CMD OPENOCD_LOAD_CMD GDB_PORT
OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_ELF_NAME}"
OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_ELF_NAME}"
export FLASH_SCRIPT DEBUG_SCRIPT OPENOCD_VERIFY_CMD OPENOCD_LOAD_CMD

51
boards/arc/em_starterkit/board.h
View file

@ -9,4 +9,55 @@
#include <soc.h>
/* Switches */
#define SW0_GPIO_PIN 0
#define SW0_GPIO_NAME CONFIG_GPIO_DW_2_NAME
#define SW1_GPIO_PIN 1
#define SW1_GPIO_NAME CONFIG_GPIO_DW_2_NAME
#define SW2_GPIO_PIN 2
#define SW2_GPIO_NAME CONFIG_GPIO_DW_2_NAME
#define SW3_GPIO_PIN 3
#define SW3_GPIO_NAME CONFIG_GPIO_DW_2_NAME
/* Buttons */
#define BTN0_GPIO_PIN 0
#define BTN0_GPIO_NAME CONFIG_GPIO_DW_0_NAME
#define BTN1_GPIO_PIN 1
#define BTN1_GPIO_NAME CONFIG_GPIO_DW_0_NAME
#define BTN2_GPIO_PIN 2
#define BTN2_GPIO_NAME CONFIG_GPIO_DW_0_NAME
/* Onboard LEDs */
#define LED0_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED0_GPIO_PIN 0
#define LED1_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED1_GPIO_PIN 1
#define LED2_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED2_GPIO_PIN 2
#define LED3_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED3_GPIO_PIN 3
#define LED4_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED4_GPIO_PIN 4
#define LED5_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED5_GPIO_PIN 5
#define LED6_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED6_GPIO_PIN 6
#define LED7_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED7_GPIO_PIN 7
#define LED8_GPIO_PORT CONFIG_GPIO_DW_1_NAME
#define LED8_GPIO_PIN 8
#endif /* __INC_BOARD_H */

2
boards/arc/em_starterkit/em_starterkit_defconfig
View file

@ -1,5 +1,5 @@
CONFIG_ARC=y
CONFIG_SOC_EM7D=y
CONFIG_SOC_EM11D=y
CONFIG_BOARD_EM_STARTERKIT=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_XIP=n

25
boards/arc/em_starterkit/support/openocd.cfg
View file

@ -1,17 +1,12 @@
#
# TODO: This file cannot be used yet. snps_em_sk.cfg is WRONG in Zephyr-SDK.
# Instead the user must download newer ARC GNU tools from github.
# See doc/board/em_starterkit.rst for more details.
#
#source [find interface/digilent-hs1.cfg] ...done in board file.
source [find board/snps_em_sk.cfg]
# Configure JTAG cable
# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
source [find interface/ftdi/digilent-hs1.cfg]
#em_starterkit.em9d configure -event gdb-attach {
# reset halt
## gdb_breakpoint_override hard
#}
# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
adapter_khz 5000
#em_starterkit.em9d configure -event gdb-detach {
# resume
# shutdown
#}
# ARCs support only JTAG.
transport select jtag
# Configure FPGA. This script supports both LX45 and LX150.
source [find target/snps_em_sk_fpga.cfg]

9
include/arch/arc/v2/aux_regs.h
View file

@ -73,6 +73,9 @@ extern "C" {
#define _ARC_V2_IRQ_PRIORITY 0x206
#define _ARC_V2_KSTACK_TOP 0x264
#define _ARC_V2_KSTACK_BASE 0x265
#define _ARC_V2_JLI_BASE 0x290
#define _ARC_V2_LDI_BASE 0x291
#define _ARC_V2_EI_BASE 0x292
#define _ARC_V2_ERET 0x400
#define _ARC_V2_ERSTATUS 0x402
#define _ARC_V2_ECR 0x403
@ -84,6 +87,12 @@ extern "C" {
#define _ARC_V2_IRQ_STATUS 0x40f
#define _ARC_V2_IRQ_PULSE_CANCEL 0x415
#define _ARC_V2_IRQ_PENDING 0x416
#define _ARC_V2_FPU_CTRL 0x300
#define _ARC_V2_FPU_STATUS 0x301
#define _ARC_V2_FPU_DPFP1L 0x302
#define _ARC_V2_FPU_DPFP1H 0x303
#define _ARC_V2_FPU_DPFP2L 0x304
#define _ARC_V2_FPU_DPFP2H 0x305
/* STATUS32/STATUS32_P0 bits */
#define _ARC_V2_STATUS32_H (1 << 0)

127
scripts/support/arc_debugger.sh Executable file
View file

@ -0,0 +1,127 @@
#!/bin/sh
# This script is loosly based on a script with same purpose provided
# by RIOT-OS (https://github.com/RIOT-OS/RIOT)
OPENOCD=${OPENOCD:-openocd}
OPENOCD_CMD="${OPENOCD}${OPENOCD_DEFAULT_PATH:+ -s $OPENOCD_DEFAULT_PATH}"
OPENOCD_CONFIG=${ZEPHYR_BASE}/boards/${ARCH}/${BOARD_NAME}/support/openocd.cfg
BIN_NAME=${O}/${KERNEL_BIN_NAME}
ELF_NAME=${O}/${KERNEL_ELF_NAME}
test_config() {
if [ ! -f "${OPENOCD_CONFIG}" ]; then
echo "Error: Unable to locate OpenOCD configuration file: ${OPENOCD_CONFIG}"
exit 1
fi
if ! which ${OPENOCD} >/dev/null 2>&1; then
echo "Error: Unable to locate OpenOCD executable: ${OPENOCD}"
exit 1
fi
}
test_bin() {
if [ ! -f "${BIN_NAME}" ]; then
echo "Error: Unable to locate image binary: ${BIN_NAME}"
exit 1
fi
}
do_flash() {
test_config
test_bin
# flash device with specified image
# setsid is needed so that Ctrl+C in GDB doesn't kill OpenOCD
[ -z "${SETSID}" ] && SETSID="$(which setsid)"
# temporary file that saves OpenOCD pid
OCD_PIDFILE=$(mktemp -t "openocd_pid.XXXXXXXXXX")
# cleanup after script terminates
trap "cleanup ${OCD_PIDFILE}" EXIT
# don't trap on Ctrl+C, because GDB keeps running
trap '' INT
# start OpenOCD as GDB server
${SETSID} sh -c "${OPENOCD_CMD} -f '${OPENOCD_CONFIG}' \
${OPENOCD_EXTRA_INIT} \
-c 'tcl_port ${TCL_PORT:-6333}' \
-c 'telnet_port ${TELNET_PORT:-4444}' \
-c 'gdb_port ${GDB_PORT:-3333}' \
-c 'init' \
-c 'targets' \
-c 'halt' \
& \
echo \$! > $OCD_PIDFILE" &
# connect to the GDB server
${GDB} ${TUI} -ex "target remote :${GDB_PORT:-3333}" \
-ex "load" -ex "c" ${ELF_NAME}
# will be called by trap
cleanup() {
OCD_PID="$(cat $OCD_PIDFILE)"
kill ${OCD_PID} &>/dev/null
rm -f "$OCD_PIDFILE"
exit 0
}
}
do_debug() {
test_config
test_bin
# setsid is needed so that Ctrl+C in GDB doesn't kill OpenOCD
[ -z "${SETSID}" ] && SETSID="$(which setsid)"
# temporary file that saves OpenOCD pid
OCD_PIDFILE=$(mktemp -t "openocd_pid.XXXXXXXXXX")
# cleanup after script terminates
trap "cleanup ${OCD_PIDFILE}" EXIT
# don't trap on Ctrl+C, because GDB keeps running
trap '' INT
# start OpenOCD as GDB server
${SETSID} sh -c "${OPENOCD_CMD} -f '${OPENOCD_CONFIG}' \
${OPENOCD_EXTRA_INIT} \
-c 'tcl_port ${TCL_PORT:-6333}' \
-c 'telnet_port ${TELNET_PORT:-4444}' \
-c 'gdb_port ${GDB_PORT:-3333}' \
-c 'init' \
-c 'targets' \
-c 'halt' \
& \
echo \$! > $OCD_PIDFILE" &
# connect to the GDB server
${GDB} ${TUI} -ex "target remote :${GDB_PORT:-3333}" -ex "load" ${ELF_NAME}
# will be called by trap
cleanup() {
OCD_PID="$(cat $OCD_PIDFILE)"
kill ${OCD_PID} &>/dev/null
rm -f "$OCD_PIDFILE"
exit 0
}
}
do_debugserver() {
test_config
sh -c "${OPENOCD_CMD} -f '${OPENOCD_CONFIG}' \
-c 'init' \
-c 'targets' \
-c 'reset halt'"
}
CMD="$1"
shift
if [ "$KBUILD_VERBOSE" -eq 1 ]
then
set -x
fi
case "${CMD}" in
flash)
echo "Flashing Target Device"
do_flash "$@"
;;
debugserver)
do_debugserver "$@"
;;
debug)
do_debug "$@"
;;
esac