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tests: kernel: interrupt: Add nested interrupt test for ARM GIC

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This commit adds the nested interrupt testing support for the ARM
Generic Interrupt Controller (GIC).

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-03-20 17:37:32 +09:00 • committed by Ioannis Glaropoulos
commit 9b81938c16
2 changed files with 43 additions and 2 deletions
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18
tests/kernel/interrupt/src/interrupt_util.h
View file

@ -60,6 +60,24 @@ static inline void trigger_irq(int irq)
#endif
}
#elif defined(CONFIG_GIC)
#include <drivers/interrupt_controller/gic.h>
static inline void trigger_irq(int irq)
{
printk("Triggering irq : %d\n", irq);
/* Ensure that the specified IRQ number is a valid SGI interrupt ID */
zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq);
/*
* Generate a software generated interrupt and forward it to the
* requesting CPU.
*/
sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
GICD_SGIR);
}
#elif defined(CONFIG_CPU_ARCV2)
static inline void trigger_irq(int irq)
{

27
tests/kernel/interrupt/src/nested_irq.c
View file

@ -8,6 +8,19 @@
#include <ztest.h>
#include "interrupt_util.h"
/*
* Run the nested interrupt test for the supported platforms only.
*
* NOTE: Cortex-A and Cortex-R platforms with the ARM GIC are skipped because
* the arch port for these architectures do not support interrupt
* nesting yet.
*/
#if defined(CONFIG_CPU_CORTEX_M) || defined(CONFIG_CPU_ARCV2) || \
(defined(CONFIG_GIC) && !defined(CONFIG_CPU_CORTEX_A) && \
!defined(CONFIG_CPU_CORTEX_R))
#define TEST_NESTED_ISR
#endif
#define DURATION 5
#define ISR0_TOKEN 0xDEADBEEF
@ -29,6 +42,16 @@
* The IRQ priorities start at 1 because the priority 0 is reserved for the
* SVCall exception and Zero-Latency IRQs (see `_EXCEPTION_RESERVED_PRIO`).
*/
#define IRQ0_PRIO 2
#define IRQ1_PRIO 1
#elif defined(CONFIG_GIC)
/*
* For the platforms that use the ARM GIC, use the SGI (software generated
* interrupt) lines 14 and 15 for testing.
*/
#define IRQ0_LINE 14
#define IRQ1_LINE 15
#define IRQ0_PRIO 2
#define IRQ1_PRIO 1
#else
@ -43,7 +66,7 @@
#define IRQ1_PRIO 0
#endif
#ifndef NO_TRIGGER_FROM_SW
#ifdef TEST_NESTED_ISR
static u32_t irq_line_0;
static u32_t irq_line_1;
@ -133,4 +156,4 @@ void test_nested_isr(void)
{
ztest_test_skip();
}
#endif /* NO_TRIGGER_FROM_SW */
#endif /* TEST_NESTED_ISR */