From 9b2ae5d02b255e9d8bc3d6feddcfceb2a561fb8f Mon Sep 17 00:00:00 2001
From: Daniel DeGrasse <daniel.degrasse@nxp.com>
Date: Wed, 1 May 2024 15:52:24 +0000
Subject: [PATCH] boards: nxp: mimxrt1050: enable PXP and apply optimized LVGL
 settings

Enable PXP on RT1050 EVK, and apply LVGL settings optimized for PXP
support. These settings will enable PXP rotation to function as expected
when using LVGL with the RT1050.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
---
 boards/nxp/mimxrt1050_evk/Kconfig.defconfig  | 23 +++++++++++++++++++-
 boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts |  4 ++++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig
index bfb4a84e341..1db4e04d777 100644
--- a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig
@@ -37,12 +37,33 @@ endif # NETWORKING
 
 if LVGL
 
+# LVGL should allocate buffers equal to size of display
 config LV_Z_VDB_SIZE
-	default 16
+	default 100
+
+# Enable double buffering
+config LV_Z_DOUBLE_VDB
+	default y
+
+# Force full refresh. This prevents memory copy associated with partial
+# display refreshes, which is not necessary for the eLCDIF driver
+config LV_Z_FULL_REFRESH
+	default y
 
 config LV_DPI_DEF
 	default 128
 
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+# Force display buffers to be aligned to cache line size (32 bytes)
+config LV_Z_VDB_ALIGN
+	default 32
+
+# Use offloaded render thread
+config LV_Z_FLUSH_THREAD
+	default y
+
 choice LV_COLOR_DEPTH
 	default LV_COLOR_DEPTH_16
 endchoice
diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts
index 9c441f051d1..4bd6b5bb441 100644
--- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts
+++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts
@@ -249,6 +249,10 @@ zephyr_udc0: &usb1 {
 	status = "okay";
 };
 
+&pxp {
+	status = "okay";
+};
+
 /* GPT and Systick are enabled. If power management is enabled, the GPT
  * timer will be used instead of systick, as allows the core clock to
  * be gated.