esp32: drivers: interrupt_controller: add interrupt allocation support
Add interrupt allocation support for ESP32. Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
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include/drivers/interrupt_controller/intc_esp32.h
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304
include/drivers/interrupt_controller/intc_esp32.h
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_ESP_INTR_ALLOC_H__
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#define ZEPHYR_INCLUDE_DRIVERS_ESP_INTR_ALLOC_H__
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#include <stdint.h>
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#include <stdbool.h>
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/* number of possible interrupts per core */
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#define ESP_INTC_INTS_NUM (32)
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/*
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* Interrupt allocation flags - These flags can be used to specify
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* which interrupt qualities the code calling esp_intr_alloc* needs.
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*
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*/
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/* Keep the LEVELx values as they are here; they match up with (1<<level) */
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#define ESP_INTR_FLAG_LEVEL1 (1<<1) /* Accept a Level 1 int vector, lowest priority */
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#define ESP_INTR_FLAG_LEVEL2 (1<<2) /* Accept a Level 2 int vector */
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#define ESP_INTR_FLAG_LEVEL3 (1<<3) /* Accept a Level 3 int vector */
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#define ESP_INTR_FLAG_LEVEL4 (1<<4) /* Accept a Level 4 int vector */
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#define ESP_INTR_FLAG_LEVEL5 (1<<5) /* Accept a Level 5 int vector */
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#define ESP_INTR_FLAG_LEVEL6 (1<<6) /* Accept a Level 6 int vector */
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#define ESP_INTR_FLAG_NMI (1<<7) /* Accept a Level 7 int vector, highest priority */
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#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
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#define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */
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#define ESP_INTR_FLAG_IRAM (1<<10) /* ISR can be called if cache is disabled */
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#define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */
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/* Low and medium prio interrupts. These can be handled in C. */
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#define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3)
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/* High level interrupts. Need to be handled in assembly. */
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#define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
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ESP_INTR_FLAG_NMI)
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/* Mask for all level flags */
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#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
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ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
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ESP_INTR_FLAG_NMI)
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/*
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* The esp_intr_alloc* functions can allocate an int for all *_INTR_SOURCE int sources that
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* are routed through the interrupt mux. Apart from these sources, each core also has some internal
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* sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
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* pass these pseudo-sources to the functions.
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*/
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#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Xtensa timer 0 interrupt source */
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#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Xtensa timer 1 interrupt source */
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#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Xtensa timer 2 interrupt source */
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#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
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#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
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#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
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/* Function prototype for interrupt handler function */
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typedef void (*intr_handler_t)(void *arg);
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struct shared_vector_desc_t {
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int disabled : 1;
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int source : 8;
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volatile uint32_t *statusreg;
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uint32_t statusmask;
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intr_handler_t isr;
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void *arg;
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struct shared_vector_desc_t *next;
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};
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/* Pack using bitfields for better memory use */
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struct vector_desc_t {
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int flags : 16; /* OR of VECDESC_FLAG_* defines */
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unsigned int cpu : 1;
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unsigned int intno : 5;
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int source : 8; /* Int mux flags, used when not shared */
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struct shared_vector_desc_t *shared_vec_info; /* used when VECDESC_FL_SHARED */
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struct vector_desc_t *next;
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};
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/** Interrupt handler associated data structure */
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struct intr_handle_data_t {
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struct vector_desc_t *vector_desc;
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struct shared_vector_desc_t *shared_vector_desc;
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};
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/**
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* @brief Initializes interrupt table to its defaults
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*/
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void esp_intr_initialize(void);
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/**
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* @brief Mark an interrupt as a shared interrupt
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*
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* This will mark a certain interrupt on the specified CPU as
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* an interrupt that can be used to hook shared interrupt handlers
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* to.
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*
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* @param intno The number of the interrupt (0-31)
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* @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
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* @param is_in_iram Shared interrupt is for handlers that reside in IRAM and
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* the int can be left enabled while the flash cache is disabled.
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*
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* @return -EINVAL if cpu or intno is invalid
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* 0 otherwise
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*/
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int esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
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/**
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* @brief Reserve an interrupt to be used outside of this framework
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*
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* This will mark a certain interrupt on the specified CPU as
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* reserved, not to be allocated for any reason.
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*
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* @param intno The number of the interrupt (0-31)
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* @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
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*
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* @return -EINVAL if cpu or intno is invalid
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* 0 otherwise
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*/
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int esp_intr_reserve(int intno, int cpu);
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/**
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* @brief Allocate an interrupt with the given parameters.
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*
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* This finds an interrupt that matches the restrictions as given in the flags
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* parameter, maps the given interrupt source to it and hooks up the given
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* interrupt handler (with optional argument) as well. If needed, it can return
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* a handle for the interrupt as well.
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*
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* The interrupt will always be allocated on the core that runs this function.
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*
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* If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or
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* RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned.
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*
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* @param source The interrupt source. One of the *_INTR_SOURCE interrupt mux
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* sources, as defined in esp-xtensa-intmux.h, or one of the internal
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* ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
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* @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
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* choice of interrupts that this routine can choose from. If this value
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* is 0, it will default to allocating a non-shared interrupt of level
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* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
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* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
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* from this function with the interrupt disabled.
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* @param handler The interrupt handler. Must be NULL when an interrupt of level >3
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* is requested, because these types of interrupts aren't C-callable.
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* @param arg Optional argument for passed to the interrupt handler
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* @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can
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* later be used to request details or free the interrupt. Can be NULL if no handle
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* is required.
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*
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* @return -EINVAL if the combination of arguments is invalid.
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* -ENODEV No free interrupt found with the specified flags
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* 0 otherwise
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*/
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int esp_intr_alloc(int source,
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int flags,
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intr_handler_t handler,
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void *arg,
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struct intr_handle_data_t **ret_handle);
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/**
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* @brief Allocate an interrupt with the given parameters.
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*
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*
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* This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
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* combo. For shared interrupts, the handler is only called if a read from the specified
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* register, ANDed with the mask, returns non-zero. By passing an interrupt status register
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* address and a fitting mask, this can be used to accelerate interrupt handling in the case
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* a shared interrupt is triggered; by checking the interrupt statuses first, the code can
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* decide which ISRs can be skipped
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*
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* @param source The interrupt source. One of the *_INTR_SOURCE interrupt mux
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* sources, as defined in esp-xtensa-intmux.h, or one of the internal
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* ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
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* @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
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* choice of interrupts that this routine can choose from. If this value
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* is 0, it will default to allocating a non-shared interrupt of level
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* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
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* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
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* from this function with the interrupt disabled.
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* @param intrstatusreg The address of an interrupt status register
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* @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
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* that are 1 in the mask set, the ISR will be called. If not, it will be
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* skipped.
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* @param handler The interrupt handler. Must be NULL when an interrupt of level >3
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* is requested, because these types of interrupts aren't C-callable.
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* @param arg Optional argument for passed to the interrupt handler
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* @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can
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* later be used to request details or free the interrupt. Can be NULL if no handle
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* is required.
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*
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* @return -EINVAL if the combination of arguments is invalid.
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* -ENODEV No free interrupt found with the specified flags
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* 0 otherwise
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*/
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int esp_intr_alloc_intrstatus(int source,
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int flags,
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uint32_t intrstatusreg,
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uint32_t intrstatusmask,
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intr_handler_t handler,
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void *arg,
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struct intr_handle_data_t **ret_handle);
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/**
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* @brief Disable and free an interrupt.
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*
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* Use an interrupt handle to disable the interrupt and release the resources associated with it.
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* If the current core is not the core that registered this interrupt, this routine will be
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* assigned to the core that allocated this interrupt, blocking and waiting until the resource
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* is successfully released.
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*
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* @note
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* When the handler shares its source with other handlers, the interrupt status bits
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* it's responsible for should be managed properly before freeing it. See ``esp_intr_disable``
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* for more details. Please do not call this function in ``esp_ipc_call_blocking``.
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*
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* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
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*
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* @return -EINVAL the handle is NULL
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* 0 otherwise
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*/
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int esp_intr_free(struct intr_handle_data_t *handle);
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/**
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* @brief Get CPU number an interrupt is tied to
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*
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* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
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*
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* @return The core number where the interrupt is allocated
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*/
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int esp_intr_get_cpu(struct intr_handle_data_t *handle);
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/**
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* @brief Get the allocated interrupt for a certain handle
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*
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* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
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*
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* @return The interrupt number
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*/
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int esp_intr_get_intno(struct intr_handle_data_t *handle);
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/**
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* @brief Disable the interrupt associated with the handle
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*
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* @note
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* 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
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* CPU the interrupt is allocated on. Other interrupts have no such restriction.
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* 2. When several handlers sharing a same interrupt source, interrupt status bits, which are
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* handled in the handler to be disabled, should be masked before the disabling, or handled
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* in other enabled interrupts properly. Miss of interrupt status handling will cause infinite
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* interrupt calls and finally system crash.
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*
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* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
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*
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* @return -EINVAL if the combination of arguments is invalid.
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* 0 otherwise
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*/
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int esp_intr_disable(struct intr_handle_data_t *handle);
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/**
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* @brief Enable the interrupt associated with the handle
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*
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* @note For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
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* CPU the interrupt is allocated on. Other interrupts have no such restriction.
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*
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* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
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*
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* @return -EINVAL if the combination of arguments is invalid.
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* 0 otherwise
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*/
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int esp_intr_enable(struct intr_handle_data_t *handle);
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/**
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* @brief Set the "in IRAM" status of the handler.
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*
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* @note Does not work on shared interrupts.
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*
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* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
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* @param is_in_iram Whether the handler associated with this handle resides in IRAM.
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* Handlers residing in IRAM can be called when cache is disabled.
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*
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* @return -EINVAL if the combination of arguments is invalid.
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* 0 otherwise
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*/
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int esp_intr_set_in_iram(struct intr_handle_data_t *handle, bool is_in_iram);
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/**
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* @brief Disable interrupts that aren't specifically marked as running from IRAM
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*/
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void esp_intr_noniram_disable(void);
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/**
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* @brief Re-enable interrupts disabled by esp_intr_noniram_disable
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*/
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void esp_intr_noniram_enable(void);
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#endif
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include/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
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include/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0 /* WiFi MAC, level */
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#define WIFI_MAC_NMI_SOURCE 1 /* WiFi MAC, NMI, use if MAC needs fix in NMI */
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#define WIFI_BB_INTR_SOURCE 2 /* WiFi BB, level, we can do some calibartion */
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#define BT_MAC_INTR_SOURCE 3 /* will be cancelled */
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#define BT_BB_INTR_SOURCE 4 /* BB, level */
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#define BT_BB_NMI_SOURCE 5 /* BT BB, NMI, use if BB have bug to fix in NMI */
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#define RWBT_INTR_SOURCE 6 /* RWBT, level */
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#define RWBLE_INTR_SOURCE 7 /* RWBLE, level */
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#define RWBT_NMI_SOURCE 8 /* RWBT, NMI, use if RWBT has bug to fix in NMI */
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#define RWBLE_NMI_SOURCE 9 /* RWBLE, NMI, use if RWBT has bug to fix in NMI */
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#define SLC0_INTR_SOURCE 10 /* SLC0, level */
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#define SLC1_INTR_SOURCE 11 /* SLC1, level */
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#define UHCI0_INTR_SOURCE 12 /* UHCI0, level */
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#define UHCI1_INTR_SOURCE 13 /* UHCI1, level */
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#define TG0_T0_LEVEL_INTR_SOURCE 14 /* TIMER_GROUP0, TIMER0, level */
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#define TG0_T1_LEVEL_INTR_SOURCE 15 /* TIMER_GROUP0, TIMER1, level */
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#define TG0_WDT_LEVEL_INTR_SOURCE 16 /* TIMER_GROUP0, WATCHDOG, level */
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#define TG0_LACT_LEVEL_INTR_SOURCE 17 /* TIMER_GROUP0, LACT, level */
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#define TG1_T0_LEVEL_INTR_SOURCE 18 /* TIMER_GROUP1, TIMER0, level */
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#define TG1_T1_LEVEL_INTR_SOURCE 19 /* TIMER_GROUP1, TIMER1, level */
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#define TG1_WDT_LEVEL_INTR_SOURCE 20 /* TIMER_GROUP1, WATCHDOG, level */
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#define TG1_LACT_LEVEL_INTR_SOURCE 21 /* TIMER_GROUP1, LACT, level */
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#define GPIO_INTR_SOURCE 22 /* interrupt of GPIO, level */
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#define GPIO_NMI_SOURCE 23 /* interrupt of GPIO, NMI */
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#define FROM_CPU_INTR0_SOURCE 24 /* int0 from a CPU, level */
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#define FROM_CPU_INTR1_SOURCE 25 /* int1 from a CPU, level */
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#define FROM_CPU_INTR2_SOURCE 26 /* int2 from a CPU, level, for DPORT Access */
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#define FROM_CPU_INTR3_SOURCE 27 /* int3 from a CPU, level, for DPORT Access */
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#define SPI0_INTR_SOURCE 28 /* SPI0, level, for $ Access, do not use this */
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#define SPI1_INTR_SOURCE 29 /* SPI1, level, flash r/w, do not use this */
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#define SPI2_INTR_SOURCE 30 /* SPI2, level */
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#define SPI3_INTR_SOURCE 31 /* SPI3, level */
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#define I2S0_INTR_SOURCE 32 /* I2S0, level */
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#define I2S1_INTR_SOURCE 33 /* I2S1, level */
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#define UART0_INTR_SOURCE 34 /* UART0, level */
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#define UART1_INTR_SOURCE 35 /* UART1, level */
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#define UART2_INTR_SOURCE 36 /* UART2, level */
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#define SDIO_HOST_INTR_SOURCE 37 /* SD/SDIO/MMC HOST, level */
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#define ETH_MAC_INTR_SOURCE 38 /* ethernet mac, level */
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#define PWM0_INTR_SOURCE 39 /* PWM0, level, Reserved */
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#define PWM1_INTR_SOURCE 40 /* PWM1, level, Reserved */
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#define PWM2_INTR_SOURCE 41 /* PWM2, level */
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#define PWM3_INTR_SOURCE 42 /* PWM3, level */
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#define LEDC_INTR_SOURCE 43 /* LED PWM, level */
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#define EFUSE_INTR_SOURCE 44 /* efuse, level, not likely to use */
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#define TWAI_INTR_SOURCE 45 /* twai, level */
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#define CAN_INTR_SOURCE TWAI_INTR_SOURCE
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#define RTC_CORE_INTR_SOURCE 46 /* rtc core, level, include rtc watchdog */
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#define RMT_INTR_SOURCE 47 /* remote controller, level */
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#define PCNT_INTR_SOURCE 48 /* pulse count, level */
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#define I2C_EXT0_INTR_SOURCE 49 /* I2C controller1, level */
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#define I2C_EXT1_INTR_SOURCE 50 /* I2C controller0, level */
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#define RSA_INTR_SOURCE 51 /* RSA accelerator, level */
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#define SPI1_DMA_INTR_SOURCE 52 /* SPI1 DMA, for flash r/w, do not use it */
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#define SPI2_DMA_INTR_SOURCE 53 /* SPI2 DMA, level */
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#define SPI3_DMA_INTR_SOURCE 54 /* interrupt of SPI3 DMA, level */
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#define WDT_INTR_SOURCE 55 /* will be cancelled */
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#define TIMER1_INTR_SOURCE 56 /* will be cancelled */
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#define TIMER2_INTR_SOURCE 57 /* will be cancelled */
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#define TG0_T0_EDGE_INTR_SOURCE 58 /* TIMER_GROUP0, TIMER0, EDGE */
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#define TG0_T1_EDGE_INTR_SOURCE 59 /* TIMER_GROUP0, TIMER1, EDGE */
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#define TG0_WDT_EDGE_INTR_SOURCE 60 /* TIMER_GROUP0, WATCH DOG, EDGE */
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#define TG0_LACT_EDGE_INTR_SOURCE 61 /* TIMER_GROUP0, LACT, EDGE */
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#define TG1_T0_EDGE_INTR_SOURCE 62 /* TIMER_GROUP1, TIMER0, EDGE */
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#define TG1_T1_EDGE_INTR_SOURCE 63 /* TIMER_GROUP1, TIMER1, EDGE */
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#define TG1_WDT_EDGE_INTR_SOURCE 64 /* TIMER_GROUP1, WATCHDOG, EDGE */
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#define TG1_LACT_EDGE_INTR_SOURCE 65 /* TIMER_GROUP0, LACT, EDGE */
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||||
#define MMU_IA_INTR_SOURCE 66 /* MMU Invalid Access, LEVEL */
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#define MPU_IA_INTR_SOURCE 67 /* MPU Invalid Access, LEVEL */
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#define CACHE_IA_INTR_SOURCE 68 /* Cache Invalid Access, LEVEL */
|
||||
#define MAX_INTR_SOURCE 69 /* total number of interrupt sources */
|
||||
|
||||
#endif
|
Loading…
Add table
Add a link
Reference in a new issue