diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c
index 80fa5b9c7f6..2e9609dfd6e 100644
--- a/boards/nxp/mimxrt700_evk/board.c
+++ b/boards/nxp/mimxrt700_evk/board.c
@@ -79,10 +79,6 @@ void board_early_init_hook(void)
 		.coarseTrimEn = true,
 	};
 
-#ifndef CONFIG_IMXRT7XX_CODE_CACHE
-	CACHE64_DisableCache(CACHE64_CTRL0);
-#endif
-
 	POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
 
 	/* Power up OSC */
diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig
index 8dcd7105337..a35c2dbd8ee 100644
--- a/soc/nxp/imxrt/imxrt7xx/Kconfig
+++ b/soc/nxp/imxrt/imxrt7xx/Kconfig
@@ -14,8 +14,13 @@ config SOC_MIMXRT798S_CM33_CPU0
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_MCUX
 	select HAS_MCUX_SYSCON
-	select HAS_MCUX_CACHE
+	select HAS_MCUX_XCACHE
+	select CACHE_MANAGEMENT
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
+	select INIT_ARCH_HW_AT_BOOT
 	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
 	select HAS_MCUX_FLEXCOMM
 
 config SOC_MIMXRT798S_CM33_CPU1
@@ -46,13 +51,6 @@ config GLIKEY_MCUX_GLIKEY
 	default y
 	bool "Use glikey MCUX Driver"
 
-config IMXRT7XX_CODE_CACHE
-	bool "Code cache"
-	default y if HAS_MCUX_CACHE
-	help
-	  Enable code cache for XSPI region at boot. If this Kconfig is
-	  cleared, the CACHE64 controller will be disabled during SOC init
-
 config MCUX_CORE_SUFFIX
 	default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0
 	default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1
diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
index 5d5466b182c..c7b1d1d4b05 100644
--- a/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
@@ -12,6 +12,10 @@ config NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 237500000 if CORTEX_M_SYSTICK
 
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 endif # SOC_MIMXRT798S_CM33_CPU0
 
 if SOC_MIMXRT798S_CM33_CPU1
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.c b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c
index d8675dd02db..5b88ac71644 100644
--- a/soc/nxp/imxrt/imxrt7xx/cm33/soc.c
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c
@@ -15,8 +15,18 @@
 #include <zephyr/init.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/linker/sections.h>
+#include <zephyr/cache.h>
 #include <soc.h>
 
+void soc_early_init_hook(void)
+{
+	/* Enable data cache */
+	sys_cache_data_enable();
+
+	__ISB();
+	__DSB();
+}
+
 #ifdef CONFIG_SOC_RESET_HOOK
 
 void soc_reset_hook(void)
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h
index 777c19f435c..92b4e3dd979 100644
--- a/soc/nxp/imxrt/imxrt7xx/cm33/soc.h
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h
@@ -20,6 +20,12 @@
 #include <zephyr/sys/util.h>
 #include <fsl_common.h>
 
+/* CPU 0 has an instruction and data cache, provide the defines for XCACHE */
+#ifdef CONFIG_SOC_MIMXRT798S_CM33_CPU0
+#define NXP_XCACHE_INSTR XCACHE1
+#define NXP_XCACHE_DATA XCACHE0
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif