tests: gen_isr_table: account for riscv32 architecture
Account for riscv32 SOCs supporting the riscv privileged architecture. Change-Id: I8c26a2bcc2baded5db252896abe6e1b5ab052113 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
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1 changed files with 22 additions and 4 deletions
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@ -17,15 +17,26 @@ extern uint32_t _irq_vector_table[];
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#define ISR1_OFFSET 0
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#define ISR2_OFFSET 1
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#if defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
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#define ISR3_OFFSET 1
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#define ISR4_OFFSET 5
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#define IRQ_LINE(offset) offset
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#define TABLE_INDEX(offset) offset
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#define TRIG_CHECK_SIZE 6
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#else
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#define ISR3_OFFSET 2
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#define ISR4_OFFSET 3
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#define IRQ_LINE(offset) (CONFIG_NUM_IRQS - ((offset) + 1))
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#define TABLE_INDEX(offset) (IRQ_TABLE_SIZE - ((offset) + 1))
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#define TRIG_CHECK_SIZE 4
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#endif
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#define ISR3_ARG 0xb01dface
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#define ISR4_ARG 0xca55e77e
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static volatile int trigger_check[4];
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static volatile int trigger_check[TRIG_CHECK_SIZE];
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#if defined(CONFIG_ARM)
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#include <arch/arm/cortex_m/cmsis.h>
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@ -39,8 +50,17 @@ void trigger_irq(int irq)
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
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void trigger_irq(int irq)
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{
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uint32_t mip;
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__asm__ volatile ("csrrs %0, mip, %1\n"
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: "=r" (mip)
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: "r" (1 << irq));
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}
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#else
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/* So far, Nios II and Risc V do not support this */
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/* So far, Nios II does not support this */
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#define NO_TRIGGER_FROM_SW
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#endif
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@ -202,5 +222,3 @@ done:
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TC_END_RESULT(rv);
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TC_END_REPORT(rv);
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}
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