drivers: gpio_cmsdk_ahb: update to use new GPIO API
Update driver code and board files to use new GPIO configuration flags such as GPIO_ACTIVE_LOW. Also add implementation of new port_* driver API as well as gpio_pin_interrupt_configure function. We treat GPIO_INT_MODE_LEVEL as not supported as the hardware doesn't seem to handle level interrupts as one would expect. Looking into this further to determine if its a HW bug or some misconfiguration in the software. We don't support dynamic setting of PULL_UP/PULL_DOWN config as this is handled by pinctrl for the current boards we support the CMSDK AHB driver on. Tested on musca-a board. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Carles Cufí
parent
30d0818179
commit
9aa1dc11ce
1 changed files with 114 additions and 31 deletions
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@ -23,6 +23,7 @@
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typedef void (*gpio_config_func_t)(struct device *port);
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struct gpio_cmsdk_ahb_cfg {
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struct gpio_driver_data common;
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volatile struct gpio_cmsdk_ahb *port;
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gpio_config_func_t gpio_config_func;
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/* GPIO Clock control in Active State */
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@ -40,50 +41,85 @@ struct gpio_cmsdk_ahb_dev_data {
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sys_slist_t gpio_cb;
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};
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static int gpio_cmsdk_ahb_port_get_raw(struct device *dev, u32_t *value)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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*value = cfg->port->data;
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return 0;
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}
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static int gpio_cmsdk_ahb_port_set_masked_raw(struct device *dev, u32_t mask,
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u32_t value)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout = (cfg->port->dataout & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_cmsdk_ahb_port_set_bits_raw(struct device *dev, u32_t mask)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout |= mask;
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return 0;
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}
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static int gpio_cmsdk_ahb_port_clear_bits_raw(struct device *dev, u32_t mask)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout &= ~mask;
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return 0;
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}
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static int gpio_cmsdk_ahb_port_toggle_bits(struct device *dev, u32_t mask)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout ^= mask;
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return 0;
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}
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static int cmsdk_ahb_gpio_config(struct device *dev, u32_t mask, int flags)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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if (((flags & GPIO_INPUT) == 0) && ((flags & GPIO_OUTPUT) == 0)) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/*
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* Setup the pin direction
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* Output Enable:
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* 0 - Input
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* 1 - Output
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*/
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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if ((flags & GPIO_OUTPUT) != 0) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_cmsdk_ahb_port_set_bits_raw(dev, mask);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_cmsdk_ahb_port_clear_bits_raw(dev, mask);
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}
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cfg->port->outenableset = mask;
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} else {
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cfg->port->outenableclr = mask;
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}
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/* Setup interrupt config */
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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return -ENOTSUP;
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} else {
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/*
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* Interrupt type:
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* 0 - LOW or HIGH level
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* 1 - For falling or rising
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*/
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if (flags & GPIO_INT_EDGE) {
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cfg->port->inttypeclr = mask;
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} else {
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cfg->port->inttypeset = mask;
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}
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/*
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* Interrupt polarity:
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* 0 - Low level or falling edge
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* 1 - High level or rising edge
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*/
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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cfg->port->intpolset = mask;
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} else {
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cfg->port->intpolclr = mask;
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}
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}
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}
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cfg->port->altfuncclr = mask;
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return 0;
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@ -202,6 +238,46 @@ static int gpio_cmsdk_ahb_read(struct device *dev, int access_op,
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return 0;
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}
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static int gpio_cmsdk_ahb_pin_interrupt_configure(struct device *dev,
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unsigned int pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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if (trig == GPIO_INT_TRIG_BOTH) {
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return -ENOTSUP;
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}
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/* For now treat level interrupts as not supported, as we seem to only
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* get a single 'edge' still interrupt rather than continuous
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* interrupts until the cause is cleared */
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if (mode == GPIO_INT_MODE_LEVEL) {
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return -ENOTSUP;
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}
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if (mode == GPIO_INT_MODE_DISABLED) {
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cfg->port->intenclr = BIT(pin);
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} else {
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if (mode == GPIO_INT_MODE_EDGE) {
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cfg->port->inttypeset = BIT(pin);
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} else {
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/* LEVEL */
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cfg->port->inttypeclr = BIT(pin);
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}
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/* Level High or Edge Risising */
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if (trig == GPIO_INT_TRIG_HIGH) {
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cfg->port->intpolset = BIT(pin);
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} else {
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cfg->port->intpolclr = BIT(pin);
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}
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cfg->port->intclear = BIT(pin);
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cfg->port->intenset = BIT(pin);
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}
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return 0;
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}
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static void gpio_cmsdk_ahb_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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@ -211,10 +287,11 @@ static void gpio_cmsdk_ahb_isr(void *arg)
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int_stat = cfg->port->intstatus;
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/* clear the port interrupts */
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cfg->port->intclear = int_stat;
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gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);
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/* clear the port interrupts */
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cfg->port->intclear = 0xFFFFFFFF;
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}
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static int gpio_cmsdk_ahb_manage_callback(struct device *dev,
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@ -274,6 +351,12 @@ static const struct gpio_driver_api gpio_cmsdk_ahb_drv_api_funcs = {
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.config = gpio_cmsdk_ahb_config,
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.write = gpio_cmsdk_ahb_write,
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.read = gpio_cmsdk_ahb_read,
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.port_get_raw = gpio_cmsdk_ahb_port_get_raw,
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.port_set_masked_raw = gpio_cmsdk_ahb_port_set_masked_raw,
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.port_set_bits_raw = gpio_cmsdk_ahb_port_set_bits_raw,
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.port_clear_bits_raw = gpio_cmsdk_ahb_port_clear_bits_raw,
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.port_toggle_bits = gpio_cmsdk_ahb_port_toggle_bits,
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.pin_interrupt_configure = gpio_cmsdk_ahb_pin_interrupt_configure,
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.manage_callback = gpio_cmsdk_ahb_manage_callback,
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.enable_callback = gpio_cmsdk_ahb_enable_callback,
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.disable_callback = gpio_cmsdk_ahb_disable_callback,
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