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soc: arm: st_stm32: update HSEM ID for stm32 hsem ipm

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New hardware semaphore ID for inter-processor mailbox

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
This commit is contained in:
HaiLong Yang 2021-08-03 09:19:10 +08:00 • committed by Carles Cufí
commit 9a80196e28
1 changed files with 8 additions and 0 deletions
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8
soc/arm/st_stm32/common/stm32_hsem.h
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@ -69,6 +69,12 @@
/** Index of the semaphore used to access the EXTI */ /** Index of the semaphore used to access the EXTI */
#define CFG_HW_EXTI_SEMID 9U #define CFG_HW_EXTI_SEMID 9U
/** Index of the semaphore for CPU1 mailbox */
#define CFG_HW_IPM_CPU1_SEMID 10U
/** Index of the semaphore for CPU2 mailbox */
#define CFG_HW_IPM_CPU2_SEMID 11U
#elif defined(CONFIG_SOC_SERIES_STM32MP1X) #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
/** HW semaphore from STM32MP1 /** HW semaphore from STM32MP1
* EXTI and GPIO are inherited from STM32MP1 Linux. * EXTI and GPIO are inherited from STM32MP1 Linux.
@ -94,6 +100,8 @@
#define CFG_HW_RNG_SEMID 0U #define CFG_HW_RNG_SEMID 0U
#define CFG_HW_GPIO_SEMID 0U #define CFG_HW_GPIO_SEMID 0U
#define CFG_HW_EXTI_SEMID 0U #define CFG_HW_EXTI_SEMID 0U
#define CFG_HW_IPM_CPU1_SEMID 0U
#define CFG_HW_IPM_CPU2_SEMID 0U
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE */ #endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE */