qmspi: update MEC172x qmspi module for pinctrl
Changes to qmspi module to support pinctrl Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This commit is contained in:
Jay Vasanth
Carles Cufí
parent
156440f3f0
commit
99c89ebb78
2 changed files with 18 additions and 155 deletions
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@ -12,7 +12,9 @@ LOG_MODULE_REGISTER(spi_xec, CONFIG_SPI_LOG_LEVEL);
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#include <errno.h>
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#include <device.h>
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#include <drivers/clock_control/mchp_xec_clock_control.h>
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#include <drivers/gpio.h>
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#include <drivers/interrupt_controller/intc_mchp_xec_ecia.h>
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#include <drivers/pinctrl.h>
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#include <drivers/pinmux.h>
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#include <drivers/spi.h>
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#include <dt-bindings/interrupt-controller/mchp-xec-ecia.h>
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@ -79,6 +81,7 @@ struct spi_qmspi_config {
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uint8_t chip_sel;
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uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
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uint8_t unused[2];
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const struct pinctrl_dev_config *pcfg;
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void (*irq_config_func)(void);
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};
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@ -107,156 +110,6 @@ struct xec_qmspi_pin {
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uint32_t attrib;
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};
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/* QMSPI pin tables by port and chip select
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* MEC172x port 0 (SHD SPI) supports quad and two chip selects
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* port 1 named PVT(private) supports quad and one chip select
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* port 2 named GP(general purpose) is internal to the package and supports
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* one chip select and only two I/O pins.
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*/
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#define XEC_QMSPI_PORT \
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DT_PROP_OR(DT_INST(0, microchip_xec_qmspi_ldma), port-sel, 0)
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#define XEC_QMSPI_LINES \
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DT_PROP_OR(DT_INST(0, microchip_xec_qmspi_ldma), lines, 1)
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#define XEC_QMSPI_CS \
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DT_PROP_OR(DT_INST(0, microchip_xec_qmspi_ldma), chip-select, 0)
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#if XEC_QMSPI_PORT == 1
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const struct xec_qmspi_pin xec_qmspi_pin_tbl[] = {
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_124,
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.attrib = MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_125,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_121,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_122,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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#if XEC_QMSPI_LINES == 4
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_123,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_126,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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#endif
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};
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#elif XEC_QMSPI_PORT == 2
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/*
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* MEC172x packages with internal SPI flash use SST25PF040C which does not
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* support quad operation. The WP#(IO2) and HOLD#(IO3) are not pulled high
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* internally. We must drive them high.
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*/
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const struct xec_qmspi_pin xec_qmspi_pin_tbl[] = {
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_036)),
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.pin = MCHP_GPIO_116,
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.attrib = MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_100_136)),
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.pin = MCHP_GPIO_117,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_040_076)),
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.pin = MCHP_GPIO_074,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_040_076)),
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.pin = MCHP_GPIO_075,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{ /* IO2 = WP# */
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_040_076)),
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.pin = MCHP_GPIO_076,
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.attrib = MCHP_GPIO_CTRL_MUX_GPIO | MCHP_GPIO_CTRL_OUTV_HI,
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},
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{ /* IO3 = HOLD# */
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_000_036)),
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.pin = MCHP_GPIO_034,
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.attrib = MCHP_GPIO_CTRL_MUX_GPIO | MCHP_GPIO_CTRL_OUTV_HI,
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}
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};
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#else /* default to port 0 SHD_SPI */
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const struct xec_qmspi_pin xec_qmspi_pin_tbl[] = {
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#if XEC_QMSPI_CS == 0
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_040_076)),
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.pin = MCHP_GPIO_055,
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.attrib = MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN,
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},
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#else
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_000_036)),
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.pin = MCHP_GPIO_002,
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.attrib = MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN,
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},
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#endif
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_040_076)),
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.pin = MCHP_GPIO_056,
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.attrib = MCHP_GPIO_CTRL_MUX_F2,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_200_236)),
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.pin = MCHP_GPIO_223,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_200_236)),
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.pin = MCHP_GPIO_224,
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.attrib = MCHP_GPIO_CTRL_MUX_F2,
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},
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#if XEC_QMSPI_LINES == 4
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_200_236)),
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.pin = MCHP_GPIO_227,
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.attrib = MCHP_GPIO_CTRL_MUX_F1,
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},
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{
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.dev = DEVICE_DT_GET(DT_NODELABEL(pinmux_000_036)),
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.pin = MCHP_GPIO_016,
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.attrib = MCHP_GPIO_CTRL_MUX_F2,
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},
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#endif
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};
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#endif
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/* Configure pins for QMSPI port selected at build time */
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static int xec_qspi_config_port(void)
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{
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for (size_t n = 0; n < ARRAY_SIZE(xec_qmspi_pin_tbl); n++) {
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const struct xec_qmspi_pin *pin = &xec_qmspi_pin_tbl[n];
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if (!device_is_ready(pin->dev)) {
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return -ENODEV;
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}
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pinmux_pin_set(pin->dev, pin->pin, pin->attrib);
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}
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return 0;
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}
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static int xec_qmspi_spin_yield(int *counter, int max_count)
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{
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@ -1232,7 +1085,7 @@ static int qmspi_xec_init(const struct device *dev)
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const struct spi_qmspi_config *cfg = dev->config;
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struct spi_qmspi_data *qdata = dev->data;
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struct qmspi_regs *regs = cfg->regs;
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int ret;
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qdata->qstatus = 0;
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qdata->np = cfg->width;
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#ifdef CONFIG_SPI_ASYNC
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@ -1242,14 +1095,14 @@ static int qmspi_xec_init(const struct device *dev)
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qdata->xfr_len = 0;
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#endif
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int ret = xec_qspi_config_port();
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z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0);
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret != 0) {
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LOG_ERR("QSPI pinctrl setup failed (%d)", ret);
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return ret;
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}
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z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0);
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qmspi_reset(regs);
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mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
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@ -1305,6 +1158,9 @@ static const struct spi_driver_api spi_qmspi_xec_driver_api = {
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* order the DT tools process all DT files in a build.
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*/
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#define QMSPI_XEC_DEVICE(i) \
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\
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PINCTRL_DT_INST_DEFINE(i); \
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\
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static void qmspi_xec_irq_config_func_##i(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(i), \
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@ -1334,6 +1190,7 @@ static const struct spi_driver_api spi_qmspi_xec_driver_api = {
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.chip_sel = DT_INST_PROP_OR(i, chip-select, 0), \
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.width = DT_INST_PROP_OR(0, lines, 1), \
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.irq_config_func = qmspi_xec_irq_config_func_##i, \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
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}; \
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DEVICE_DT_INST_DEFINE(i, &qmspi_xec_init, NULL, \
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&qmspi_xec_data_##i, &qmspi_xec_config_##i, \
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@ -6,7 +6,7 @@ description: Microchip XEC QMSPI controller with local DMA
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compatible: "microchip,xec-qmspi-ldma"
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include: spi-controller.yaml
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include: [spi-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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@ -28,6 +28,12 @@ properties:
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A two entry integer array containing the QMSPI PCR sleep register
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index and bit position.
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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lines:
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type: int
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required: false
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